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  /src/sys/arch/arm/nvidia/
tegra_mcreg.h 85 #define MC_SMMU_TRANSLATION_ENABLE_2_REG 0x230
tegra210_pinmux.c 201 TEGRA_PIN("button_power_on_px5", 0x230, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
tegra_hdmireg.h 301 #define HDMI_NV_PDISP_AUDIO_N_REG 0x230
  /src/sys/dev/ic/
igpioreg.h 213 { "INTC3001", 0, 0, 167, 0x200, 0x230 },
214 { "INTC3001", 1, 168, 236, 0x200, 0x230 },
mvsatareg.h 174 #define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_lrc.h 40 #define RING_ELSP(base) _MMIO((base) + 0x230)
  /src/sys/dev/gpib/
rdreg.h 77 #define RD2203AID 0x230 /* yet another guess */
  /src/sys/arch/arm/samsung/
exynos_reg.h 189 #define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230
exynos_usbphy.c 49 #define USB20PHY_CFG 0x230
  /src/sys/arch/powerpc/include/mpc8xx/
spr.h 43 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
  /src/sys/dev/eisa/
bha_eisa.c 77 port = 0x230;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
trinityd.h 172 #define SMC_RESP_0 0x230
  /src/sys/arch/arm/marvell/
mv78xx0reg.h 180 #define MV78XX0_ICI_EIMLR 0x230 /* Endpoint Intr Mask Low */
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
am4.h 19 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
120 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 167 #define GPMC_TESTMODE_CTRL 0x230
  /src/sys/arch/sparc64/dev/
ffbreg.h 163 #define FFB_FBC_DCSF 0x230
  /src/sys/dev/isa/
dpt_isa.c 72 static const int dpt_isa_iobases[] = { 0x230, 0x330, 0x1f0, 0x170, 0 };
essreg.h 166 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 325 0x230 MODE_NITRO /* drdu2_vbus_ppc */
  /src/sys/arch/hp300/dev/
rdreg.h 122 #define RD2203AID 0x230 /* yet another guess */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mp-pinfunc.h 752 #define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6
753 #define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0
754 #define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0
755 #define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4
756 #define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0
757 #define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1
758 #define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0
759 #define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0
  /src/sys/arch/powerpc/include/oea/
spr.h 119 #define SPR_IBAT4U 0x230 /* ..6. Instruction BAT Reg 4 Upper */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap2430.dtsi 70 reg = <0x230 0x4>;
imx25-pinfunc.h 25 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
26 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
27 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
28 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210.h 64 #define INIT_SIFS 0x230 /* = 16 us - 2 us */

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