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  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_lrc.h 41 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
42 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
  /src/sys/arch/arm/nvidia/
tegra_mcreg.h 86 #define MC_SMMU_TRANSLATION_ENABLE_3_REG 0x234
tegra210_pinmux.c 202 TEGRA_PIN("button_vol_up_px6", 0x234, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/dev/pci/
pciide_sis_reg.h 111 {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214};
  /src/sys/dev/eisa/
bha_eisa.c 80 port = 0x234;
  /src/sys/arch/arm/marvell/
mv78xx0reg.h 181 #define MV78XX0_ICI_EIMHR 0x234 /* Endpoint Intr Mask High */
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 168 #define GPMC_PSA_LSB 0x234
  /src/sys/arch/sparc64/dev/
ffbreg.h 164 #define FFB_FBC_DCSB 0x234
  /src/sys/dev/ic/
mvsatareg.h 175 #define DMA_DRLA 0x234 /* Data Region Low Address */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 326 0x234 MODE_NITRO /* drdu2_vbus_present */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mp-pinfunc.h 760 #define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0
761 #define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7
762 #define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5
763 #define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0
764 #define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0
765 #define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1
766 #define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2
767 #define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0
imx8mm-pinfunc.h 600 #define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
601 #define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
602 #define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
603 #define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
604 #define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
imx8mq-pinfunc.h 568 #define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
569 #define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
570 #define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
571 #define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
572 #define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
imx8mn-pinfunc.h 603 #define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
604 #define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
605 #define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
606 #define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
  /src/sys/arch/powerpc/include/oea/
spr.h 123 #define SPR_IBAT6U 0x234 /* ..6. Instruction BAT Reg 6 Upper */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
imx25-pinfunc.h 30 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
31 #define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x05 0x000
32 #define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x06 0x000
33 #define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x07 0x000
imx35-pinfunc.h 589 #define MX35_PAD_SD1_CLK__ESDHC1_CLK 0x234 0x698 0x000 0x0 0x0
590 #define MX35_PAD_SD1_CLK__MSHC_BS 0x234 0x698 0x000 0x1 0x0
591 #define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK 0x234 0x698 0x000 0x3 0x0
592 #define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 0x234 0x698 0x9b8 0x4 0x0
593 #define MX35_PAD_SD1_CLK__GPIO1_7 0x234 0x698 0x85c 0x5 0x2
594 #define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK 0x234 0x698 0x000 0x7 0x0
imx6dl-pinfunc.h 756 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
757 #define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609
758 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
759 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
760 #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
761 #define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
imx6q-pinfunc.h 680 #define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
681 #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
682 #define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
683 #define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
684 #define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
imx6sl-pinfunc.h 889 #define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0
890 #define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2
891 #define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2
892 #define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0
893 #define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0
hi3620-hi4511.dts 526 0x234 0 /* KEY_OUT1 (IOCFG149) */
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_d.h 164 #define ixCLIENT1_K2 0x234
oss_3_0_d.h 233 #define ixCLIENT1_K2 0x234
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
execlist.c 43 #define _EL_OFFSET_STATUS 0x234
  /src/sys/arch/powerpc/include/booke/
etsecreg.h 259 #define TBASE6 0x234 /* TxBD base address of ring 6 [TSEC3] */

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