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  /src/sys/arch/acorn32/mainbus/
piocreg.h 122 #define PIOC_COM4_OFFSET 0x238
  /src/sys/arch/arm/nvidia/
tegra_mcreg.h 87 #define MC_SMMU_AFI_ASID_REG 0x238
tegra210_pinmux.c 203 TEGRA_PIN("button_vol_down_px7", 0x238, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/arch/x86/pci/
lpssreg.h 66 #define LPSS_CLKGATE 0x238
  /src/sys/dev/isa/
isareg.h 76 #define IO_BMS2 0x238 /* secondary InPort Bus Mouse */
  /src/sys/arch/arm/marvell/
mv78xx0reg.h 182 #define MV78XX0_ICI_ESCR 0x238 /* Endpoint Select Cause */
  /src/sys/arch/powerpc/include/mpc8xx/
spr.h 56 #define SPR_DC_CST 0x238 /* ..8 Data Cache CSR */
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
am4.h 66 #define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 166 #define GPMC_PSA_MSB 0x238
  /src/sys/arch/sparc64/dev/
ffbreg.h 165 #define FFB_FBC_DCZF 0x238
  /src/sys/dev/ic/
mvsatareg.h 176 #define DMA_DRHA 0x238 /* Data Region High Address */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 327 0x238 MODE_NITRO /* drdu2_id */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mp-pinfunc.h 768 #define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8
769 #define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0
770 #define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0
771 #define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4
772 #define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1
773 #define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0
774 #define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2
775 #define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0
imx8mm-pinfunc.h 606 #define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
607 #define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1
608 #define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
609 #define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
610 #define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
imx8mq-pinfunc.h 573 #define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
574 #define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
575 #define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
576 #define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
577 #define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
imx8mn-pinfunc.h 607 #define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
608 #define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1
609 #define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
610 #define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
  /src/sys/arch/powerpc/include/oea/
spr.h 128 #define SPR_DBAT4U 0x238 /* ..6. Data BAT Reg 4 Upper */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h 110 #define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
111 #define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
112 #define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
113 #define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
114 #define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
115 #define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
imx25-pinfunc.h 40 #define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x00 0x000
41 #define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x05 0x000
42 #define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x06 0x000
43 #define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x07 0x000
imx6dl-pinfunc.h 762 #define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
763 #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
764 #define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
765 #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
766 #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
767 #define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
768 #define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
769 #define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
770 #define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
imxrt1170-pinfunc.h 1487 #define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0
1488 #define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0
1489 #define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1
1490 #define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1
1491 #define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0
1492 #define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1
1493 #define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0
1494 #define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1
1495 #define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2
imx35-pinfunc.h 595 #define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x238 0x69c 0x000 0x0 0x0
596 #define MX35_PAD_SD1_DATA0__MSHC_DATA_0 0x238 0x69c 0x000 0x1 0x0
597 #define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 0x238 0x69c 0x000 0x3 0x0
598 #define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 0x238 0x69c 0x9bc 0x4 0x0
599 #define MX35_PAD_SD1_DATA0__GPIO1_8 0x238 0x69c 0x860 0x5 0x2
600 #define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 0x238 0x69c 0x000 0x7 0x0
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 211 0x238: _060LSP__ftwotoxx_
  /src/sys/arch/mips/cavium/dev/
octeon_gmxreg.h 72 #define GMX0_TX0_PAUSE_PKT_TIME 0x238
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_d.h 165 #define ixCLIENT1_K3 0x238

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