| /src/sys/external/bsd/compiler_rt/dist/lib/builtins/ |
| popcountti2.c | 24 tu_int x3 = (tu_int)a; local in function:__popcountti2
25 x3 = x3 - ((x3 >> 1) & (((tu_int)0x5555555555555555uLL << 64) |
28 x3 = ((x3 >> 2) & (((tu_int)0x3333333333333333uLL << 64) | 0x3333333333333333uLL))
29 + (x3 & (((tu_int)0x3333333333333333uLL << 64) | 0x3333333333333333uLL));
31 x3 = (x3 + (x3 >> 4)
[all...] |
| /src/sys/dev/pci/ |
| pciide_acard_reg.h | 37 static const u_int8_t acard_act_udma[] = {0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3};
39 static const u_int8_t acard_act_dma[] = {0x0, 0x3, 0x3};
40 static const u_int8_t acard_rec_dma[] = {0xa, 0x3, 0x1}
[all...] |
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/mux/ |
| ti-serdes.h | 16 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
21 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
26 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
31 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
36 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
41 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
46 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
51 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
56 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
61 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all...] |
| /src/sys/stand/efiboot/bootaa64/ |
| cache.S | 45 * in x1. It will corrupt x0, x1, x2, and x3.
49 mrs x3, ctr_el0
50 ubfx x3, x3, #16, #4 /* x3 = D cache shift */
52 lsl x3, x2, x3 /* x3 = D cache line size */
54 mrs x3, ctr_el0
55 ubfx x2, x3, #16, #4 /* x2 = D cache shift *
[all...] |
| /src/sys/arch/hp300/dev/ |
| rtcreg.h | 44 #define RTC_REG5_HOUR 0x3
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| ni_reg.h | 32 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)
37 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
46 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)
50 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)
63 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)
67 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)
68 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
69 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12)
72 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0)
77 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4
[all...] |
| si_reg.h | 36 # define SI_GRPH_DEPTH(x) (((x) & 0x3) << 0)
40 # define SI_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
45 # define SI_GRPH_Z(x) (((x) & 0x3) << 4)
46 # define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
70 # define SI_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
83 # define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
|
| /src/sys/arch/arm/cortex/ |
| gic_splfuncs_armv8.S | 36 ldr w1, [x3, #L_NOPREEMPT]; \
38 str w1, [x3, #L_NOPREEMPT]
40 ldr w1, [x3, #L_NOPREEMPT]; \
42 str w1, [x3, #L_NOPREEMPT]
56 /* Save curlwp in x3, curcpu in x1 */
57 mrs x3, tpidr_el1 /* get curlwp */
59 ldr x1, [x3, #L_CPU] /* get curcpu */
82 /* Save curlwp in x3, curcpu in x1 */
83 mrs x3, tpidr_el1 /* get curlwp */
85 ldr x1, [x3, #L_CPU] /* get curcpu *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_gpu_commands.h | 27 #define INSTR_RC_CLIENT 0x3
176 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
178 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
180 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
181 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
185 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
186 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
191 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
192 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
193 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0
[all...] |
| /src/sys/arch/pmax/pmax/ |
| pmaxtype.h | 43 #define DS_3MIN 0x3 /* DECstation 5000/1xx */
|
| /src/sys/dev/isa/ |
| tsdioreg.h | 34 #define TSDIO_INTCTL 0x3
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/sound/ |
| adi,adau1977.h | 10 #define ADAU1977_MICBIAS_6V5 0x3
|
| /src/lib/libc/arch/aarch64/gen/ |
| sigsetjmp.S | 49 ldr x3, [x0, #_JB_MAGIC]
50 tbnz x3, #0, _C_LABEL(__longjmp14)
|
| swapcontext.S | 48 mov x3, x0 /* save return value */
61 cbnz x3, 1f
64 mov x0, x3 /* restore getcontext return value */
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/soc/ |
| qcom,apr.h | 10 #define APR_DOMAIN_MODEM 0x3
16 #define APR_SVC_ADSP_CORE 0x3
|
| /src/sys/arch/hpcmips/vr/ |
| bcureg.h | 54 #define BCUCNT1_ROMSMASK (0x3<<14) /* ROM SIZE (=4181) */
116 #define BCUCNT1_RTYPE (0x3<<1) /* ROM type (=4181) */
166 #define BCUROMSPEED_PATIME (0x3<<12) /* Page Access time */
167 #define BCUROMSPEED_PATIME_5VT (0x3<<12) /* 5VTClock */
185 #define BCUROMSPEED_ATIME_6VT (0x3) /* 6VTClock */
193 #define BCUIO0SPEED_RWCS (0x3<<12) /* R/W - CS time */
194 #define BCUIO0SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
212 #define BCUIO0SPEED_RDYRW_6VT (0x3) /* 6VTClock */
230 #define BCUIO0SPEED_RWRDY_2VT (0x3) /* 2VTClock */
248 #define BCUIO0SPEED_CSRW_4VT (0x3) /* 4VTClock *
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| pmi8998.dtsi | 25 reg = <0x3 SPMI_USID>;
33 interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
34 <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>;
39 interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
40 <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
|
| /src/sys/arch/x86/pci/ |
| lpssreg.h | 37 #define LPSS_RESET_CTRL_REL 0x3
42 #define LPSS_ACTIVELTR_SSCALE_32 (0x3 << 10)
48 #define LPSS_IDLELTR_SSCALE_32 (0x3 << 10)
70 #define LPSS_CLKGATE_DMA_ON (0x3 << 2)
74 #define LPSS_CLKGATE_CTRL_ON (0x3 << 0)
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx7ulp-pinfunc.h | 43 #define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
51 #define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
59 #define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
73 #define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
81 #define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
89 #define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
97 #define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
104 #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
112 #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
121 #define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x
[all...] |
| /src/common/lib/libc/arch/aarch64/string/ |
| memcmp.S | 48 ands x3, x9, #7
54 add x2, x2, x3 /* add unalignment to length */
57 sub x9, x9, x3 /* dword align src1 */
60 sub x10, x10, x3 /* src2 -= x3 */
61 lsl x3, x3, #3 /* convert bytes to bits */
64 lsl x4, x4, x3 /* discard leading bytes from data1 */
65 lsr x6, x6, x3 /* discard leading bytes from data2 */
66 lsl x6, x6, x3 /* get back bit position *
[all...] |
| /src/sys/arch/mips/alchemy/dev/ |
| auspireg.h | 47 #define SPICFG_RT_8 (0x3 << 30)
51 #define SPICFG_TT_8 (0x3 << 28)
59 #define SPICFG_DIV_MASK (0x3 << 13) /* psc clock divider */
|
| /src/sys/arch/aarch64/aarch64/ |
| pmap_page.S | 53 mov x3, #4
54 lsl x3, x3, x2
57 add x0, x0, x3
86 1: ldnp x2, x3, [x0, #0]
91 stnp x2, x3, [x1, #0]
|
| /src/sys/dev/nand/ |
| nand_toshiba.c | 43 NAND_TOSHIBA_PAGEMASK = 0x3,
45 NAND_TOSHIBA_BLOCKMASK = 0x3 << 4,
50 NAND_TOSHIBA_PLANENUMMASK = 0x3 << 2
92 case 0x3:
113 case 0x3:
141 case 0x3:
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/ |
| vce_2_0_sh_mask.h | 80 #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
82 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
84 #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
89 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3
93 #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3
97 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3
|
| /src/lib/libc/arch/aarch64/sys/ |
| __syscall.S | 62 mov x2, x3
63 mov x3, x4
|
