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  /src/share/locale/ctype/charset/
Latin-6+ 10 ALPHA 0x40 - 0x4f 0x60 - 0x6f
11 GRAPH 0x20 0x30 0x40 - 0x4f 0x60 - 0x6f
14 UPPER 0x40 - 0x4f
16 PRINT 0x20 0x30 0x40 - 0x4f 0x60 - 0x6f
19 MAPLOWER < 0x40 - 0x4f : 0x60 >
22 MAPUPPER < 0x40 - 0x4f : 0x40 >
23 MAPUPPER < 0x60 - 0x6f : 0x40 >
Latin-1 8 ALPHA 0x40 - 0x56 0x58 - 0x76 0x78 - 0x7f
13 UPPER 0x40 - 0x56 0x58 - 0x5f
18 MAPLOWER < 0x40 - 0x56 : 0x60 >
23 MAPUPPER < 0x40 - 0x56 : 0x40 >
25 MAPUPPER < 0x60 - 0x76 : 0x40 >
Latin-5 10 ALPHA 0x40 - 0x56 0x58 - 0x5f
16 UPPER 0x40 - 0x56 0x58 - 0x5f
21 MAPLOWER < 0x40 - 0x56 : 0x60 >
26 MAPUPPER < 0x40 - 0x56 : 0x40 >
28 MAPUPPER < 0x60 - 0x76 : 0x40 >
Latin-Greek 11 ALPHA 0x40 - 0x51 0x53 - 0x7e
14 LOWER 0x72 0x40 0x60
22 MAPLOWER < 0x40 - 0x56 : 0x60 >
27 MAPUPPER < 0x40 - 0x56 : 0x40 >
29 MAPUPPER < 0x60 - 0x76 : 0x40 >
  /src/sys/arch/x86/pci/
amd8131reg.h 8 #define AMD8131_PCIX_MISC 0x40
  /src/sys/dev/mca/
mcareg.h 43 #define MCA_POS5_CHCK_STAT 0x40 /* POS5, lo => CHCK status available */
  /src/sys/arch/acorn32/eb7500atx/
rsidereg.h 46 #define DRIVE_REGISTERS_SPACE (8 * 0x40)
47 #define DRIVE_REGISTER_BYTE_SPACING (0x40)
  /src/sys/arch/x68k/dev/
opmvar.h 39 #define OPM1B_CT2MSK (0x40)
45 #define FDCRDY (0x40)
mb86601reg.h 44 #define PSNS_ACK 0x40
  /src/sys/arch/hp300/hp300/
leds.h 44 #define LED_LANRCV 0x40 /* for LAN receive activity */
  /src/sys/arch/sun2/sun2/
buserr.h 36 #define BUSERR_VMEBUSERR 0x40 /* bus error signaled on VMEbus */
  /src/sys/dev/i2o/
iopreg.h 37 #define IOP_REG_IFIFO 0x40 /* Inbound FIFO (to IOP) */
  /src/sys/arch/news68k/dev/
ms_hbreg.h 40 #define MSSTAT_RDY 0x40 /* mouse Rx data ready */
  /src/sys/arch/arm/nvidia/
tegra_apbdmareg.h 59 #define APBDMACHAN_CSR_REG(n) (0x1000 + ((n) * 0x40))
67 #define APBDMACHAN_STA_REG(n) (0x1004 + ((n) * 0x40))
68 #define APBDMACHAN_DMA_BYTE_STA_REG(n) (0x1008 + ((n) * 0x40))
69 #define APBDMACHAN_CSRE_REG(n) (0x100c + ((n) * 0x40))
70 #define APBDMACHAN_AHB_PTR_REG(n) (0x1010 + ((n) * 0x40))
72 #define APBDMACHAN_AHB_SEQ_REG(n) (0x1014 + ((n) * 0x40))
91 #define APBDMACHAN_APB_PTR_REG(n) (0x1018 + ((n) * 0x40))
93 #define APBDMACHAN_APB_SEQ_REG(n) (0x101c + ((n) * 0x40))
108 #define APBDMACHAN_WCOUNT_REG(n) (0x1020 + ((n) * 0x40))
109 #define APBDMACHAN_WORD_REG(n) (0x1024 + ((n) * 0x40))
    [all...]
  /src/sys/dev/wsfont/
spleen5x8.h 95 0x40, /* .*...... */
120 0x40, /* .*...... */
121 0x40, /* .*...... */
122 0x40, /* .*...... */
123 0x40, /* .*...... */
127 0x40, /* .*...... */
134 0x40, /* .*...... */
161 0x40, /* .*...... */
185 0x40, /* .*...... */
186 0x40, /* .*...... *
    [all...]
  /src/sys/dev/pci/ixgbe/
ixgbe_vf.h 66 #define IXGBE_VFRDBAL(x) (0x01000 + (0x40 * (x)))
67 #define IXGBE_VFRDBAH(x) (0x01004 + (0x40 * (x)))
68 #define IXGBE_VFRDLEN(x) (0x01008 + (0x40 * (x)))
69 #define IXGBE_VFRDH(x) (0x01010 + (0x40 * (x)))
70 #define IXGBE_VFRDT(x) (0x01018 + (0x40 * (x)))
71 #define IXGBE_VFRXDCTL(x) (0x01028 + (0x40 * (x)))
72 #define IXGBE_VFSRRCTL(x) (0x01014 + (0x40 * (x)))
73 #define IXGBE_VFRSCCTL(x) (0x0102C + (0x40 * (x)))
75 #define IXGBE_VFTDBAL(x) (0x02000 + (0x40 * (x)))
76 #define IXGBE_VFTDBAH(x) (0x02004 + (0x40 * (x))
    [all...]
  /src/sys/dev/ic/
mc6854reg.h 33 #define MC6854_CR1_RX_RS 0x40 /* Receiver Reset */
45 #define MC6854_CR2_CLR_TX_ST 0x40 /* Clear Transmitter Status */
58 #define MC6854_CR3_GAP_TST 0x40 /* Go Active On Poll/Test */
76 #define MC6854_CR4_ABTEX 0x40 /* Abort Extend */
86 #define MC6854_SR1_TDRA 0x40 /* Transmitter Data Register Available */
87 #define MC6854_SR1_FC 0x40 /* Frame Complete */
99 #define MC6854_SR2_OVRN 0x40 /* Receiver Overrun */
depcareg.h 69 #define DEPCA_CSR_LOW32K 0x40 /* Map lower 32K chunk */
dl10019reg.h 46 #define DL0_GPIO_MII_DATAOUT 0x40 /* MII data MAC->PHY */
  /src/sys/dev/i2c/
tea5767reg.h 39 #define TEA5767_SEARCH 0x40 /* Activate search Mode */
44 #define TEA5767_SSL_2 0x40 /* ADC o/p = 7 */
51 #define TEA5767_STANDBY 0x40
65 #define TEA5767_BAND_LIMIT 0X40
  /src/sys/arch/atari/dev/
serreg.h 44 #define UCR_6BITS 0x40 /* 6 databits */
57 #define RSR_OERR 0x40 /* Overrun error */
64 #define TSR_UE 0x40 /* Uart empty */
75 #define MCR_RI 0x40
  /src/sys/arch/ia64/include/
sapicreg.h 38 #define SAPIC_APIC_EOI 0x40
  /src/sys/arch/sh3/include/
dacreg.h 41 #define SH7709_DACR_DAOE0 0x40 /* output enable for channel 0 */
  /src/sys/arch/sun3/sun3/
buserr.h 38 #define BUSERR_PROTERR 0x40 /* MMU protection error (sun3 only) */
enable.h 41 #define ENA_FPP 0x40 /* Enable MC68881 */

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