| /src/sys/arch/x86/pci/ |
| amd8131reg.h | 11 #define AMD8131_IOAPIC_CTL 0x44
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| sumo_dpm.h | 141 #define SUMO_UTC_DFLT_01 0x44
142 #define SUMO_UTC_DFLT_02 0x44
143 #define SUMO_UTC_DFLT_03 0x44
144 #define SUMO_UTC_DFLT_04 0x44
145 #define SUMO_UTC_DFLT_05 0x44
146 #define SUMO_UTC_DFLT_06 0x44
147 #define SUMO_UTC_DFLT_07 0x44
148 #define SUMO_UTC_DFLT_08 0x44
149 #define SUMO_UTC_DFLT_09 0x44
150 #define SUMO_UTC_DFLT_10 0x44
[all...] |
| /src/sys/dev/i2o/ |
| iopreg.h | 38 #define IOP_REG_OFIFO 0x44 /* Outbound FIFO (from IOP) */
|
| /src/sys/dev/wsfont/ |
| sony8x16.h | 97 0x44, /* .*...*.. */
98 0x44, /* .*...*.. */
101 0x44, /* .*...*.. */
102 0x44, /* .*...*.. */
105 0x44, /* .*...*.. */
106 0x44, /* .*...*.. */
188 0x44, /* .*...*.. */
189 0x44, /* .*...*.. */
190 0x44, /* .*...*.. */
575 0x44, /* .*...*.. *
[all...] |
| /src/sys/dev/i2c/ |
| sht4xreg.h | 22 #define SHT4X_TYPICAL_ADDR 0x44
|
| tvpll_tuners.c | 39 { 999999999, 62500, 0xc6, 0x44, TVPLL_IGNORE_AUX },
|
| /src/sys/dev/pci/ |
| hdaudio_pci.h | 40 #define HDAUDIO_INTEL_REG_ICH_TCSEL 0x44
|
| pciide_svwsata_reg.h | 34 #define SVWSATA_SERROR 0x44
|
| pciide_natsemi_reg.h | 74 #define NATSEMI_C1D1DRT 0x44 /* Channel 1/device 1 data read timing */
97 #define NATSEMI_RTREG(c,d) (0x44 + (c * 8) + (d * 4) + 0)
98 #define NATSEMI_WTREG(c,d) (0x44 + (c * 8) + (d * 4) + 1)
|
| autrireg.h | 50 #define AUTRI_PCI_LEGACY_IOBASE 0x44
58 #define AUTRI_DX_ACR1 0x44
67 #define AUTRI_NX_ACR1 0x44
80 #define AUTRI_SIS_ACRD 0x44
91 #define AUTRI_ALI_ACRD 0x44
|
| pciide_ixp_reg.h | 32 #define IXP_MDMA_TIMING 0x44
|
| pcscpreg.h | 48 #define DMA_STC 0x44 /* Start Transfer Count */
|
| lynxfbreg.h | 50 #define DPR_DST_BASE 0x44
|
| pciide_sl82c105_reg.h | 47 #define SYMPH_P0D0CR 0x44 /* port 0 drive 0 control */
|
| /src/sys/arch/i386/pci/ |
| sis85c503reg.h | 33 #define SIS85C503_CFG_PIRQ_REGEND 0x44
|
| via82c586reg.h | 33 #define VP3_CFG_KBDMISCCTRL12_REG 0x44
|
| /src/share/locale/ctype/charset/ |
| Latin-3 | 14 ALPHA 0x40 - 0x42 0x44 - 0x4f 0x51 - 0x56 0x58 - 0x5f
28 PRINT 0x40 - 0x42 0x44 - 0x4f 0x51 - 0x5f
41 MAPLOWER < 0x44 - 0x4f : 0x64 >
58 MAPUPPER < 0x44 - 0x4f : 0x44 >
62 MAPUPPER < 0x64 - 0x6f : 0x44 >
|
| /src/sys/external/bsd/compiler_rt/dist/lib/fuzzer/tests/ |
| FuzzerUnittest.cpp | 119 uint8_t REM0[8] = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77};
120 uint8_t REM1[8] = {0x00, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77};
121 uint8_t REM2[8] = {0x00, 0x11, 0x33, 0x44, 0x55, 0x66, 0x77};
122 uint8_t REM3[8] = {0x00, 0x11, 0x22, 0x44, 0x55, 0x66, 0x77};
124 uint8_t REM5[8] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x66, 0x77};
125 uint8_t REM6[8] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x77};
126 uint8_t REM7[8] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66};
128 uint8_t REM8[6] = {0x22, 0x33, 0x44, 0x55, 0x66, 0x77};
129 uint8_t REM9[6] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55};
132 uint8_t REM11[5] = {0x33, 0x44, 0x55, 0x66, 0x77}
[all...] |
| /src/common/lib/libc/arch/sparc/gen/ |
| saveregs.S | 55 st %i0, [%fp + 0x44] ! fr->fr_argd[0]
|
| /src/include/ |
| stab.h | 51 #define N_SLINE 0x44 /* text segment line number */
|
| /src/sys/arch/hpcmips/vr/ |
| vrc4172gpioreg.h | 51 #define VRC2_EXGPINTEN1 0x44 /* interrupt enable (16..23) */
|
| /src/sys/arch/mips/alchemy/dev/ |
| usbdreg.h | 57 #define USBD_EP0WRSTAT 0x44 /* EP0 Write FIFO Status */
|
| /src/tests/lib/libbluetooth/ |
| t_sdp_set.c | 90 0x0c, 0x00, 0x44, 0x00, // uint128 0x00440044004400440044004400440044
91 0x44, 0x00, 0x44, 0x00,
92 0x44, 0x00, 0x44, 0x00,
93 0x44, 0x00, 0x44, 0x00,
101 ATF_REQUIRE(sdp_set_uint(&test, 0x44));
131 0x08, 0x44, // uint8 0x44
[all...] |
| /src/sys/dev/microcode/wi/ |
| spectrum24t_cf.h | 47 0x96,0xff,0x06,0xf7,0x20,0xfe,0x00,0x64,0x97,0xff,0x07,0x04,0x30,0x44,0x04,0xa8,
49 0x20,0xfe,0x44,0x41,0x00,0x64,0x64,0x40,0x10,0x2b,0x04,0x64,0x40,0x51,0x00,0x64,
68 0xff,0xff,0x80,0xe7,0xff,0xff,0xff,0xff,0x06,0xe3,0xff,0xff,0x98,0xff,0x30,0x44,
73 0x59,0xd9,0xfd,0x1f,0x58,0x4f,0x2e,0x00,0x58,0x4f,0x14,0x00,0x30,0x44,0x00,0xa8,
86 0xff,0xff,0xef,0x02,0x68,0x40,0x99,0xff,0x3e,0x44,0xfc,0xb4,0x01,0xbc,0x00,0x7f,
88 0x3e,0x44,0xfc,0xb4,0x00,0x7f,0x40,0x5e,0x98,0xff,0x0d,0x63,0x01,0x60,0x58,0x4e,
90 0xfe,0x1f,0x2e,0x58,0xff,0xff,0x98,0xff,0x00,0xe1,0x30,0x44,0x01,0xa8,0x02,0xa8,
92 0x91,0x65,0x78,0x44,0xc4,0x98,0xff,0xff,0x98,0xff,0x88,0xe2,0x00,0xe1,0x30,0x44,
95 0x78,0x44,0xc4,0x98,0xff,0xff,0x0a,0xe1,0xa3,0xff,0xae,0xff,0xff,0xff,0xff,0xff
[all...] |
| /src/sys/arch/arm/cortex/ |
| scu_reg.h | 47 #define SCU_FILTER_END 0x44 // Filtering End Address
|
