| /src/share/locale/ctype/charset/ |
| Latin-1 | 8 ALPHA 0x40 - 0x56 0x58 - 0x76 0x78 - 0x7f
13 UPPER 0x40 - 0x56 0x58 - 0x5f
19 MAPLOWER < 0x58 - 0x5f : 0x78 >
24 MAPUPPER < 0x58 - 0x5f : 0x58 >
26 MAPUPPER < 0x78 - 0x7f : 0x58 >
|
| Latin-5 | 10 ALPHA 0x40 - 0x56 0x58 - 0x5f
16 UPPER 0x40 - 0x56 0x58 - 0x5f
22 MAPLOWER < 0x58 - 0x5e : 0x78 >
27 MAPUPPER < 0x58 - 0x5e : 0x58 >
29 MAPUPPER < 0x78 - 0x7e : 0x58 >
|
| Latin-Greek | 23 MAPLOWER < 0x58 - 0x5e : 0x78 >
28 MAPUPPER < 0x58 - 0x5e : 0x58 >
30 MAPUPPER < 0x78 - 0x7e : 0x58 >
|
| Latin-2 | 12 ALPHA 0x40 - 0x56 0x58 - 0x5f
22 UPPER 0x40 - 0x56 0x58 - 0x5e
38 MAPLOWER < 0x58 - 0x5e : 0x78 >
53 MAPUPPER < 0x58 - 0x5e : 0x58 >
55 MAPUPPER < 0x78 - 0x7e : 0x58 >
|
| Latin-3 | 14 ALPHA 0x40 - 0x42 0x44 - 0x4f 0x51 - 0x56 0x58 - 0x5f
24 UPPER 0x40 - 0x56 0x58 - 0x5e
43 MAPLOWER < 0x58 - 0x5e : 0x78 >
60 MAPUPPER < 0x58 - 0x5e : 0x58 >
64 MAPUPPER < 0x78 - 0x7e : 0x58 >
|
| Latin-4 | 13 ALPHA 0x40 - 0x56 0x58 - 0x76 0x78 - 0x7f
21 UPPER 0x40 - 0x56 0x58 - 0x5e
39 MAPLOWER < 0x58 - 0x5e : 0x78 >
56 MAPUPPER < 0x58 - 0x5e : 0x58 >
58 MAPUPPER < 0x78 - 0x7e : 0x58 >
|
| /src/sys/dev/pci/ |
| amdpmreg.h | 46 #define AMDPM_PMPTR 0x58 /* PMxx System Management IO space
|
| pciide_ite_reg.h | 37 #define IT_TIM(chan) ((chan) ? 0x58 : 0x54) /* timings */
|
| pcscpreg.h | 63 #define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */
|
| pciide_acer_reg.h | 91 #define ACER_PCIB_CTRL 0x58
104 {0x0c, 0x58, 0x44, 0x33, 0x31};
|
| /src/common/lib/libc/arch/sparc/gen/ |
| saveregs.S | 61 st %i5, [%fp + 0x58] ! fr->fr_argd[5]
|
| /src/sys/arch/mips/alchemy/dev/ |
| usbdreg.h | 62 #define USBD_ENABLE 0x58 /* USB Device Controller Enable */
|
| /src/sys/arch/pmax/stand/common/ |
| bootread.S | 39 lw v0, 0x58(v0) # offset for callv->_bootread
|
| /src/sys/arch/vax/uba/ |
| qv_ic.h | 41 #define QV_IC_SIRR 0x58
|
| /src/lib/libc/arch/sparc64/gen/ |
| _setjmp.S | 70 stx %g7, [%o0+0x58]
87 ldx [%i0+0x58],%g7
|
| /src/sys/arch/macppc/macppc/ |
| static_edid.c | 50 /* 50 */ 0x2d, 0x49, 0x41, 0x58, 0x47, 0x30, 0x31, 0x41,
52 /* 60 */ 0x42, 0x4d, 0x2d, 0x49, 0x41, 0x58, 0x47, 0x30,
66 /* 18 */ 0xe8, 0x16, 0xe0, 0x98, 0x58, 0x51, 0x7e, 0x27,
70 /* 38 */ 0x20, 0x00, 0x31, 0x58, 0x1c, 0x20, 0x28, 0x80,
|
| /src/sys/arch/sgimips/mace/ |
| mavbreg.h | 57 #define MAVB_CHANNEL2_DEPTH 0x58
|
| if_mecreg.h | 118 #define MEC_TX_VECTOR 0x58
119 #define MEC_IRQ_VECTOR 0x58
|
| /src/sys/dev/ic/ |
| cs4237reg.h | 49 #define CS_X_RIGHTINPUT_CONTROL 0x58 /* Right Input Mixer Control */
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| omap4.h | 27 #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
90 #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
103 #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/pm/ |
| nouveau_nvkm_engine_pm_gt200.c | 94 { 0x58, "pc01_vfetch_12", g84_vfetch_sources },
117 { 0x58, "pc02_crop_03", gt200_crop_sources },
|
| /src/sys/external/bsd/gnu-efi/dist/lib/mips64el/ |
| setjmp.S | 38 sd $s7, 0x58($a0)
74 ld $s7, 0x58($a0)
|
| /src/sys/dev/microcode/wi/ |
| spectrum24t_cf.h | 71 0xfc,0x60,0x00,0x66,0x09,0x60,0xc2,0x64,0x58,0xd0,0x59,0xd9,0xfd,0x1f,0x05,0x60,
72 0x08,0x63,0x08,0x60,0xfe,0x61,0xfc,0x60,0x00,0x66,0x0a,0x60,0x02,0x64,0x58,0xd0,
73 0x59,0xd9,0xfd,0x1f,0x58,0x4f,0x2e,0x00,0x58,0x4f,0x14,0x00,0x30,0x44,0x00,0xa8,
75 0xff,0xff,0x58,0x4f,0x41,0x00,0x01,0x60,0x9c,0x78,0xff,0xff,0x98,0xff,0x00,0xe1,
79 0x2f,0x58,0xff,0xff,0x00,0x60,0x7e,0x63,0xfe,0x60,0x00,0x65,0x45,0x4b,0xdc,0x60,
80 0xfe,0x61,0xfc,0x60,0x00,0x65,0x0f,0x60,0x0c,0x64,0x65,0x46,0x58,0xd0,0x2b,0x46,
81 0x59,0xd8,0xfb,0x1f,0x7e,0x63,0x40,0xa1,0x40,0xa1,0x65,0x46,0x58,0xd0,0x2b,0x46,
82 0x59,0xd8,0xfb,0x1f,0x7e,0x63,0x40,0xa1,0x40,0xa1,0x65,0x46,0x58,0xd0,0x2b,0x46,
83 0x59,0xd8,0xfb,0x1f,0x2f,0x58,0xff,0xff,0x04,0xee,0x0d,0x60,0x26,0x63,0x0e,0x60
[all...] |
| /src/sys/arch/arm/ep93xx/ |
| epgpioreg.h | 99 #define EP93XX_GPIO_FIntEn 0x58 /* Interrupt Enable (R/W) */
|
| /src/sys/arch/arm/nvidia/ |
| tegra_timerreg.h | 41 #define TMR4_PTV_REG 0x58
|
