/src/sys/arch/hp300/dev/ |
dnkbdmap.h | 29 extern const uint8_t dnkbd_raw[0x80];
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/src/sys/arch/luna68k/dev/ |
omkbdmap.h | 22 extern const uint8_t omkbd_raw[0x80];
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/src/sys/dev/mca/ |
mcareg.h | 44 #define MCA_POS5_CHCK 0x80 /* POS5, lo => adapter CHCK signal */
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/src/lib/libbluetooth/ |
sdp_uuid.c | 41 0x80, 43 { 0x00, 0x80, 0x5f, 0x9b, 0x34, 0xfb }
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/src/lib/libc/gen/ |
infinityf_ieee754.c | 17 { { 0x7f, 0x80, 0, 0 } }; 19 { { 0, 0, 0x80, 0x7f } };
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/src/sys/arch/x68k/dev/ |
opmvar.h | 38 #define OPM1B_CT1MSK (0x80) 42 #define VS_CLK_4MHZ (0x80)
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mb86601reg.h | 43 #define PSNS_REQ 0x80
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/src/sys/arch/next68k/dev/ |
bmapreg.h | 30 #define BMAP_DDIR_UTPENABLE_MASK 0x80|0x10 39 #define BMAP_DATA_UTPENABLE 0x80|0x10
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/src/sys/dev/ic/ |
aic77xxreg.h | 37 #define INTDEF_IST_LEVEL 0x80
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/src/sys/dev/i2c/ |
tea5767reg.h | 38 #define TEA5767_MUTE 0x80 /* Set Mute */ 42 #define TEA5767_SUD 0x80 /* Search Up */ 59 #define TEA5767_PLLREF 0x80 /* If enabled TEA5767_CLK_FREQ : 6.5MHZ*/ 64 #define TEA5767_READY_FLAG 0x80 68 #define TEA5767_STEREO 0x80
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/src/sys/arch/evbppc/walnut/dev/ |
ds1743reg.h | 54 #define DS_CTL_W 0x80 /* W bit in the century register */ 57 #define DS_CTL_OSC 0x80 /* ~OSC BIT in the seconds register */ 59 #define DS_CTL_BF 0x80 /* BF(battery failure) bit in the day register */
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/src/lib/libc/arch/i386/gen/ |
infinityl.c | 16 { { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0x7f, 0, 0 } };
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/src/lib/libc/arch/m68k/gen/ |
infinityl.c | 17 { { 0x7f, 0xff, 0, 0, 0x80, 0, 0, 0, 0, 0, 0, 0 } };
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/src/lib/libc/arch/x86_64/gen/ |
infinityl.c | 16 { { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0x7f, 0, 0, 0, 0, 0, 0 } };
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/src/share/locale/ctype/ |
ru_RU.CP866.src | 12 ALPHA 'A' - 'Z' 'a' - 'z' 0x80 - 0xaf 0xe0 - 0xf1 15 GRAPH 0x21 - 0x7e 0x80 - 0xff 19 UPPER 'A' - 'Z' 0x80 - 0x9f 0xf0 22 PRINT 0x20 - 0x7e 0x80 - 0xff 30 MAPLOWER <0x80 - 0x8f : 0xa0> 38 MAPUPPER <0x80 - 0x9f : 0x80> 40 MAPUPPER <0xa0 - 0xaf : 0x80>
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/src/sys/arch/amd64/amd64/ |
linux32_sigcode.S | 12 int $0x80 14 int $0x80 23 int $0x80 25 int $0x80
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/src/sys/arch/amiga/dev/ |
dmavar.h | 36 #define DMAGO_NOINT 0x80 /* don't interrupt on completion */
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/src/sys/arch/hp300/hp300/ |
leds.h | 43 #define LED_LANXMT 0x80 /* for LAN transmit activity */
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/src/sys/arch/mvme68k/dev/ |
dmavar.h | 36 #define DMAGO_NOINT 0x80 /* don't interrupt on completion */
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/src/sys/arch/sun2/sun2/ |
buserr.h | 37 #define BUSERR_VALID 0x80 /* page map was valid */
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/src/sys/dev/hil/ |
hilkbdmap.h | 36 extern const uint8_t hilkbd_raw[0x80];
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/src/sys/external/bsd/gnu-efi/dist/inc/protocol/ |
adapterdebug.h | 26 { 0x82f86881, 0x282b, 0x11d4, {0xbc, 0x7d, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} }
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/src/sys/external/isc/atheros_hal/dist/ar5212/ |
ar5212_phy.c | 37 /* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 }, 39 /* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2, 0, 0 }, 41 /* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4, 0, 0 }, 54 /* 6 Mb */ { AH_TRUE, OFDM, 3000, 0x0b, 0x00, (0x80|6), 0, 0, 0 }, 56 /* 12 Mb */ { AH_TRUE, OFDM, 6000, 0x0a, 0x00, (0x80|12), 2, 0, 0 }, 58 /* 24 Mb */ { AH_TRUE, OFDM, 12000, 0x09, 0x00, (0x80|24), 4, 0, 0 }, 71 /* 6 Mb */ { AH_TRUE, OFDM, 1500, 0x0b, 0x00, (0x80|3), 0, 0, 0 }, 73 /* 12 Mb */ { AH_TRUE, OFDM, 3000, 0x0a, 0x00, (0x80|6), 2, 0, 0 }, 75 /* 24 Mb */ { AH_TRUE, OFDM, 6000, 0x09, 0x00, (0x80|12), 4, 0, 0 }, 88 /* 6 Mb */ { AH_TRUE, TURBO, 6000, 0x0b, 0x00, (0x80|12), 0, 0, 0 } [all...] |
/src/sys/arch/amiga/pci/ |
empbreg.h | 51 #define ZORRO_PRODID_MEDZIV_MEM ZORRO_PRODID_MEDZIV+0x80 52 #define ZORRO_PRODID_MED1K2_MEM ZORRO_PRODID_MED1K2+0x80 53 #define ZORRO_PRODID_MED4K_MEM ZORRO_PRODID_MED4K+0x80 54 #define ZORRO_PRODID_MED1K2SX_MEM ZORRO_PRODID_MED1K2SX+0x80 55 #define ZORRO_PRODID_MED1K2LT2_MEM ZORRO_PRODID_MED1K2LT2+0x80 56 #define ZORRO_PRODID_MED1K2LT4_MEM ZORRO_PRODID_MED1K2LT4+0x80 57 #define ZORRO_PRODID_MED1K2TX_MEM ZORRO_PRODID_MED1K2TX+0x80 58 #define ZORRO_PRODID_MED4KMKII_MEM ZORRO_PRODID_MED4KMKII+0x80
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/src/sys/dev/smbus/ |
m41t81reg.h | 46 #define M41T81_SEC_ST 0x80 /* Stop Bit */ 51 #define M41T81_HOUR_CEB 0x80 /* Century Enable Bit */ 60 #define M41T81_CTL_OUT 0x80 /* Output Level */ 72 #define M41T81_ALM_MON_AFE 0x80 /* Alarm Flag Enable Flag */ 75 #define M41T81_ALM_DATE_RPT4 0x80 /* Alarm Repeat Mode Bit 4 */ 78 #define M41T81_ALM_HOUR_RPT3 0x80 /* Alarm Repeat Mode Bit 3 */ 80 #define M41T81_ALM_MIN_RPT2 0x80 /* Alarm Repeat Mode Bit 2 */ 82 #define M41T81_ALM_SEC_RPT1 0x80 /* Alarm Repeat Mode Bit 1 */
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