Searched refs:A6XX_TEX_CONST_DWORDS (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_descriptor_set.c76 return A6XX_TEX_CONST_DWORDS * 4 * 2;
78 return A6XX_TEX_CONST_DWORDS * 4;
88 * mutable descriptors, max_size should be always A6XX_TEX_CONST_DWORDS * 4.
96 assert(max_size == A6XX_TEX_CONST_DWORDS * 4);
447 A6XX_TEX_CONST_DWORDS * 4 * layout->dynamic_offset_count;
537 offset += A6XX_TEX_CONST_DWORDS;
614 bo_size += A6XX_TEX_CONST_DWORDS * 4 *
629 host_size += A6XX_TEX_CONST_DWORDS * 4 * dynamic_count;
795 memset(dst, 0, A6XX_TEX_CONST_DWORDS * sizeof(uint32_t));
819 memset(dst, 0, A6XX_TEX_CONST_DWORDS * sizeo
[all...]
H A Dtu_private.h125 #define A6XX_TEX_CONST_DWORDS 16 macro
728 uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
1457 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1462 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1542 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
H A Dtu_clear_blit.c804 A6XX_TEX_CONST_DWORDS, &texture);
810 memcpy(texture.map, tex_const, A6XX_TEX_CONST_DWORDS * 4);
818 texture.map[A6XX_TEX_CONST_DWORDS + 0] =
825 texture.map[A6XX_TEX_CONST_DWORDS + 1] =
829 texture.map[A6XX_TEX_CONST_DWORDS + 2] = 0;
830 texture.map[A6XX_TEX_CONST_DWORDS + 3] = 0;
838 tu_cs_emit_qw(cs, texture.iova + A6XX_TEX_CONST_DWORDS * 4);
840 tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_SAMP(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4));
874 uint32_t desc[A6XX_TEX_CONST_DWORDS];
894 for (uint32_t i = 6; i < A6XX_TEX_CONST_DWORDS;
[all...]
H A Dtu_shader.c212 base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
375 nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
377 descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
H A Dtu_cmd_buffer.c1057 A6XX_TEX_CONST_DWORDS, &texture);
1071 uint32_t *dst = &texture.map[A6XX_TEX_CONST_DWORDS * i];
1075 memcpy(dst, iview->descriptor, A6XX_TEX_CONST_DWORDS * 4);
1124 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
1776 &descriptors_state->dynamic_descriptors[dst_idx * A6XX_TEX_CONST_DWORDS];
1778 &set->dynamic_descriptors[src_idx * A6XX_TEX_CONST_DWORDS];
1791 memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
1816 A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
1823 layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
1880 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS *
[all...]
H A Dtu_pipeline.c177 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
210 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
225 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
226 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
H A Dtu_device.c797 static const size_t max_descriptor_set_size = (1 << 28) / A6XX_TEX_CONST_DWORDS;

Completed in 36 milliseconds