1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-03 18:24:29) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2019-05-03 18:24:29) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-03 18:24:37) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2018 by the following authors: 24 - Rob Clark <robdclark (at) gmail.com> (robclark) 25 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 enum chip { 50 A2XX = 0, 51 A3XX = 0, 52 A4XX = 0, 53 A5XX = 0, 54 A6XX = 0, 55 }; 56 57 enum adreno_pa_su_sc_draw { 58 PC_DRAW_POINTS = 0, 59 PC_DRAW_LINES = 1, 60 PC_DRAW_TRIANGLES = 2, 61 }; 62 63 enum adreno_compare_func { 64 FUNC_NEVER = 0, 65 FUNC_LESS = 1, 66 FUNC_EQUAL = 2, 67 FUNC_LEQUAL = 3, 68 FUNC_GREATER = 4, 69 FUNC_NOTEQUAL = 5, 70 FUNC_GEQUAL = 6, 71 FUNC_ALWAYS = 7, 72 }; 73 74 enum adreno_stencil_op { 75 STENCIL_KEEP = 0, 76 STENCIL_ZERO = 1, 77 STENCIL_REPLACE = 2, 78 STENCIL_INCR_CLAMP = 3, 79 STENCIL_DECR_CLAMP = 4, 80 STENCIL_INVERT = 5, 81 STENCIL_INCR_WRAP = 6, 82 STENCIL_DECR_WRAP = 7, 83 }; 84 85 enum adreno_rb_blend_factor { 86 FACTOR_ZERO = 0, 87 FACTOR_ONE = 1, 88 FACTOR_SRC_COLOR = 4, 89 FACTOR_ONE_MINUS_SRC_COLOR = 5, 90 FACTOR_SRC_ALPHA = 6, 91 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 92 FACTOR_DST_COLOR = 8, 93 FACTOR_ONE_MINUS_DST_COLOR = 9, 94 FACTOR_DST_ALPHA = 10, 95 FACTOR_ONE_MINUS_DST_ALPHA = 11, 96 FACTOR_CONSTANT_COLOR = 12, 97 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 98 FACTOR_CONSTANT_ALPHA = 14, 99 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 100 FACTOR_SRC_ALPHA_SATURATE = 16, 101 FACTOR_SRC1_COLOR = 20, 102 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 103 FACTOR_SRC1_ALPHA = 22, 104 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 105 }; 106 107 enum adreno_rb_surface_endian { 108 ENDIAN_NONE = 0, 109 ENDIAN_8IN16 = 1, 110 ENDIAN_8IN32 = 2, 111 ENDIAN_16IN32 = 3, 112 ENDIAN_8IN64 = 4, 113 ENDIAN_8IN128 = 5, 114 }; 115 116 enum adreno_rb_dither_mode { 117 DITHER_DISABLE = 0, 118 DITHER_ALWAYS = 1, 119 DITHER_IF_ALPHA_OFF = 2, 120 }; 121 122 enum adreno_rb_depth_format { 123 DEPTHX_16 = 0, 124 DEPTHX_24_8 = 1, 125 DEPTHX_32 = 2, 126 }; 127 128 enum adreno_rb_copy_control_mode { 129 RB_COPY_RESOLVE = 1, 130 RB_COPY_CLEAR = 2, 131 RB_COPY_DEPTH_STENCIL = 5, 132 }; 133 134 enum a3xx_rop_code { 135 ROP_CLEAR = 0, 136 ROP_NOR = 1, 137 ROP_AND_INVERTED = 2, 138 ROP_COPY_INVERTED = 3, 139 ROP_AND_REVERSE = 4, 140 ROP_INVERT = 5, 141 ROP_XOR = 6, 142 ROP_NAND = 7, 143 ROP_AND = 8, 144 ROP_EQUIV = 9, 145 ROP_NOOP = 10, 146 ROP_OR_INVERTED = 11, 147 ROP_COPY = 12, 148 ROP_OR_REVERSE = 13, 149 ROP_OR = 14, 150 ROP_SET = 15, 151 }; 152 153 enum a3xx_render_mode { 154 RB_RENDERING_PASS = 0, 155 RB_TILING_PASS = 1, 156 RB_RESOLVE_PASS = 2, 157 RB_COMPUTE_PASS = 3, 158 }; 159 160 enum a3xx_msaa_samples { 161 MSAA_ONE = 0, 162 MSAA_TWO = 1, 163 MSAA_FOUR = 2, 164 MSAA_EIGHT = 3, 165 }; 166 167 enum a3xx_threadmode { 168 MULTI = 0, 169 SINGLE = 1, 170 }; 171 172 enum a3xx_instrbuffermode { 173 CACHE = 0, 174 BUFFER = 1, 175 }; 176 177 enum a3xx_threadsize { 178 TWO_QUADS = 0, 179 FOUR_QUADS = 1, 180 }; 181 182 enum a3xx_color_swap { 183 WZYX = 0, 184 WXYZ = 1, 185 ZYXW = 2, 186 XYZW = 3, 187 }; 188 189 enum a3xx_rb_blend_opcode { 190 BLEND_DST_PLUS_SRC = 0, 191 BLEND_SRC_MINUS_DST = 1, 192 BLEND_DST_MINUS_SRC = 2, 193 BLEND_MIN_DST_SRC = 3, 194 BLEND_MAX_DST_SRC = 4, 195 }; 196 197 enum a4xx_tess_spacing { 198 EQUAL_SPACING = 0, 199 ODD_SPACING = 2, 200 EVEN_SPACING = 3, 201 }; 202 203 #define REG_AXXX_CP_RB_BASE 0x000001c0 204 205 #define REG_AXXX_CP_RB_CNTL 0x000001c1 206 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 207 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 208 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 209 { 210 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 211 } 212 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 213 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 214 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 215 { 216 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 217 } 218 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 219 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 220 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 221 { 222 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 223 } 224 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 225 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 226 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 227 228 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 229 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 230 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 231 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 232 { 233 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 234 } 235 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 236 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 237 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 238 { 239 assert(!(val & 0x3)); 240 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 241 } 242 243 #define REG_AXXX_CP_RB_RPTR 0x000001c4 244 245 #define REG_AXXX_CP_RB_WPTR 0x000001c5 246 247 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 248 249 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 250 251 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 252 253 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 254 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 255 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 256 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 257 { 258 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 259 } 260 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 261 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 262 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 263 { 264 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 265 } 266 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 267 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 268 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 269 { 270 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 271 } 272 273 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 274 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 275 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 276 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 277 { 278 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 279 } 280 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 281 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 282 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 283 { 284 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 285 } 286 287 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 288 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 289 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 290 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 291 { 292 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 293 } 294 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 295 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 296 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 297 { 298 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 299 } 300 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 301 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 302 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 303 { 304 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 305 } 306 307 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 308 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 309 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 310 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 311 { 312 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 313 } 314 315 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 316 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 317 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 318 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 319 { 320 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 321 } 322 323 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 324 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 325 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 326 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 327 { 328 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 329 } 330 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 331 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 332 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 333 { 334 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 335 } 336 337 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 338 339 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 340 341 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 342 343 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 344 345 #define REG_AXXX_CP_INT_CNTL 0x000001f2 346 #define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 347 #define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 348 #define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 349 #define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 350 #define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 351 #define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 352 #define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 353 #define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 354 #define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 355 356 #define REG_AXXX_CP_INT_STATUS 0x000001f3 357 358 #define REG_AXXX_CP_INT_ACK 0x000001f4 359 360 #define REG_AXXX_CP_ME_CNTL 0x000001f6 361 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 362 #define AXXX_CP_ME_CNTL_HALT 0x10000000 363 364 #define REG_AXXX_CP_ME_STATUS 0x000001f7 365 366 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 367 368 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 369 370 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 371 372 #define REG_AXXX_CP_DEBUG 0x000001fc 373 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 374 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 375 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 376 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 377 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 378 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 379 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 380 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 381 382 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 383 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 384 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 385 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 386 { 387 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 388 } 389 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 390 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 391 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 392 { 393 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 394 } 395 396 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 397 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 398 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 399 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 400 { 401 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 402 } 403 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 404 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 405 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 406 { 407 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 408 } 409 410 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 411 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 412 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 413 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 414 { 415 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 416 } 417 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 418 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 419 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 420 { 421 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 422 } 423 424 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 425 426 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 427 428 #define REG_AXXX_CP_ST_BASE 0x0000044d 429 430 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 431 432 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 433 434 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 435 436 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 437 438 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 439 440 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 441 442 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 443 444 #define REG_AXXX_CP_IB1_BASE 0x00000458 445 446 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 447 448 #define REG_AXXX_CP_IB2_BASE 0x0000045a 449 450 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 451 452 #define REG_AXXX_CP_STAT 0x0000047f 453 #define AXXX_CP_STAT_CP_BUSY 0x80000000 454 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 455 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 456 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 457 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 458 #define AXXX_CP_STAT_ME_BUSY 0x04000000 459 #define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 460 #define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 461 #define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 462 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 463 #define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 464 #define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 465 #define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 466 #define AXXX_CP_STAT_PFP_BUSY 0x00020000 467 #define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 468 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 469 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 470 #define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 471 #define AXXX_CP_STAT_CSF_BUSY 0x00000400 472 #define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 473 #define AXXX_CP_STAT_EVENT_BUSY 0x00000100 474 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 475 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 476 #define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 477 #define AXXX_CP_STAT_RCIU_BUSY 0x00000010 478 #define AXXX_CP_STAT_RBIU_BUSY 0x00000008 479 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 480 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 481 #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 482 483 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 484 485 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 486 487 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 488 489 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 490 491 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 492 493 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 494 495 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 496 497 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 498 499 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 500 501 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 502 503 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 504 505 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 506 507 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 508 509 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 510 511 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 512 513 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 514 515 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 516 517 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 518 519 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 520 521 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 522 523 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 524 525 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 526 527 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 528 529 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 530 531 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 532 533 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 534 535 536 #endif /* ADRENO_COMMON_XML */ 537
Indexes created Sat Aug 01 00:24:56 UTC 2026