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    Searched refs:COND (Results 1 - 25 of 129) sorted by relevancy

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  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
etnaviv_asm.c 74 VIV_ISA_WORD_0_COND(inst->cond) |
75 COND(inst->sat, VIV_ISA_WORD_0_SAT) |
76 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) |
83 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) |
85 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) |
87 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) |
88 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS);
91 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) |
93 COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) |
95 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG)
    [all...]
etnaviv_rasterizer.c 53 COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) |
54 COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) |
55 COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE);
60 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE);
64 COND(!so->flatshade_first, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST) |
65 COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etnaviv_texture_desc.c 113 COND(ss->lod_bias != 0.0, VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE);
114 cs->SAMP_ANISOTROPY = COND(ansio, etna_log2_fixp88(ss->max_anisotropy));
191 DESC_SET(CONFIG0, COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format))
193 COND(res->layout == ETNA_LAYOUT_LINEAR && !util_format_is_compressed(so->format),
195 DESC_SET(CONFIG1, COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
196 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
197 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
200 COND(sint && desc->channel[0].size == 8, TE_SAMPLER_CONFIG2_SIGNED_INT8) |
201 COND(sint && desc->channel[0].size == 16, TE_SAMPLER_CONFIG2_SIGNED_INT16));
206 DESC_SET(ASTC0, COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format))
    [all...]
etnaviv_texture_state.c 105 VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(COND(ansio, etna_log2_fixp55(ss->max_anisotropy)));
114 COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP) : 0;
117 COND(ss->lod_bias != 0.0 && mipmap, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
139 COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) |
184 COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
224 sv->config1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
225 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
226 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
228 sv->astc0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
229 COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB)
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/etnaviv/
etnaviv_asm.c 74 VIV_ISA_WORD_0_COND(inst->cond) |
75 COND(inst->sat, VIV_ISA_WORD_0_SAT) |
76 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) |
83 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) |
85 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) |
87 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) |
88 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS);
91 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) |
93 COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) |
95 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG)
    [all...]
etnaviv_rasterizer.c 53 COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) |
54 COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) |
55 COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE);
60 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE);
64 COND(!so->flatshade_first, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST) |
65 COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
etnaviv_zsa.c 99 COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
100 COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
102 COND(disable_zs && ctx->specs.halti < 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
104 COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
etnaviv_util.h 31 #define COND(bool, val) ((bool) ? (val) : 0)
etnaviv_texture_state.c 57 COND(ss->normalized_coords, VIVS_TE_SAMPLER_CONFIG0_ROUND_UV);
61 COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
111 sv->TE_SAMPLER_CONFIG0 = COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
145 sv->TE_SAMPLER_CONFIG1 = COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
146 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
148 sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
157 COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
158 COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
294 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
fd5_emit.h 134 OUT_RING(ring, COND(mode == GMEM, CP_SET_RENDER_MODE_3_GMEM_ENABLE) |
135 COND(mode == BINNING, CP_SET_RENDER_MODE_3_VSC_ENABLE));
178 COND(binning, A5XX_RB_RENDER_CNTL_BINNING_PASS) |
179 COND(binning, A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE) |
180 COND(samples_passed, A5XX_RB_RENDER_CNTL_SAMPLES_PASSED) |
181 COND(!blit, 0x8));
185 COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) |
186 COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED));
fd5_blend.c 102 COND(cso->logicop_enable, A5XX_RB_MRT_CONTROL_ROP_ENABLE) |
126 COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
127 COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
131 COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE);
fd5_program.c 133 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
134 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
135 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
136 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
301 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
304 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
307 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
310 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
313 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
320 COND(s[VS].v && s[VS].v->has_ssbo
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
fd5_emit.h 127 OUT_RING(ring, COND(mode == GMEM, CP_SET_RENDER_MODE_3_GMEM_ENABLE) |
128 COND(mode == BINNING, CP_SET_RENDER_MODE_3_VSC_ENABLE));
164 COND(binning, A5XX_RB_RENDER_CNTL_BINNING_PASS) |
165 COND(binning, A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE) |
166 COND(samples_passed, A5XX_RB_RENDER_CNTL_SAMPLES_PASSED) |
167 COND(!blit, 0x8));
171 COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) |
172 COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED));
fd5_blend.c 121 COND(cso->logicop_enable, A5XX_RB_MRT_CONTROL_ROP_ENABLE) |
143 COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
144 COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
146 COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE) |
147 COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
fd5_program.c 218 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
219 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
220 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
221 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
369 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
372 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
375 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
378 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
381 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
388 COND(s[VS].v && s[VS].v->has_ssbo, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE))
    [all...]
  /xsrc/external/mit/libdrm/dist/
libdrm_macros.h 37 * Basically, use COND to dimension an array. If COND is false/zero the
40 #define STATIC_ASSERT(COND) \
42 (void) sizeof(char [1 - 2*!(COND)]); \
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
fd6_blend.c 120 COND(cso->logicop_enable, A6XX_RB_MRT_CONTROL_ROP_ENABLE) |
141 COND(cso->alpha_to_coverage, A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
142 COND(cso->independent_blend_enable, A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
144 COND(cso->alpha_to_coverage, A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE) |
145 COND(mrt_blend, A6XX_SP_BLEND_CNTL_ENABLED);
fd6_program.c 232 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
233 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
234 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
235 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
300 #define CONDREG(r, val) COND(VALIDREG(r), (val))
365 OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
375 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
379 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
386 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
399 OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED)
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a4xx/
fd4_program.c 302 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
306 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
307 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
308 COND(s[VS].instrlen && s[FS].instrlen,
321 COND(s[VS].v->num_samp > 0, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
371 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
390 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
396 COND(s[FS].v->num_samp > 0, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
399 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
400 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a4xx/
fd4_blend.c 99 COND(cso->logicop_enable, A4XX_RB_MRT_CONTROL_ROP_ENABLE) |
121 COND(cso->independent_blend_enable, A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND);
fd4_program.c 274 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
278 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
279 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
280 COND(s[VS].instrlen && s[FS].instrlen,
295 COND(s[VS].v->need_pixlod, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
347 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
369 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
375 COND(s[FS].v->need_pixlod, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
379 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
380 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a3xx/
fd3_program.c 225 COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
236 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
307 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
313 COND(fp->need_pixlod, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
329 OUT_RING(ring, COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
337 COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
342 COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
343 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
351 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
416 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE))
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a3xx/
fd3_program.c 253 COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
263 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
332 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
338 COND(fp->num_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
354 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
361 COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
365 mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
366 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
375 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
449 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE))
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
fd6_program.c 140 COND(so->pvtmem_per_wave,
246 COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
247 COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
248 COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
249 COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
290 OUT_RING(ring, COND(state->hs,
293 OUT_RING(ring, COND(state->ds,
296 OUT_RING(ring, COND(state->gs,
304 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
310 OUT_RING(ring, COND(state->hs
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/util/
macros.h 81 # define STATIC_ASSERT(COND) do { \
82 (void) sizeof(char [(COND) != 0]); \
85 /* This version of STATIC_ASSERT() relies on VLAs. If COND is
89 # define STATIC_ASSERT(COND) do { \
90 (void) sizeof(char [1 - 2*!(COND)]); \
93 # define STATIC_ASSERT(COND) do { } while (0)

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