Searched refs:GS (Results 1 - 25 of 76) sorted by relevance

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/xsrc/external/mit/freetype/dist/src/truetype/
H A Dttinterp.c438 exec->GS = size->GS;
554 exec->GS.gep0 = 1;
555 exec->GS.gep1 = 1;
556 exec->GS.gep2 = 1;
558 exec->GS.projVector.x = 0x4000;
559 exec->GS.projVector.y = 0x0000;
561 exec->GS.freeVector = exec->GS.projVector;
562 exec->GS
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H A Dttobjs.c996 exec->GS.dualVector.x = 0x4000;
997 exec->GS.dualVector.y = 0;
998 exec->GS.projVector.x = 0x4000;
999 exec->GS.projVector.y = 0x0;
1000 exec->GS.freeVector.x = 0x4000;
1001 exec->GS.freeVector.y = 0x0;
1003 exec->GS.rp0 = 0;
1004 exec->GS.rp1 = 0;
1005 exec->GS.rp2 = 0;
1007 exec->GS
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H A Dttobjs.h304 TT_GraphicsState GS; member in struct:TT_SizeRec_
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md128 * GS = Geometry Shader
136 * ES = Export Shader (merged into GS on GFX9+), if there is a GS in the SW pipeline, the preceding stage (ie. SW VS or SW TES) always has to run on this HW stage
137 * GS = Geometry Shader, also known as legacy GS
138 * VS = Vertex Shader, **not equivalent to SW VS**: when there is a GS in the SW pipeline this stage runs a "GS copy" shader, otherwise it always runs the SW stage before FS
139 * NGG = Next Generation Geometry, a new hardware stage that replaces legacy HW GS and HW VS on RDNA GPUs
143 ##### Notes about HW VS and the "GS copy" shader
146 However, GS stor
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H A Daco_instruction_selection_setup.cpp831 sw_stage = sw_stage | (is_gs_copy_shader ? SWStage::GSCopy : SWStage::GS);
846 hw_stage = HWStage::NGG; /* GFX10/NGG: VS without GS uses the HW GS stage */
847 else if (sw_stage == SWStage::GS)
848 hw_stage = HWStage::GS;
856 hw_stage = HWStage::GS; /* GFX6-9: VS+GS merged into a GS (and GFX10/legacy) */
858 hw_stage = HWStage::NGG; /* GFX10+: VS+GS merged into an NGG GS */
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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.2.9.rst57 - radeonsi: release GS rings at context destruction
58 - radeonsi: properly destroy the GS copy shader and scratch_bo for
H A D10.3.1.rst94 - radeonsi: release GS rings at context destruction
95 - radeonsi: properly destroy the GS copy shader and scratch_bo for
H A D13.0.3.rst110 - radeonsi: add a tess+GS hang workaround for VI dGPUs
136 - radeonsi: do not kill GS with memory writes
H A D18.3.3.rst61 - radv: Set partial_vs_wave for pipelines with just GS, not tess.
132 - radeonsi: also apply the GS hang workaround to draws without
H A D21.2.3.rst118 - radv: don't require a GS copy shader to use the cache with NGG VS+GS
H A D19.2.5.rst51 - spirv: Don't leak GS initialization to other stages
H A D10.4.6.rst66 - i965/gs: Check newly-generated GS-out VUE map against correct stage
H A D10.5.2.rst67 - i965: Set nr_params to the number of uniform components in the VS/GS
/xsrc/external/mit/xorg-server/dist/hw/xfree86/x86emu/x86emu/
H A Dx86emui.h83 # undef GS
H A Dregs.h123 # undef GS
127 u16 CS, DS, SS, ES, FS, GS; member in struct:i386_segment_regs
174 #define R_GS seg.GS
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_program.c134 GS = 4, enumerator in enum:__anon4fcc07340103
146 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
193 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
194 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
295 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
296 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
297 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
298 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
418 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
419 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS]
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_program.c254 GS = 4, enumerator in enum:__anon68029e760103
266 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
316 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
379 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
380 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
381 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
395 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
396 COND(s[GS].v && s[GS].v->has_ssbo, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
411 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS]
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_program.c164 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES }; enumerator in enum:__anonb59db1490103
174 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
225 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
311 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
312 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
313 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
331 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
332 COND(s[GS].v && s[GS].v->has_ssbo,
348 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS]
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/xsrc/external/mit/MesaLib/dist/src/nouveau/drm-shim/
H A DREADME.md18 | 84 | G84 | GeForce 8600 GS | SM 1.1 |
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_urb.c40 #define GS 1 macro
68 * GS has the same requirement as CLIP, but it never handles tristrips,
112 /* Most minimal update, forces re-emit of URB fence packet after GS
143 brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries;
172 brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
199 "URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_urb.c40 #define GS 1 macro
68 * GS has the same requirement as CLIP, but it never handles tristrips,
112 /* Most minimal update, forces re-emit of URB fence packet after GS
143 brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries;
172 brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
199 "URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_program.c91 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES }; enumerator in enum:__anon9d671a070103
101 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
149 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
150 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
266 A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
267 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
268 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
269 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
400 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
401 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS]
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/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/x86emu/x86emu/
H A Dregs.h116 u16 CS, DS, SS, ES, FS, GS; member in struct:i386_segment_regs
171 #define R_GS seg.GS
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/d3d12/
H A Dd3d12_pipeline_state.cpp209 pso_desc.GS.BytecodeLength = shader->bytecode_length;
210 pso_desc.GS.pShaderBytecode = shader->bytecode;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_program.c252 GS = 4, enumerator in enum:__anon803935b80103
271 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
386 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
387 OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
415 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */

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