Searched refs:INPLL (Results 1 - 13 of 13) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_pm.c88 tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV);
93 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
97 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
103 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
109 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
115 tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV);
121 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
129 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
135 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
141 tmp = INPLL(pScr
[all...]
H A Dlegacy_crtc.c226 INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
233 while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
251 INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
258 while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
324 if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
325 (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) &
403 INPLL(pScrn, RADEON_PPLL_CNTL));
477 INPLL(pScrn, RADEON_P2PLL_CNTL));
602 save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV);
603 save->ppll_div_3 = INPLL(pScr
[all...]
H A Dradeon_macros.h81 #define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr) macro
87 uint32_t tmp_ = INPLL(pScrn, addr); \
H A Dradeon_tv.c226 savePLLTest = INPLL(pScrn, RADEON_PLL_TEST_CNTL);
598 save->tv_pll_cntl = INPLL(pScrn, RADEON_TV_PLL_CNTL);
599 save->tv_pll_cntl1 = INPLL(pScrn, RADEON_TV_PLL_CNTL1);
H A Dradeon_bios.c1568 val = INPLL(pScrn, reg);
1824 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) &
1946 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) &
1956 if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) &
1964 clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL);
1966 val = INPLL(pScrn, RADEON_MCLK_CNTL);
1993 val = INPLL(pScrn, index);
H A Dlegacy_output.c207 ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel);
536 ulOrigVCLK_ECP_CNTL = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
703 ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
1001 unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
1701 vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
1864 pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
H A Dradeon_accel.c271 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
277 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
283 mclk_cntl = INPLL(pScrn, RADEON_MCLK_CNTL);
H A Dradeon_driver.c1062 switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) {
1069 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff);
1070 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff);
1075 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff);
1076 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff);
1085 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
1086 m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff);
1091 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
1138 tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV);
1139 ref_div = INPLL(pScr
[all...]
H A Dradeon_video.c1535 ecp = (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (info->ecp_div << 8);
2569 but only call OUTPLL/INPLL if needed since it may cause a 10ms delay due to
2586 (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (ecp_div << 8));
2593 there is now plenty of usleep after INPLL/OUTPLL for those...*/
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_crtc.c460 while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
468 while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
477 while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
485 while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R);
551 INPLL(pScrn, R128_PPLL_CNTL)));
623 INPLL(pScrn, R128_P2PLL_CNTL)));
H A Dr128_driver.c623 x_mpll_ref_fb_div = INPLL(pScrn, R128_X_MPLL_REF_FB_DIV);
624 xclk_cntl = INPLL(pScrn, R128_XCLK_CNTL) & 0x7;
626 INPLL(pScrn,R128_PPLL_REF_DIV) & R128_PPLL_REF_DIV_MASK;
2410 save->ppll_ref_div = INPLL(pScrn, R128_PPLL_REF_DIV);
2411 save->ppll_div_3 = INPLL(pScrn, R128_PPLL_DIV_3);
2412 save->ppll_div_0 = INPLL(pScrn, R128_PPLL_DIV_0);
2413 save->htotal_cntl = INPLL(pScrn, R128_HTOTAL_CNTL);
2431 save->p2pll_ref_div = INPLL(pScrn, R128_P2PLL_REF_DIV);
2432 save->p2pll_div_0 = INPLL(pScrn, R128_P2PLL_DIV_0);
2433 save->htotal_cntl2 = INPLL(pScr
[all...]
H A Dr128_reg.h71 #define INPLL(pScrn, addr) R128INPLL(pScrn, addr) macro
81 uint32_t tmp = INPLL(pScrn, addr); \
H A Dr128_accel.c135 mclk_cntl = INPLL(pScrn, R128_MCLK_CNTL);

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