Searched refs:MC (Results 1 - 21 of 21) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/isl/tests/
H A Disl_aux_info_test.cpp79 E(CLEAR, MC, false, ASSERT);
80 E(CLEAR, MC, true, ASSERT);
81 E(PARTIAL_CLEAR, MC, false, ASSERT);
82 E(PARTIAL_CLEAR, MC, true, ASSERT);
83 E(COMPRESSED_CLEAR, MC, false, ASSERT);
84 E(COMPRESSED_CLEAR, MC, true, ASSERT);
85 E(COMPRESSED_NO_CLEAR, MC, false, NONE);
86 E(COMPRESSED_NO_CLEAR, MC, true, ASSERT);
87 E(RESOLVED, MC, false, NONE);
88 E(RESOLVED, MC, tru
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_dri.c604 pI810->MC.Size = 7 * 1024 * 1024;
605 pI810->MC.Start = pI810->FbMapSize - 7 * 1024 * 1024;
609 pI810->MC.Size = 8 * 1024 * 1024;
610 pI810->MC.Start = pI810->FbMapSize - 8 * 1024 * 1024;
612 drmAgpAlloc(pI810->drmSubFD, pI810->MC.Size, 0, NULL,
618 if (drmAgpBind(pI810->drmSubFD, agpHandle, pI810->MC.Start) == 0) {
621 pI810->MC.End = pI810->MC.Start + pI810->MC.Size;
624 pI810->MC
[all...]
H A Di810_hwmc.c214 if (drmAddMap(pI810->drmSubFD, (drm_handle_t)pI810->MC.Start,
215 pI810->MC.Size, DRM_AGP, 0, (drmAddress) &pI810->mc_map) < 0) {
216 xf86DrvMsg(pScreen->myNum, X_ERROR, "drmAddMap(MC) failed\n");
282 contextRec->SurfacesOffset = pI810->MC.Start;
283 contextRec->SurfacesSize = pI810->MC.Size;
H A Di810.h149 I810MemRange MC; member in struct:_I810Rec
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_dri.c604 pI810->MC.Size = 7 * 1024 * 1024;
605 pI810->MC.Start = pI810->FbMapSize - 7 * 1024 * 1024;
609 pI810->MC.Size = 8 * 1024 * 1024;
610 pI810->MC.Start = pI810->FbMapSize - 8 * 1024 * 1024;
612 drmAgpAlloc(pI810->drmSubFD, pI810->MC.Size, 0, NULL,
618 if (drmAgpBind(pI810->drmSubFD, agpHandle, pI810->MC.Start) == 0) {
621 pI810->MC.End = pI810->MC.Start + pI810->MC.Size;
624 pI810->MC
[all...]
H A Di810_hwmc.c214 if (drmAddMap(pI810->drmSubFD, (drm_handle_t)pI810->MC.Start,
215 pI810->MC.Size, DRM_AGP, 0, (drmAddress) &pI810->mc_map) < 0) {
216 xf86DrvMsg(pScreen->myNum, X_ERROR, "drmAddMap(MC) failed\n");
282 contextRec->SurfacesOffset = pI810->MC.Start;
283 contextRec->SurfacesSize = pI810->MC.Size;
H A Di810.h149 I810MemRange MC; member in struct:_I810Rec
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di810_hwmc.c216 if (drmAddMap(pI810->drmSubFD, (drm_handle_t)pI810->MC.Start,
217 pI810->MC.Size, DRM_AGP, 0, (drmAddress) &pI810->mc_map) < 0) {
218 xf86DrvMsg(pScreen->myNum, X_ERROR, "drmAddMap(MC) failed\n");
284 contextRec->SurfacesOffset = pI810->MC.Start;
285 contextRec->SurfacesSize = pI810->MC.Size;
H A Di810_dri.c715 pI810->MC.Size = 7 * 1024 * 1024;
716 pI810->MC.Start = pI810->FbMapSize - 7 * 1024 * 1024;
720 pI810->MC.Size = 8 * 1024 * 1024;
721 pI810->MC.Start = pI810->FbMapSize - 8 * 1024 * 1024;
723 drmAgpAlloc(pI810->drmSubFD, pI810->MC.Size, 0, NULL,
729 if (drmAgpBind(pI810->drmSubFD, agpHandle, pI810->MC.Start) == 0) {
732 pI810->MC.End = pI810->MC.Start + pI810->MC.Size;
735 pI810->MC
[all...]
H A Di810.h162 I810MemRange MC; member in struct:_I810Rec
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_perfcounter.h80 MC = 0x15, enumerator in enum:ac_pc_gpu_block
H A Dac_perfcounter.c555 .gpu_block = MC,
556 .name = "MC",
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/clover/llvm/
H A Dcompat.hpp60 #include <llvm/MC/TargetRegistry.h>
/xsrc/external/mit/pixman/dist/pixman/
H A Dpixman-mmx.c225 # define MC(x) to_m64 (c.mmx_ ## x) macro
227 # define MC(x) ((__m64)c.mmx_ ## x) macro
229 # define MC(x) (*(__m64 *)&c.mmx_ ## x) macro
231 # define MC(x) c.mmx_ ## x macro
281 return _mm_xor_si64 (mask, MC (4x00ff));
313 res = _mm_adds_pu16 (res, MC (4x0080));
314 res = _mm_mulhi_pu16 (res, MC (4x0101));
355 __m64 srcfaaa = _mm_or_si64 (srca, MC (full_alpha));
484 return is_equal (_mm_and_si64 (v, MC (full_alpha)), MC (full_alph
[all...]
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_pack.c378 #define MC (1 << 1) macro
394 { MC, (1 << 5) | (1 << 4) },
395 { MC | APF, (1 << 5) | (1 << 4) },
396 { MC | AC, (1 << 6) },
397 { MC | AUF, (1 << 6) },
404 flags_present |= MC;
431 if (flags_present & MC) {
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_pack.c377 #define MC (1 << 1) macro
393 { MC, (1 << 5) | (1 << 4) },
394 { MC | APF, (1 << 5) | (1 << 4) },
395 { MC | AC, (1 << 6) },
396 { MC | AUF, (1 << 6) },
403 flags_present |= MC;
430 if (flags_present & MC) {
/xsrc/external/mit/MesaLib/dist/src/intel/isl/
H A Disl_aux_info.c97 AUX(RESOLVE_AMBIGUATE, Y, x, x, Y, MC)
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_print_asm.cpp35 #include <llvm/MC/MCDisassembler/MCDisassembler.h>
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_target_gv100.cpp105 #define OPINFO(O,SA,MA,SB,MB,SC,MC) \
110 { SRC_##SC, MOD_##MC }}, \
/xsrc/external/mit/ctwm/dist/
H A DCHANGES.md827 1. Workspace switch peformance optimization (by MC)
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.3.0.rst3864 - iris: Support planar resource imports for MC
3866 - iris: Support MC modifier in plane count queries

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