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      1 /*
      2  * Copyright 2005 Stephane Marchesin.
      3  * All Rights Reserved.
      4  *
      5  * Permission is hereby granted, free of charge, to any person obtaining a
      6  * copy of this software and associated documentation files (the "Software"),
      7  * to deal in the Software without restriction, including without limitation
      8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      9  * and/or sell copies of the Software, and to permit persons to whom the
     10  * Software is furnished to do so, subject to the following conditions:
     11  *
     12  * The above copyright notice and this permission notice (including the next
     13  * paragraph) shall be included in all copies or substantial portions of the
     14  * Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 
     25 #ifndef __NOUVEAU_DRM_H__
     26 #define __NOUVEAU_DRM_H__
     27 
     28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
     29 
     30 #include "drm.h"
     31 
     32 #if defined(__cplusplus)
     33 extern "C" {
     34 #endif
     35 
     36 struct drm_nouveau_channel_alloc {
     37 	uint32_t     fb_ctxdma_handle;
     38 	uint32_t     tt_ctxdma_handle;
     39 
     40 	int          channel;
     41 	uint32_t     pushbuf_domains;
     42 
     43 	/* Notifier memory */
     44 	uint32_t     notifier_handle;
     45 
     46 	/* DRM-enforced subchannel assignments */
     47 	struct {
     48 		uint32_t handle;
     49 		uint32_t grclass;
     50 	} subchan[8];
     51 	uint32_t nr_subchan;
     52 };
     53 
     54 struct drm_nouveau_channel_free {
     55 	int channel;
     56 };
     57 
     58 struct drm_nouveau_grobj_alloc {
     59 	int      channel;
     60 	uint32_t handle;
     61 	int      class;
     62 };
     63 
     64 struct drm_nouveau_notifierobj_alloc {
     65 	uint32_t channel;
     66 	uint32_t handle;
     67 	uint32_t size;
     68 	uint32_t offset;
     69 };
     70 
     71 struct drm_nouveau_gpuobj_free {
     72 	int      channel;
     73 	uint32_t handle;
     74 };
     75 
     76 #define NOUVEAU_GETPARAM_PCI_VENDOR      3
     77 #define NOUVEAU_GETPARAM_PCI_DEVICE      4
     78 #define NOUVEAU_GETPARAM_BUS_TYPE        5
     79 #define NOUVEAU_GETPARAM_FB_SIZE         8
     80 #define NOUVEAU_GETPARAM_AGP_SIZE        9
     81 #define NOUVEAU_GETPARAM_CHIPSET_ID      11
     82 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
     83 #define NOUVEAU_GETPARAM_GRAPH_UNITS     13
     84 #define NOUVEAU_GETPARAM_PTIMER_TIME     14
     85 #define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
     86 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
     87 struct drm_nouveau_getparam {
     88 	uint64_t param;
     89 	uint64_t value;
     90 };
     91 
     92 struct drm_nouveau_setparam {
     93 	uint64_t param;
     94 	uint64_t value;
     95 };
     96 
     97 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
     98 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
     99 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
    100 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
    101 #define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
    102 
    103 #define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
    104 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
    105 #define NOUVEAU_GEM_TILE_16BPP       0x00000001
    106 #define NOUVEAU_GEM_TILE_32BPP       0x00000002
    107 #define NOUVEAU_GEM_TILE_ZETA        0x00000004
    108 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
    109 
    110 struct drm_nouveau_gem_info {
    111 	__u32 handle;
    112 	__u32 domain;
    113 	__u64 size;
    114 	__u64 offset;
    115 	__u64 map_handle;
    116 	__u32 tile_mode;
    117 	__u32 tile_flags;
    118 };
    119 
    120 struct drm_nouveau_gem_new {
    121 	struct drm_nouveau_gem_info info;
    122 	__u32 channel_hint;
    123 	__u32 align;
    124 };
    125 
    126 #define NOUVEAU_GEM_MAX_BUFFERS 1024
    127 struct drm_nouveau_gem_pushbuf_bo_presumed {
    128 	__u32 valid;
    129 	__u32 domain;
    130 	__u64 offset;
    131 };
    132 
    133 struct drm_nouveau_gem_pushbuf_bo {
    134 	__u64 user_priv;
    135 	__u32 handle;
    136 	__u32 read_domains;
    137 	__u32 write_domains;
    138 	__u32 valid_domains;
    139 	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
    140 };
    141 
    142 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
    143 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
    144 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
    145 #define NOUVEAU_GEM_MAX_RELOCS 1024
    146 struct drm_nouveau_gem_pushbuf_reloc {
    147 	__u32 reloc_bo_index;
    148 	__u32 reloc_bo_offset;
    149 	__u32 bo_index;
    150 	__u32 flags;
    151 	__u32 data;
    152 	__u32 vor;
    153 	__u32 tor;
    154 };
    155 
    156 #define NOUVEAU_GEM_MAX_PUSH 512
    157 struct drm_nouveau_gem_pushbuf_push {
    158 	__u32 bo_index;
    159 	__u32 pad;
    160 	__u64 offset;
    161 	__u64 length;
    162 };
    163 
    164 struct drm_nouveau_gem_pushbuf {
    165 	__u32 channel;
    166 	__u32 nr_buffers;
    167 	__u64 buffers;
    168 	__u32 nr_relocs;
    169 	__u32 nr_push;
    170 	__u64 relocs;
    171 	__u64 push;
    172 	__u32 suffix0;
    173 	__u32 suffix1;
    174 #define NOUVEAU_GEM_PUSHBUF_SYNC                                    (1ULL << 0)
    175 	__u64 vram_available;
    176 	__u64 gart_available;
    177 };
    178 
    179 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
    180 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
    181 struct drm_nouveau_gem_cpu_prep {
    182 	__u32 handle;
    183 	__u32 flags;
    184 };
    185 
    186 struct drm_nouveau_gem_cpu_fini {
    187 	__u32 handle;
    188 };
    189 
    190 #define DRM_NOUVEAU_GETPARAM           0x00 /* deprecated */
    191 #define DRM_NOUVEAU_SETPARAM           0x01 /* deprecated */
    192 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02 /* deprecated */
    193 #define DRM_NOUVEAU_CHANNEL_FREE       0x03 /* deprecated */
    194 #define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
    195 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
    196 #define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
    197 #define DRM_NOUVEAU_NVIF               0x07
    198 #define DRM_NOUVEAU_SVM_INIT           0x08
    199 #define DRM_NOUVEAU_SVM_BIND           0x09
    200 #define DRM_NOUVEAU_GEM_NEW            0x40
    201 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
    202 #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
    203 #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
    204 #define DRM_NOUVEAU_GEM_INFO           0x44
    205 
    206 struct drm_nouveau_svm_init {
    207 	__u64 unmanaged_addr;
    208 	__u64 unmanaged_size;
    209 };
    210 
    211 struct drm_nouveau_svm_bind {
    212 	__u64 header;
    213 	__u64 va_start;
    214 	__u64 va_end;
    215 	__u64 npages;
    216 	__u64 stride;
    217 	__u64 result;
    218 	__u64 reserved0;
    219 	__u64 reserved1;
    220 };
    221 
    222 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT          0
    223 #define NOUVEAU_SVM_BIND_COMMAND_BITS           8
    224 #define NOUVEAU_SVM_BIND_COMMAND_MASK           ((1 << 8) - 1)
    225 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT         8
    226 #define NOUVEAU_SVM_BIND_PRIORITY_BITS          8
    227 #define NOUVEAU_SVM_BIND_PRIORITY_MASK          ((1 << 8) - 1)
    228 #define NOUVEAU_SVM_BIND_TARGET_SHIFT           16
    229 #define NOUVEAU_SVM_BIND_TARGET_BITS            32
    230 #define NOUVEAU_SVM_BIND_TARGET_MASK            0xffffffff
    231 
    232 /*
    233  * Below is use to validate ioctl argument, userspace can also use it to make
    234  * sure that no bit are set beyond known fields for a given kernel version.
    235  */
    236 #define NOUVEAU_SVM_BIND_VALID_BITS     48
    237 #define NOUVEAU_SVM_BIND_VALID_MASK     ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
    238 
    239 
    240 /*
    241  * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
    242  * result: number of page successfuly migrate to the target memory.
    243  */
    244 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE               0
    245 
    246 /*
    247  * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
    248  */
    249 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM               (1UL << 31)
    250 
    251 
    252 #if defined(__cplusplus)
    253 }
    254 #endif
    255 
    256 #endif /* __NOUVEAU_DRM_H__ */
    257