Searched refs:OP_MERGE (Results 1 - 16 of 16) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_helper.cpp75 insn->op = OP_MERGE;
102 insn->op = OP_MERGE;
105 insn->op = OP_MERGE;
141 insn->op = OP_MERGE;
169 insn->op = OP_MERGE;
233 insn->op = OP_MERGE;
268 insn->op = OP_MERGE;
H A Dnv50_ir_from_tgsi.cpp3888 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3933 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3947 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3959 mkOp2(OP_MERGE, TYPE_U64, src0, srcComp[0], srcComp[1]);
3982 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3994 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4019 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4022 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
4059 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4081 mkOp2(OP_MERGE, TYPE_U6
[all...]
H A Dnv50_ir_from_nir.cpp401 return OP_MERGE;
1461 return mkOp2(OP_MERGE, ty, def, lo, hi);
2045 mkOp2(OP_MERGE, dType, newDefs[i], lo, hi);
2158 mkOp2(OP_MERGE, dType, newDefs[i], def, loadImm(getSSA(), 0u));
2907 Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]);
2967 mkOp2(OP_MERGE, dType, newDefs[0], val0, val1);
3036 mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
3064 mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0));
H A Dnv50_ir_ra.cpp824 // need to fixup register id for participants of OP_MERGE/SPLIT
1095 case OP_MERGE:
1100 if (insn->op == OP_MERGE) {
1121 if (i && i->op == OP_MERGE) // do we really still need this ?
1712 ld = new_Instruction(func, OP_MERGE, ty);
2127 Instruction *merge = new_Instruction(func, OP_MERGE, typeOfSize(size));
2511 i->op == OP_MERGE ||
2597 if (cst->op == OP_MERGE || cst->op == OP_UNION) {
H A Dnv50_ir_lowering_nvc0.cpp108 bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), def[0], def[1]);
150 bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]);
263 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
292 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
1723 bld.mkOp2(OP_MERGE, TYPE_U64, dreg, cas->getSrc(1), cas->getSrc(2));
2129 bld.mkOp2(OP_MERGE, TYPE_U64, addr, bf, eau);
H A Dnv50_ir.h47 OP_MERGE, // opposite of split, e.g. combine 2 32 bit into a 64 bit value enumerator in enum:nv50_ir::operation
H A Dnv50_ir_peephole.cpp36 if (op == OP_PHI || op == OP_SPLIT || op == OP_MERGE || op == OP_CONSTRAINT)
136 if (i->op != OP_MERGE || typeSizeof(i->dType) != 8)
710 case OP_MERGE:
2623 bld.mkOp2(OP_MERGE, i->dType, i->getDef(0), def[0], def[1]);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_helper.cpp75 insn->op = OP_MERGE;
102 insn->op = OP_MERGE;
105 insn->op = OP_MERGE;
141 insn->op = OP_MERGE;
169 insn->op = OP_MERGE;
233 insn->op = OP_MERGE;
268 insn->op = OP_MERGE;
H A Dnv50_ir_lowering_gv100.cpp65 bld.mkOp2(OP_MERGE, i->dType, i->getDef(0), def[0], def[1]);
80 src2 = bld.mkOp2(OP_MERGE, TYPE_U64, bld.getSSA(8), src2s[0], src2s[1])->getDef(0);
341 bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), dest[0], dest[1]);
H A Dnv50_ir_from_tgsi.cpp3920 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3965 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3979 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3991 mkOp2(OP_MERGE, TYPE_U64, src0, srcComp[0], srcComp[1]);
4014 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4026 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4051 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4054 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
4091 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
4113 mkOp2(OP_MERGE, TYPE_U6
[all...]
H A Dnv50_ir_from_nir.cpp439 return OP_MERGE;
1251 return mkOp2(OP_MERGE, ty, def, lo, hi);
1775 mkOp2(OP_MERGE, dType, newDefs[i], lo, hi);
1895 mkOp2(OP_MERGE, dType, newDefs[i], def, loadImm(getSSA(), 0u));
2629 Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]);
2689 mkOp2(OP_MERGE, dType, newDefs[0], val0, val1);
2810 mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
2838 mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0));
H A Dnv50_ir_ra.cpp867 // need to fixup register id for participants of OP_MERGE/SPLIT
1142 case OP_MERGE:
1147 if (insn->op == OP_MERGE) {
1168 if (i && i->op == OP_MERGE) // do we really still need this ?
1758 ld = new_Instruction(func, OP_MERGE, ty);
2177 Instruction *merge = new_Instruction(func, OP_MERGE, typeOfSize(size));
2582 i->op == OP_MERGE ||
2675 if (cst->op == OP_MERGE || cst->op == OP_UNION) {
H A Dnv50_ir_lowering_nvc0.cpp108 bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), def[0], def[1]);
150 bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]);
263 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
292 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]);
1741 bld.mkOp2(OP_MERGE, ty, dreg, cas->getSrc(1), cas->getSrc(2));
2150 bld.mkOp2(OP_MERGE, TYPE_U64, addr, bf, eau);
H A Dnv50_ir.h47 OP_MERGE, // opposite of split, e.g. combine 2 32 bit into a 64 bit value enumerator in enum:nv50_ir::operation
H A Dnv50_ir_peephole.cpp36 if (op == OP_PHI || op == OP_SPLIT || op == OP_MERGE || op == OP_CONSTRAINT)
136 if (i->op != OP_MERGE || typeSizeof(i->dType) != 8)
726 case OP_MERGE:
2676 bld.mkOp2(OP_MERGE, i->dType, i->getDef(0), def[0], def[1]);
H A Dnv50_ir_lowering_nv50.cpp1828 return bld.mkOp2v(OP_MERGE, TYPE_U32, bld.getSSA(), coords[0], coords[1]);
2107 Instruction *merge = bld.mkOp(OP_MERGE, bytes < 4 ? TYPE_U32 : ty, bld.getSSA(bytes < 4 ? 4 : bytes));

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