Searched refs:OP_MUL (Results 1 - 25 of 34) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_from_common.cpp90 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
H A Dnv50_ir_target_gm107.cpp173 if ((insn->op == OP_MUL || insn->op == OP_MAD) &&
222 case OP_MUL:
H A Dnv50_ir_lowering_nv50.cpp93 i[2] = i[3] = bld->mkOp2(OP_MUL, fTy, t[1], a[1],
96 i[2] = bld->mkOp2(OP_MUL, fTy, t[0], a[0],
467 mul = bld.mkOp2(OP_MUL, add->sType, res, add->getSrc(0), add->getSrc(1));
517 bld.mkOp2(OP_MUL, TYPE_F32, (qf = bld.getSSA()), af, bf)->rnd = ROUND_Z;
522 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q0, b));
527 bld.mkOp2(OP_MUL, TYPE_F32, (qRf = bld.getSSA()), aR, bf)->rnd = ROUND_Z;
534 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q, b));
572 expandIntegerMUL(&bld, bld.mkOp2(OP_MUL, TYPE_U32, m, q, mod->getSrc(1)));
601 case OP_MUL:
740 i->setSrc(c, bld.mkOp2v(OP_MUL, TYPE_F3
[all...]
H A Dnv50_ir_target_nv50.cpp87 { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
116 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN,
121 OP_MOV, OP_ADD, OP_SUB, OP_MUL, OP_MAD, OP_SAD, OP_RCP, OP_LINTERP,
198 opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
345 if ((i->op == OP_MUL || i->op == OP_MAD) && !isFloatType(i->dType)) {
H A Dnv50_ir_target_nvc0.cpp104 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
198 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN,
204 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN
552 if (op != OP_MUL)
582 if (i->op == OP_MUL && i->dType != TYPE_F32)
612 case OP_MUL:
644 case OP_MUL:
H A Dnv50_ir_peephole.cpp563 case OP_MUL:
883 assert(mul2->op == OP_MUL && mul2->dType == TYPE_F32);
887 if (!mul2->src(t).mod && insn->op == OP_MUL && insn->dType == TYPE_F32)
902 if (prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
925 if (insn->op == OP_MUL && insn->dType == TYPE_F32)
928 if (mul2 && prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
944 i->op = OP_MUL;
1047 case OP_MUL:
1209 mul = bld.mkOp2(OP_MUL, TYPE_U32, tA, i->getSrc(0),
1300 bld.mkOp2v(OP_MUL,
[all...]
H A Dnv50_ir_lowering_nvc0.cpp937 i->setSrc(c, bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(),
1244 src[c] = bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(), crd[c], val);
1412 bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(def),
2270 bld.mkOp2(OP_MUL, TYPE_F32, typedDst[i], typedDst[i], bld.loadImm(NULL, 1.0f / ((1 << format->bits[i]) - 1)));
2272 bld.mkOp2(OP_MUL, TYPE_F32, typedDst[i], typedDst[i], bld.loadImm(NULL, 1.0f / ((1 << (format->bits[i] - 1)) - 1)));
2380 su->setSrc(0, bld.mkOp2v(OP_MUL, TYPE_U32, bld.getSSA(), src[0], v));
2387 su->setSrc(2, bld.mkOp2v(OP_MUL, TYPE_U32, bld.getSSA(), src[2], v));
2822 bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(0), i->getDef(0), bld.mkImm(1.0f / 16.0f));
2887 i->op = OP_MUL;
2899 bld.mkOp2(OP_MUL,
[all...]
H A Dnv50_ir_lowering_gm107.cpp162 src[c] = bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(), crd[c], val);
H A Dnv50_ir_from_nir.cpp416 return OP_MUL;
2078 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2860 indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS),
2882 indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS), getSrc(reg.indirect, 0), mkImm(csize));
3145 return mkOp2v(OP_MUL, TYPE_F32, getScratch(), src, proj);
3193 Value *offset = mkOp2v(OP_MUL, TYPE_U32, getSSA(), loadImm(getSSA(), it->first), it->second);
H A Dnv50_ir_from_tgsi.cpp2221 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1)
2335 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
3100 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
3200 if (op == OP_MUL && dstTy == TYPE_F32)
3301 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0)
3328 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1)
H A Dnv50_ir.h54 OP_MUL, enumerator in enum:nv50_ir::operation
H A Dnv50_ir_emit_nv50.cpp1896 case OP_MUL:
2102 if (i->op == OP_MUL && i->rnd != ROUND_N)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_from_common.cpp92 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
H A Dnv50_ir_target_gm107.cpp173 if ((insn->op == OP_MUL || insn->op == OP_MAD) &&
222 case OP_MUL:
H A Dnv50_ir_target_nv50.cpp87 { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
116 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN,
121 OP_MOV, OP_ADD, OP_SUB, OP_MUL, OP_MAD, OP_SAD, OP_RCP, OP_LINTERP,
198 opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
352 if ((i->op == OP_MUL || i->op == OP_MAD) && !isFloatType(i->dType)) {
H A Dnv50_ir_target_nvc0.cpp104 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
198 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN,
204 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN
562 if (op != OP_MUL)
592 if (i->op == OP_MUL && i->dType != TYPE_F32)
622 case OP_MUL:
654 case OP_MUL:
H A Dnv50_ir_lowering_nv50.cpp111 i[2] = i[3] = bld->mkOp2(OP_MUL, fTy, t[1], a[1],
114 i[2] = bld->mkOp2(OP_MUL, fTy, t[0], a[0],
490 mul = bld.mkOp2(OP_MUL, add->sType, res, add->getSrc(0), add->getSrc(1));
540 bld.mkOp2(OP_MUL, TYPE_F32, (qf = bld.getSSA()), af, bf)->rnd = ROUND_Z;
545 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q0, b));
550 bld.mkOp2(OP_MUL, TYPE_F32, (qRf = bld.getSSA()), aR, bf)->rnd = ROUND_Z;
557 bld.mkOp2(OP_MUL, TYPE_U32, (t = bld.getSSA()), q, b));
595 expandIntegerMUL(&bld, bld.mkOp2(OP_MUL, TYPE_U32, m, q, mod->getSrc(1)));
624 case OP_MUL:
794 i->setSrc(c, bld.mkOp2v(OP_MUL, TYPE_F3
[all...]
H A Dnv50_ir_lowering_gv100.cpp283 case OP_MUL:
411 mul = bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(0), i->getDef(0), i->getSrc(1));
431 bld.mkOp2(OP_MUL, i->dType, i->getDef(0), i->getSrc(0), bld.mkImm(f));
H A Dnv50_ir_peephole.cpp579 case OP_MUL:
916 assert(mul2->op == OP_MUL && mul2->dType == TYPE_F32);
920 if (!mul2->src(t).mod && insn->op == OP_MUL && insn->dType == TYPE_F32)
935 if (prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
958 if (insn->op == OP_MUL && insn->dType == TYPE_F32)
961 if (mul2 && prog->getTarget()->isPostMultiplySupported(OP_MUL, f, e)) {
977 i->op = OP_MUL;
1080 case OP_MUL:
1245 mul = bld.mkOp2(OP_MUL, TYPE_U32, tA, i->getSrc(0),
1336 bld.mkOp2v(OP_MUL,
[all...]
H A Dnv50_ir_target_gv100.cpp35 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_MAX, OP_MIN,
317 case OP_MUL:
418 case OP_MUL: return true;
H A Dnv50_ir_lowering_nvc0.cpp951 i->setSrc(c, bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(),
1258 src[c] = bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(), crd[c], val);
1426 bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(def),
2308 bld.mkOp2(OP_MUL, TYPE_F32, typedDst[i], typedDst[i], bld.loadImm(NULL, 1.0f / ((1 << format->bits[i]) - 1)));
2310 bld.mkOp2(OP_MUL, TYPE_F32, typedDst[i], typedDst[i], bld.loadImm(NULL, 1.0f / ((1 << (format->bits[i] - 1)) - 1)));
2425 su->setSrc(2, (src[2] = bld.mkOp2v(OP_MUL, TYPE_U32, bld.getSSA(), src[2], v)));
2501 bld.mkOp2v(OP_MUL, TYPE_U32, bld.getSSA(),
3036 bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(0), i->getDef(0), bld.mkImm(1.0f / 16.0f));
3101 i->op = OP_MUL;
3113 bld.mkOp2(OP_MUL,
[all...]
H A Dnv50_ir_lowering_gm107.cpp181 src[c] = bld.mkOp2v(OP_MUL, TYPE_F32, bld.getSSA(), crd[c], val);
H A Dnv50_ir_from_tgsi.cpp2203 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1)
2317 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
3123 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
3223 if (op == OP_MUL && dstTy == TYPE_F32)
3324 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0)
3351 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1)
H A Dnv50_ir.h54 OP_MUL, enumerator in enum:nv50_ir::operation
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.1.5.rst58 - nv50/ir: fix constant folding for OP_MUL subop HIGH

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