Searched refs:OP_QUADOP (Results 1 - 19 of 19) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_gm107.cpp | 140 add = bld.mkOp2(OP_QUADOP, TYPE_F32, crd[c], tmp, crd[c]);
148 add = bld.mkOp2(OP_QUADOP, TYPE_F32, crd[c], tmp, crd[c]);
227 insn->op = OP_QUADOP;
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| H A D | nv50_ir_target_gm107.cpp | 227 case OP_QUADOP:
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| H A D | nv50_ir.h | 147 OP_QUADOP, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_build_util.cpp | 266 Instruction *quadop = mkOp2(OP_QUADOP, TYPE_F32, def, src0, src1);
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| H A D | nv50_ir_emit_gk110.cpp | 2684 case OP_QUADOP:
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| H A D | nv50_ir_emit_nv50.cpp | 2024 case OP_QUADOP:
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| H A D | nv50_ir_emit_gm107.cpp | 3653 case OP_QUADOP:
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| H A D | nv50_ir_emit_nvc0.cpp | 2878 case OP_QUADOP:
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_gm107.cpp | 159 add = bld.mkOp2(OP_QUADOP, TYPE_F32, crd[c], tmp, crd[c]);
167 add = bld.mkOp2(OP_QUADOP, TYPE_F32, crd[c], tmp, crd[c]);
246 insn->op = OP_QUADOP;
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| H A D | nv50_ir_target_gm107.cpp | 227 case OP_QUADOP:
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| H A D | nv50_ir.h | 150 OP_QUADOP, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_build_util.cpp | 268 Instruction *quadop = mkOp2(OP_QUADOP, TYPE_F32, def, src0, src1);
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| H A D | nv50_ir_target_gv100.cpp | 334 case OP_QUADOP: return &opInfo_FSWZADD;
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| H A D | nv50_ir_emit_gv100.cpp | 1912 case OP_QUADOP:
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| H A D | nv50_ir_emit_gk110.cpp | 2691 case OP_QUADOP:
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| H A D | nv50_ir_emit_nv50.cpp | 2111 case OP_QUADOP:
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| H A D | nv50_ir_emit_gm107.cpp | 3726 case OP_QUADOP:
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| H A D | nv50_ir_emit_nvc0.cpp | 2885 case OP_QUADOP:
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 12.0.2.rst | 349 - nv50/ir: always emit the NDV bit for OP_QUADOP
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