| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 232 case OP_SET_XOR:
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| H A D | nv50_ir_target_nv50.cpp | 117 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT
437 case OP_SET_XOR:
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| H A D | nv50_ir_target_nvc0.cpp | 143 { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
199 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT
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| H A D | nv50_ir_emit_gm107.cpp | 1176 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
1224 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
1563 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
1612 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
2062 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
2108 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
3522 case OP_SET_XOR:
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| H A D | nv50_ir.h | 81 OP_SET_XOR, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_emit_gk110.cpp | 1177 case OP_SET_XOR: code[1] |= 0x2 << 16; break;
2600 case OP_SET_XOR:
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| H A D | nv50_ir_peephole.cpp | 238 insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
2002 logop->op == OP_XOR ? OP_SET_XOR : OP_SET_OR);
2008 set0->op != OP_SET_XOR)
2281 set->op == OP_SET_OR || set->op == OP_SET_XOR) &&
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| H A D | nv50_ir_emit_nvc0.cpp | 1192 case OP_SET_XOR: hi = 0x10400000; break;
2770 case OP_SET_XOR:
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| H A D | nv50_ir_lowering_nvc0.cpp | 353 case OP_SET_XOR:
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 232 case OP_SET_XOR:
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| H A D | nv50_ir_target_nv50.cpp | 117 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT
448 case OP_SET_XOR:
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| H A D | nv50_ir_target_gv100.cpp | 36 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT
346 case OP_SET_XOR:
453 op == OP_SET_XOR)
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| H A D | nv50_ir_emit_gv100.cpp | 523 case OP_SET_XOR: emitField(74, 2, 2); break;
548 case OP_SET_XOR: emitField(74, 2, 2); break;
650 case OP_SET_XOR: emitField(74, 2, 2); break;
743 case OP_SET_XOR: emitField(74, 2, 2); break;
1927 case OP_SET_XOR:
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| H A D | nv50_ir_target_nvc0.cpp | 143 { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
199 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT
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| H A D | nv50_ir_emit_gm107.cpp | 1214 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
1262 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
1601 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
1650 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
2100 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
2146 case OP_SET_XOR: emitField(0x2d, 2, 2); break;
3590 case OP_SET_XOR:
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| H A D | nv50_ir_lowering_gv100.cpp | 273 case OP_SET_XOR:
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| H A D | nv50_ir.h | 83 OP_SET_XOR, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_emit_gk110.cpp | 1175 case OP_SET_XOR: code[1] |= 0x2 << 16; break;
2607 case OP_SET_XOR:
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| H A D | nv50_ir_peephole.cpp | 238 insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
2055 logop->op == OP_XOR ? OP_SET_XOR : OP_SET_OR);
2061 set0->op != OP_SET_XOR)
2334 set->op == OP_SET_OR || set->op == OP_SET_XOR) &&
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| H A D | nv50_ir_emit_nvc0.cpp | 1190 case OP_SET_XOR: hi = 0x10400000; break;
2777 case OP_SET_XOR:
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| H A D | nv50_ir_lowering_nvc0.cpp | 361 case OP_SET_XOR:
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