Searched refs:OP_SIN (Results 1 - 22 of 22) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 134 case OP_SIN:
266 case OP_SIN:
295 case OP_SIN:
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| H A D | nv50_ir_target_nvc0.cpp | 127 { OP_SIN, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
628 case OP_SIN:
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| H A D | nv50_ir_target_nv50.cpp | 547 case OP_SIN:
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| H A D | nv50_ir.h | 88 OP_SIN, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_emit_gm107.cpp | 1409 case OP_SIN: mufu = 1; break;
3549 case OP_SIN:
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| H A D | nv50_ir_emit_gk110.cpp | 2640 case OP_SIN:
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| H A D | nv50_ir_emit_nv50.cpp | 1963 case OP_SIN:
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| H A D | nv50_ir_peephole.cpp | 856 case OP_SIN: res.data.f32 = sinf(imm.reg.data.f32); break;
861 // these should be handled in subsequent OP_SIN/COS/EX2
1506 case OP_SIN:
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| H A D | nv50_ir_emit_nvc0.cpp | 2810 case OP_SIN:
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| H A D | nv50_ir_from_nir.cpp | 451 return OP_SIN;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 134 case OP_SIN:
266 case OP_SIN:
295 case OP_SIN:
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| H A D | nv50_ir_target_nvc0.cpp | 127 { OP_SIN, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
638 case OP_SIN:
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| H A D | nv50_ir_target_nv50.cpp | 558 case OP_SIN:
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| H A D | nv50_ir_emit_gv100.cpp | 596 case OP_SIN : mufu = 1; break;
1816 case OP_SIN:
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| H A D | nv50_ir.h | 90 OP_SIN, enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_target_gv100.cpp | 271 case OP_SIN:
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| H A D | nv50_ir_emit_gm107.cpp | 1447 case OP_SIN: mufu = 1; break;
3617 case OP_SIN:
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| H A D | nv50_ir_emit_gk110.cpp | 2647 case OP_SIN:
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| H A D | nv50_ir_emit_nv50.cpp | 2050 case OP_SIN:
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| H A D | nv50_ir_peephole.cpp | 889 case OP_SIN: res.data.f32 = sinf(imm.reg.data.f32); break;
894 // these should be handled in subsequent OP_SIN/COS/EX2
1553 case OP_SIN:
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| H A D | nv50_ir_emit_nvc0.cpp | 2817 case OP_SIN:
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| H A D | nv50_ir_from_nir.cpp | 487 return OP_SIN;
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