| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 209 case OP_SUSTP:
302 case OP_SUSTP:
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| H A D | nv50_ir_target_nvc0.cpp | 152 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
162 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
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| H A D | nv50_ir_emit_gk110.cpp | 1771 assert(i->op == OP_SUSTP);
1779 if (i->op == OP_SUSTP)
1793 if (i->op == OP_SUSTP)
2734 case OP_SUSTP:
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| H A D | nv50_ir_target_nv50.cpp | 129 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
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| H A D | nv50_ir_lowering_nvc0.cpp | 2152 if (su->op != OP_SUSTP && su->tex.format) {
2344 if (su->op == OP_SUSTB || su->op == OP_SUSTP)
2395 if (su->op != OP_SUSTP && su->tex.format) {
2482 case OP_SUSTP:
2508 if (su->op != OP_SUSTP && su->tex.format) {
3140 case OP_SUSTP:
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| H A D | nv50_ir.h | 132 OP_SUSTP, // surface store (formatted) enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_emit_nvc0.cpp | 2370 if (i->op == OP_SUSTP)
2465 if (i->op == OP_SUSTP)
2850 case OP_SUSTP:
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| H A D | nv50_ir_ra.cpp | 2317 case OP_SUSTP:
2374 if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
2407 if (tex->op == OP_SUSTB || tex->op == OP_SUSTP)
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| H A D | nv50_ir_emit_gm107.cpp | 3676 case OP_SUSTP:
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| H A D | nv50_ir_from_nir.cpp | 546 return OP_SUSTP;
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| H A D | nv50_ir_from_tgsi.cpp | 2796 // For formatted stores, the write mask on OP_SUSTP can be used.
2846 mkTex(OP_SUSTP, tgsi.getImageTarget(), 0, 0, dummy, src);
2905 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
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| H A D | nv50_ir_peephole.cpp | 69 op == OP_SUSTB || op == OP_SUSTP || op == OP_SUREDP || op == OP_SUREDB ||
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 209 case OP_SUSTP:
302 case OP_SUSTP:
|
| H A D | nv50_ir_target_nvc0.cpp | 152 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
162 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
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| H A D | nv50_ir_emit_gk110.cpp | 1778 assert(i->op == OP_SUSTP);
1786 if (i->op == OP_SUSTP)
1800 if (i->op == OP_SUSTP)
2741 case OP_SUSTP:
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| H A D | nv50_ir_target_nv50.cpp | 129 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
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| H A D | nv50_ir_lowering_nvc0.cpp | 2173 if (su->op != OP_SUSTP && su->tex.format) {
2382 if (su->op == OP_SUSTB || su->op == OP_SUSTP)
2519 if (su->op != OP_SUSTP && su->tex.format) {
2608 case OP_SUSTP:
2653 if (su->op != OP_SUSTP && su->tex.format) {
3354 case OP_SUSTP:
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| H A D | nv50_ir.h | 135 OP_SUSTP, // surface store (formatted) enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_target_gv100.cpp | 391 case OP_SUSTP: return &opInfo_SUST;
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| H A D | nv50_ir_emit_nvc0.cpp | 2377 if (i->op == OP_SUSTP)
2472 if (i->op == OP_SUSTP)
2857 case OP_SUSTP:
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| H A D | nv50_ir_ra.cpp | 2379 case OP_SUSTP:
2436 if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
2469 if (tex->op == OP_SUSTB || tex->op == OP_SUSTP)
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| H A D | nv50_ir_emit_gv100.cpp | 1982 case OP_SUSTP:
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| H A D | nv50_ir_emit_gm107.cpp | 3749 case OP_SUSTP:
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| H A D | nv50_ir_from_nir.cpp | 574 return OP_SUSTP;
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| H A D | nv50_ir_lowering_nv50.cpp | 2235 case OP_SUSTP:
|