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    Searched refs:OUT_ACCEL_REG (Results 1 - 10 of 10) sorted by relevancy

  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_commonfuncs.c 69 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
70 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
71 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
88 OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
89 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
91 OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
92 OUT_ACCEL_REG(R300_GB_SELECT, 0);
93 OUT_ACCEL_REG(R300_GB_ENABLE, 0);
101 OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
102 OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0)
    [all...]
radeon_textured_videofuncs.c 147 OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
149 OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
197 OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format);
200 OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
218 OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
222 OUT_ACCEL_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE |
228 OUT_ACCEL_REG(RADEON_PP_TXFILTER_0,
234 OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat | RADEON_TXFORMAT_ST_ROUTE_STQ0);
236 OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
242 OUT_ACCEL_REG(RADEON_PP_TXABLEND_0
    [all...]
radeon_render.c 481 OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
482 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size);
483 OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, dst_pitch - 32);
484 OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation +
486 OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR |
533 OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
534 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
536 OUT_ACCEL_REG(RADEON_PP_TFACTOR_0, srccolor);
537 OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_TFACTOR_COLOR |
539 OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
    [all...]
radeon_accelfuncs.c 147 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip);
148 OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color);
149 OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
150 OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT
155 OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
156 OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
175 OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset |
177 OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x);
178 OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
201 OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT
    [all...]
radeon_exa_render.c 468 OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, txfilter);
469 OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
470 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
473 OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, txpitch - 32);
478 OUT_ACCEL_REG(RADEON_PP_TXFILTER_1, txfilter);
479 OUT_ACCEL_REG(RADEON_PP_TXFORMAT_1, txformat);
481 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_1,
484 OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_1, txpitch - 32);
691 OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl);
692 OUT_ACCEL_REG(RADEON_RB3D_CNTL, dst_format | RADEON_ALPHA_BLEND_ENABLE)
    [all...]
radeon_exa_funcs.c 107 OUT_ACCEL_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
108 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
109 OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
110 OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
111 OUT_ACCEL_REG(RADEON_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr);
112 OUT_ACCEL_REG(RADEON_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr);
113 OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask);
114 OUT_ACCEL_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
116 OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
121 OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset)
    [all...]
radeon_macros.h 179 OUT_ACCEL_REG((reg), (value)); \
184 OUT_ACCEL_REG((reg), _pix_offset | value); \
193 OUT_ACCEL_REG((reg), (offset)); \
196 OUT_ACCEL_REG((reg), (offset) + info->fbLocation + pScrn->fbOffset);} \
202 OUT_ACCEL_REG((reg), value); \
205 OUT_ACCEL_REG((reg), value); \
radeon_textured_video.c 150 #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
160 #undef OUT_ACCEL_REG
172 #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
173 #define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val))
183 #undef OUT_ACCEL_REG
radeon_exa.c 665 #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
678 #undef OUT_ACCEL_REG
690 #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
704 #undef OUT_ACCEL_REG
radeon_accel.c 590 #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
602 #undef OUT_ACCEL_REG
612 #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
625 #undef OUT_ACCEL_REG

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