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Searched refs:R600_UVD_ENABLE_TILING (Results 1 - 2 of 2) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A D	r600_uvd.c	`53 #define R600_UVD_ENABLE_TILING 0 macro 83 if (ctx->b.chip_class < EVERGREEN \|\| tmpl->interlaced \|\| !R600_UVD_ENABLE_TILING) 92 if (ctx->b.chip_class < EVERGREEN \|\| tmpl->interlaced \|\| !R600_UVD_ENABLE_TILING) 102 if (ctx->b.chip_class < EVERGREEN \|\| tmpl->interlaced \|\| !R600_UVD_ENABLE_TILING)`
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A D	r600_uvd.c	`53 #define R600_UVD_ENABLE_TILING 0 macro 84 if (ctx->b.chip_class < EVERGREEN \|\| tmpl->interlaced \|\| !R600_UVD_ENABLE_TILING) 94 if (ctx->b.chip_class < EVERGREEN \|\| tmpl->interlaced \|\| !R600_UVD_ENABLE_TILING) 105 if (ctx->b.chip_class < EVERGREEN \|\| tmpl->interlaced \|\| !R600_UVD_ENABLE_TILING)`

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