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    Searched refs:SVBI (Results 1 - 3 of 3) sorted by relevancy

  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
brw_ff_gs.h 86 struct brw_reg SVBI;
brw_ff_gs_emit.c 48 * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
65 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
361 get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
364 get_element_ud(c->reg.SVBI, 4));
367 /* Compute the destination indices to write to. Usually we use SVBI[0]
372 * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
373 * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
377 * packed-word execution mode, and SVBI is a double-word, we need to
379 * or (1, 0, 2)) to the destination_indices register, and then add SVBI
413 c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0))
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_compile_ff_gs.c 52 struct brw_reg SVBI;
76 * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
93 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
390 get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
393 get_element_ud(c->reg.SVBI, 4));
396 /* Compute the destination indices to write to. Usually we use SVBI[0]
401 * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
402 * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
406 * packed-word execution mode, and SVBI is a double-word, we need to
408 * or (1, 0, 2)) to the destination_indices register, and then add SVBI
    [all...]

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