1 /* 2 * (C) Copyright IBM Corporation 2006 3 * Copyright 2009 Red Hat, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 /* 26 * Copyright (c) 2007 Paulo R. Zanoni, Tiago Vignatti 27 * 28 * Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use, 32 * copy, modify, merge, publish, distribute, sublicense, and/or sell 33 * copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 * 49 */ 50 51 /** 52 * \file pciaccess.h 53 * 54 * \author Ian Romanick <idr (at) us.ibm.com> 55 */ 56 57 #ifndef PCIACCESS_H 58 #define PCIACCESS_H 59 60 #include <inttypes.h> 61 62 #if (__GNUC__ >= 3) || (__SUNPRO_C >= 0x5130) 63 #define __deprecated __attribute__((deprecated)) 64 #else 65 #define __deprecated 66 #endif 67 68 typedef uint64_t pciaddr_t; 69 70 struct pci_device; 71 struct pci_device_iterator; 72 struct pci_id_match; 73 struct pci_slot_match; 74 75 #ifdef __cplusplus 76 extern "C" { 77 #endif 78 79 int pci_device_has_kernel_driver(struct pci_device *dev); 80 81 int pci_device_is_boot_vga(struct pci_device *dev); 82 83 int pci_device_read_rom(struct pci_device *dev, void *buffer); 84 85 int __deprecated pci_device_map_region(struct pci_device *dev, 86 unsigned region, int write_enable); 87 88 int __deprecated pci_device_unmap_region(struct pci_device *dev, 89 unsigned region); 90 91 int pci_device_map_range(struct pci_device *dev, pciaddr_t base, 92 pciaddr_t size, unsigned map_flags, void **addr); 93 94 int pci_device_unmap_range(struct pci_device *dev, void *memory, 95 pciaddr_t size); 96 97 int __deprecated pci_device_map_memory_range(struct pci_device *dev, 98 pciaddr_t base, pciaddr_t size, int write_enable, void **addr); 99 100 int __deprecated pci_device_unmap_memory_range(struct pci_device *dev, 101 void *memory, pciaddr_t size); 102 103 int pci_device_probe(struct pci_device *dev); 104 105 const struct pci_agp_info *pci_device_get_agp_info(struct pci_device *dev); 106 107 const struct pci_bridge_info *pci_device_get_bridge_info( 108 struct pci_device *dev); 109 110 const struct pci_pcmcia_bridge_info *pci_device_get_pcmcia_bridge_info( 111 struct pci_device *dev); 112 113 int pci_device_get_bridge_buses(struct pci_device *dev, int *primary_bus, 114 int *secondary_bus, int *subordinate_bus); 115 116 int pci_system_init(void); 117 118 void pci_system_init_dev_mem(int fd); 119 120 void pci_system_cleanup(void); 121 122 struct pci_device_iterator *pci_slot_match_iterator_create( 123 const struct pci_slot_match *match); 124 125 struct pci_device_iterator *pci_id_match_iterator_create( 126 const struct pci_id_match *match); 127 128 void pci_iterator_destroy(struct pci_device_iterator *iter); 129 130 struct pci_device *pci_device_next(struct pci_device_iterator *iter); 131 132 struct pci_device *pci_device_find_by_slot(uint32_t domain, uint32_t bus, 133 uint32_t dev, uint32_t func); 134 135 struct pci_device *pci_device_get_parent_bridge(struct pci_device *dev); 136 137 void pci_get_strings(const struct pci_id_match *m, 138 const char **device_name, const char **vendor_name, 139 const char **subdevice_name, const char **subvendor_name); 140 const char *pci_device_get_device_name(const struct pci_device *dev); 141 const char *pci_device_get_subdevice_name(const struct pci_device *dev); 142 const char *pci_device_get_vendor_name(const struct pci_device *dev); 143 const char *pci_device_get_subvendor_name(const struct pci_device *dev); 144 145 void pci_device_enable(struct pci_device *dev); 146 void pci_device_disable(struct pci_device *dev); 147 148 int pci_device_cfg_read (struct pci_device *dev, void *data, 149 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read); 150 int pci_device_cfg_read_u8 (struct pci_device *dev, uint8_t *data, 151 pciaddr_t offset); 152 int pci_device_cfg_read_u16(struct pci_device *dev, uint16_t *data, 153 pciaddr_t offset); 154 int pci_device_cfg_read_u32(struct pci_device *dev, uint32_t *data, 155 pciaddr_t offset); 156 157 int pci_device_cfg_write (struct pci_device *dev, const void *data, 158 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written); 159 int pci_device_cfg_write_u8 (struct pci_device *dev, uint8_t data, 160 pciaddr_t offset); 161 int pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data, 162 pciaddr_t offset); 163 int pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data, 164 pciaddr_t offset); 165 int pci_device_cfg_write_bits(struct pci_device *dev, uint32_t mask, 166 uint32_t data, pciaddr_t offset); 167 168 #ifdef __cplusplus 169 } 170 #endif 171 172 /** 173 * \name Mapping flags passed to \c pci_device_map_range 174 */ 175 /*@{*/ 176 #define PCI_DEV_MAP_FLAG_WRITABLE (1U<<0) 177 #define PCI_DEV_MAP_FLAG_WRITE_COMBINE (1U<<1) 178 #define PCI_DEV_MAP_FLAG_CACHABLE (1U<<2) 179 /*@}*/ 180 181 182 #define PCI_MATCH_ANY (~0U) 183 184 /** 185 * Compare two PCI ID values (either vendor or device). This is used 186 * internally to compare the fields of \c pci_id_match to the fields of 187 * \c pci_device. 188 */ 189 #define PCI_ID_COMPARE(a, b) \ 190 (((a) == PCI_MATCH_ANY) || ((a) == (b))) 191 192 /** 193 */ 194 struct pci_id_match { 195 /** 196 * \name Device / vendor matching controls 197 * 198 * Control the search based on the device, vendor, subdevice, or subvendor 199 * IDs. Setting any of these fields to \c PCI_MATCH_ANY will cause the 200 * field to not be used in the comparison. 201 */ 202 /*@{*/ 203 uint32_t vendor_id; 204 uint32_t device_id; 205 uint32_t subvendor_id; 206 uint32_t subdevice_id; 207 /*@}*/ 208 209 210 /** 211 * \name Device class matching controls 212 * 213 */ 214 /*@{*/ 215 uint32_t device_class; 216 uint32_t device_class_mask; 217 /*@}*/ 218 219 intptr_t match_data; 220 }; 221 222 223 /** 224 */ 225 struct pci_slot_match { 226 /** 227 * \name Device slot matching controls 228 * 229 * Control the search based on the domain, bus, slot, and function of 230 * the device. Setting any of these fields to \c PCI_MATCH_ANY will cause 231 * the field to not be used in the comparison. 232 */ 233 /*@{*/ 234 uint32_t domain; 235 uint32_t bus; 236 uint32_t dev; 237 uint32_t func; 238 /*@}*/ 239 240 intptr_t match_data; 241 }; 242 243 /** 244 * BAR descriptor for a PCI device. 245 */ 246 struct pci_mem_region { 247 /** 248 * When the region is mapped, this is the pointer to the memory. 249 * 250 * This field is \b only set when the deprecated \c pci_device_map_region 251 * interface is used. Use \c pci_device_map_range instead. 252 * 253 * \deprecated 254 */ 255 void *memory; 256 257 258 /** 259 * Base physical address of the region within its bus / domain. 260 * 261 * \warning 262 * This address is really only useful to other devices in the same 263 * domain. It's probably \b not the address applications will ever 264 * use. 265 * 266 * \warning 267 * Most (all?) platform back-ends leave this field unset. 268 */ 269 pciaddr_t bus_addr; 270 271 272 /** 273 * Base physical address of the region from the CPU's point of view. 274 * 275 * This address is typically passed to \c pci_device_map_range to create 276 * a mapping of the region to the CPU's virtual address space. 277 */ 278 pciaddr_t base_addr; 279 280 281 /** 282 * Size, in bytes, of the region. 283 */ 284 pciaddr_t size; 285 286 287 /** 288 * Is the region I/O ports or memory? 289 */ 290 unsigned is_IO:1; 291 292 /** 293 * Is the memory region prefetchable? 294 * 295 * \note 296 * This can only be set if \c is_IO is not set. 297 */ 298 unsigned is_prefetchable:1; 299 300 301 /** 302 * Is the memory at a 64-bit address? 303 * 304 * \note 305 * This can only be set if \c is_IO is not set. 306 */ 307 unsigned is_64:1; 308 }; 309 310 311 /** 312 * PCI device. 313 * 314 * Contains all of the information about a particular PCI device. 315 * 316 * This structure - like everything else in libpciaccess - is allocated 317 * by the library itself. Do not embed this structure in other structs, 318 * or otherwise allocate them yourself. 319 */ 320 struct pci_device { 321 /** 322 * \name Device bus identification. 323 * 324 * Complete bus identification, including domain, of the device. On 325 * platforms that do not support PCI domains (e.g., 32-bit x86 hardware), 326 * the domain will always be zero. 327 * 328 * The domain_16 field is provided for binary compatibility with older 329 * libpciaccess. 330 */ 331 /*@{*/ 332 uint16_t domain_16; 333 uint8_t bus; 334 uint8_t dev; 335 uint8_t func; 336 /*@}*/ 337 338 339 /** 340 * \name Vendor / device ID 341 * 342 * The vendor ID, device ID, and sub-IDs for the device. 343 */ 344 /*@{*/ 345 uint16_t vendor_id; 346 uint16_t device_id; 347 uint16_t subvendor_id; 348 uint16_t subdevice_id; 349 /*@}*/ 350 351 /** 352 * Device's class, subclass, and programming interface packed into a 353 * single 32-bit value. The class is at bits [23:16], subclass is at 354 * bits [15:8], and programming interface is at [7:0]. 355 */ 356 uint32_t device_class; 357 358 359 /** 360 * Device revision number, as read from the configuration header. 361 */ 362 uint8_t revision; 363 364 365 /** 366 * BAR descriptors for the device. 367 */ 368 struct pci_mem_region regions[6]; 369 370 371 /** 372 * Size, in bytes, of the device's expansion ROM. 373 */ 374 pciaddr_t rom_size; 375 376 377 /** 378 * IRQ associated with the device. If there is no IRQ, this value will 379 * be -1. 380 */ 381 int irq; 382 383 384 /** 385 * Storage for user data. Users of the library can store arbitrary 386 * data in this pointer. The library will not use it for any purpose. 387 * It is the user's responsibility to free this memory before destroying 388 * the \c pci_device structure. 389 */ 390 intptr_t user_data; 391 392 /** 393 * Used by the VGA arbiter. Type of resource decoded by the device and 394 * the file descriptor (/dev/vga_arbiter). */ 395 int vgaarb_rsrc; 396 397 398 /** 399 * PCI domain value (full 32 bits) 400 */ 401 uint32_t domain; 402 }; 403 404 405 /** 406 * Description of the AGP capability of the device. 407 * 408 * \sa pci_device_get_agp_info 409 */ 410 struct pci_agp_info { 411 /** 412 * Offset of the AGP registers in the devices configuration register 413 * space. This is generally used so that the offset of the AGP command 414 * register can be determined. 415 */ 416 unsigned config_offset; 417 418 419 /** 420 * \name AGP major / minor version. 421 */ 422 /*@{*/ 423 uint8_t major_version; 424 uint8_t minor_version; 425 /*@}*/ 426 427 /** 428 * Logical OR of the supported AGP rates. For example, a value of 0x07 429 * means that the device can support 1x, 2x, and 4x. A value of 0x0c 430 * means that the device can support 8x and 4x. 431 */ 432 uint8_t rates; 433 434 unsigned int fast_writes:1; /**< Are fast-writes supported? */ 435 unsigned int addr64:1; 436 unsigned int htrans:1; 437 unsigned int gart64:1; 438 unsigned int coherent:1; 439 unsigned int sideband:1; /**< Is side-band addressing supported? */ 440 unsigned int isochronus:1; 441 442 uint8_t async_req_size; 443 uint8_t calibration_cycle_timing; 444 uint8_t max_requests; 445 }; 446 447 /** 448 * Description of a PCI-to-PCI bridge device. 449 * 450 * \sa pci_device_get_bridge_info 451 */ 452 struct pci_bridge_info { 453 uint8_t primary_bus; 454 uint8_t secondary_bus; 455 uint8_t subordinate_bus; 456 uint8_t secondary_latency_timer; 457 458 uint8_t io_type; 459 uint8_t mem_type; 460 uint8_t prefetch_mem_type; 461 462 uint16_t secondary_status; 463 uint16_t bridge_control; 464 465 uint32_t io_base; 466 uint32_t io_limit; 467 468 uint32_t mem_base; 469 uint32_t mem_limit; 470 471 uint64_t prefetch_mem_base; 472 uint64_t prefetch_mem_limit; 473 }; 474 475 /** 476 * Description of a PCI-to-PCMCIA bridge device. 477 * 478 * \sa pci_device_get_pcmcia_bridge_info 479 */ 480 struct pci_pcmcia_bridge_info { 481 uint8_t primary_bus; 482 uint8_t card_bus; 483 uint8_t subordinate_bus; 484 uint8_t cardbus_latency_timer; 485 486 uint16_t secondary_status; 487 uint16_t bridge_control; 488 489 struct { 490 uint32_t base; 491 uint32_t limit; 492 } io[2]; 493 494 struct { 495 uint32_t base; 496 uint32_t limit; 497 } mem[2]; 498 499 }; 500 501 502 /** 503 * VGA Arbiter definitions, functions and related. 504 */ 505 506 /* Legacy VGA regions */ 507 #define VGA_ARB_RSRC_NONE 0x00 508 #define VGA_ARB_RSRC_LEGACY_IO 0x01 509 #define VGA_ARB_RSRC_LEGACY_MEM 0x02 510 /* Non-legacy access */ 511 #define VGA_ARB_RSRC_NORMAL_IO 0x04 512 #define VGA_ARB_RSRC_NORMAL_MEM 0x08 513 514 int pci_device_vgaarb_init (void); 515 void pci_device_vgaarb_fini (void); 516 int pci_device_vgaarb_set_target (struct pci_device *dev); 517 /* use the targeted device */ 518 int pci_device_vgaarb_decodes (int new_vga_rsrc); 519 int pci_device_vgaarb_lock (void); 520 int pci_device_vgaarb_trylock (void); 521 int pci_device_vgaarb_unlock (void); 522 /* return the current device count + resource decodes for the device */ 523 int pci_device_vgaarb_get_info (struct pci_device *dev, int *vga_count, int *rsrc_decodes); 524 525 /* 526 * I/O space access. 527 */ 528 529 struct pci_io_handle; 530 531 struct pci_io_handle *pci_device_open_io(struct pci_device *dev, pciaddr_t base, 532 pciaddr_t size); 533 struct pci_io_handle *pci_legacy_open_io(struct pci_device *dev, pciaddr_t base, 534 pciaddr_t size); 535 void pci_device_close_io(struct pci_device *dev, struct pci_io_handle *handle); 536 uint32_t pci_io_read32(struct pci_io_handle *handle, uint32_t reg); 537 uint16_t pci_io_read16(struct pci_io_handle *handle, uint32_t reg); 538 uint8_t pci_io_read8(struct pci_io_handle *handle, uint32_t reg); 539 void pci_io_write32(struct pci_io_handle *handle, uint32_t reg, uint32_t data); 540 void pci_io_write16(struct pci_io_handle *handle, uint32_t reg, uint16_t data); 541 void pci_io_write8(struct pci_io_handle *handle, uint32_t reg, uint8_t data); 542 543 /* 544 * Legacy memory access 545 */ 546 547 int pci_device_map_legacy(struct pci_device *dev, pciaddr_t base, 548 pciaddr_t size, unsigned map_flags, void **addr); 549 int pci_device_unmap_legacy(struct pci_device *dev, void *addr, pciaddr_t size); 550 551 #endif /* PCIACCESS_H */ 552
Indexes created Fri Jul 03 00:25:33 UTC 2026