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      1 /* Copyright (C) 2015 Broadcom
      2  *
      3  * Permission is hereby granted, free of charge, to any person obtaining a
      4  * copy of this software and associated documentation files (the "Software"),
      5  * to deal in the Software without restriction, including without limitation
      6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      7  * and/or sell copies of the Software, and to permit persons to whom the
      8  * Software is furnished to do so, subject to the following conditions:
      9  *
     10  * The above copyright notice and this permission notice (including the next
     11  * paragraph) shall be included in all copies or substantial portions of the
     12  * Software.
     13  *
     14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
     20  * IN THE SOFTWARE.
     21  */
     22 
     23 #ifndef _NIR_BUILDER_OPCODES_
     24 #define _NIR_BUILDER_OPCODES_
     25 
     26 
     27 
     28 static inline nir_ssa_def *
     29 nir_amul(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     30 {
     31    return nir_build_alu(build, nir_op_amul, src0, src1, NULL, NULL);
     32 }
     33 static inline nir_ssa_def *
     34 nir_b16all_fequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     35 {
     36    return nir_build_alu(build, nir_op_b16all_fequal16, src0, src1, NULL, NULL);
     37 }
     38 static inline nir_ssa_def *
     39 nir_b16all_fequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     40 {
     41    return nir_build_alu(build, nir_op_b16all_fequal2, src0, src1, NULL, NULL);
     42 }
     43 static inline nir_ssa_def *
     44 nir_b16all_fequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     45 {
     46    return nir_build_alu(build, nir_op_b16all_fequal3, src0, src1, NULL, NULL);
     47 }
     48 static inline nir_ssa_def *
     49 nir_b16all_fequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     50 {
     51    return nir_build_alu(build, nir_op_b16all_fequal4, src0, src1, NULL, NULL);
     52 }
     53 static inline nir_ssa_def *
     54 nir_b16all_fequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     55 {
     56    return nir_build_alu(build, nir_op_b16all_fequal5, src0, src1, NULL, NULL);
     57 }
     58 static inline nir_ssa_def *
     59 nir_b16all_fequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     60 {
     61    return nir_build_alu(build, nir_op_b16all_fequal8, src0, src1, NULL, NULL);
     62 }
     63 static inline nir_ssa_def *
     64 nir_b16all_iequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     65 {
     66    return nir_build_alu(build, nir_op_b16all_iequal16, src0, src1, NULL, NULL);
     67 }
     68 static inline nir_ssa_def *
     69 nir_b16all_iequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     70 {
     71    return nir_build_alu(build, nir_op_b16all_iequal2, src0, src1, NULL, NULL);
     72 }
     73 static inline nir_ssa_def *
     74 nir_b16all_iequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     75 {
     76    return nir_build_alu(build, nir_op_b16all_iequal3, src0, src1, NULL, NULL);
     77 }
     78 static inline nir_ssa_def *
     79 nir_b16all_iequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     80 {
     81    return nir_build_alu(build, nir_op_b16all_iequal4, src0, src1, NULL, NULL);
     82 }
     83 static inline nir_ssa_def *
     84 nir_b16all_iequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     85 {
     86    return nir_build_alu(build, nir_op_b16all_iequal5, src0, src1, NULL, NULL);
     87 }
     88 static inline nir_ssa_def *
     89 nir_b16all_iequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     90 {
     91    return nir_build_alu(build, nir_op_b16all_iequal8, src0, src1, NULL, NULL);
     92 }
     93 static inline nir_ssa_def *
     94 nir_b16any_fnequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
     95 {
     96    return nir_build_alu(build, nir_op_b16any_fnequal16, src0, src1, NULL, NULL);
     97 }
     98 static inline nir_ssa_def *
     99 nir_b16any_fnequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    100 {
    101    return nir_build_alu(build, nir_op_b16any_fnequal2, src0, src1, NULL, NULL);
    102 }
    103 static inline nir_ssa_def *
    104 nir_b16any_fnequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    105 {
    106    return nir_build_alu(build, nir_op_b16any_fnequal3, src0, src1, NULL, NULL);
    107 }
    108 static inline nir_ssa_def *
    109 nir_b16any_fnequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    110 {
    111    return nir_build_alu(build, nir_op_b16any_fnequal4, src0, src1, NULL, NULL);
    112 }
    113 static inline nir_ssa_def *
    114 nir_b16any_fnequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    115 {
    116    return nir_build_alu(build, nir_op_b16any_fnequal5, src0, src1, NULL, NULL);
    117 }
    118 static inline nir_ssa_def *
    119 nir_b16any_fnequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    120 {
    121    return nir_build_alu(build, nir_op_b16any_fnequal8, src0, src1, NULL, NULL);
    122 }
    123 static inline nir_ssa_def *
    124 nir_b16any_inequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    125 {
    126    return nir_build_alu(build, nir_op_b16any_inequal16, src0, src1, NULL, NULL);
    127 }
    128 static inline nir_ssa_def *
    129 nir_b16any_inequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    130 {
    131    return nir_build_alu(build, nir_op_b16any_inequal2, src0, src1, NULL, NULL);
    132 }
    133 static inline nir_ssa_def *
    134 nir_b16any_inequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    135 {
    136    return nir_build_alu(build, nir_op_b16any_inequal3, src0, src1, NULL, NULL);
    137 }
    138 static inline nir_ssa_def *
    139 nir_b16any_inequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    140 {
    141    return nir_build_alu(build, nir_op_b16any_inequal4, src0, src1, NULL, NULL);
    142 }
    143 static inline nir_ssa_def *
    144 nir_b16any_inequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    145 {
    146    return nir_build_alu(build, nir_op_b16any_inequal5, src0, src1, NULL, NULL);
    147 }
    148 static inline nir_ssa_def *
    149 nir_b16any_inequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    150 {
    151    return nir_build_alu(build, nir_op_b16any_inequal8, src0, src1, NULL, NULL);
    152 }
    153 static inline nir_ssa_def *
    154 nir_b16csel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    155 {
    156    return nir_build_alu(build, nir_op_b16csel, src0, src1, src2, NULL);
    157 }
    158 static inline nir_ssa_def *
    159 nir_b2b1(nir_builder *build, nir_ssa_def *src0)
    160 {
    161    return nir_build_alu(build, nir_op_b2b1, src0, NULL, NULL, NULL);
    162 }
    163 static inline nir_ssa_def *
    164 nir_b2b16(nir_builder *build, nir_ssa_def *src0)
    165 {
    166    return nir_build_alu(build, nir_op_b2b16, src0, NULL, NULL, NULL);
    167 }
    168 static inline nir_ssa_def *
    169 nir_b2b32(nir_builder *build, nir_ssa_def *src0)
    170 {
    171    return nir_build_alu(build, nir_op_b2b32, src0, NULL, NULL, NULL);
    172 }
    173 static inline nir_ssa_def *
    174 nir_b2b8(nir_builder *build, nir_ssa_def *src0)
    175 {
    176    return nir_build_alu(build, nir_op_b2b8, src0, NULL, NULL, NULL);
    177 }
    178 static inline nir_ssa_def *
    179 nir_b2f16(nir_builder *build, nir_ssa_def *src0)
    180 {
    181    return nir_build_alu(build, nir_op_b2f16, src0, NULL, NULL, NULL);
    182 }
    183 static inline nir_ssa_def *
    184 nir_b2f32(nir_builder *build, nir_ssa_def *src0)
    185 {
    186    return nir_build_alu(build, nir_op_b2f32, src0, NULL, NULL, NULL);
    187 }
    188 static inline nir_ssa_def *
    189 nir_b2f64(nir_builder *build, nir_ssa_def *src0)
    190 {
    191    return nir_build_alu(build, nir_op_b2f64, src0, NULL, NULL, NULL);
    192 }
    193 static inline nir_ssa_def *
    194 nir_b2i1(nir_builder *build, nir_ssa_def *src0)
    195 {
    196    return nir_build_alu(build, nir_op_b2i1, src0, NULL, NULL, NULL);
    197 }
    198 static inline nir_ssa_def *
    199 nir_b2i16(nir_builder *build, nir_ssa_def *src0)
    200 {
    201    return nir_build_alu(build, nir_op_b2i16, src0, NULL, NULL, NULL);
    202 }
    203 static inline nir_ssa_def *
    204 nir_b2i32(nir_builder *build, nir_ssa_def *src0)
    205 {
    206    return nir_build_alu(build, nir_op_b2i32, src0, NULL, NULL, NULL);
    207 }
    208 static inline nir_ssa_def *
    209 nir_b2i64(nir_builder *build, nir_ssa_def *src0)
    210 {
    211    return nir_build_alu(build, nir_op_b2i64, src0, NULL, NULL, NULL);
    212 }
    213 static inline nir_ssa_def *
    214 nir_b2i8(nir_builder *build, nir_ssa_def *src0)
    215 {
    216    return nir_build_alu(build, nir_op_b2i8, src0, NULL, NULL, NULL);
    217 }
    218 static inline nir_ssa_def *
    219 nir_b32all_fequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    220 {
    221    return nir_build_alu(build, nir_op_b32all_fequal16, src0, src1, NULL, NULL);
    222 }
    223 static inline nir_ssa_def *
    224 nir_b32all_fequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    225 {
    226    return nir_build_alu(build, nir_op_b32all_fequal2, src0, src1, NULL, NULL);
    227 }
    228 static inline nir_ssa_def *
    229 nir_b32all_fequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    230 {
    231    return nir_build_alu(build, nir_op_b32all_fequal3, src0, src1, NULL, NULL);
    232 }
    233 static inline nir_ssa_def *
    234 nir_b32all_fequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    235 {
    236    return nir_build_alu(build, nir_op_b32all_fequal4, src0, src1, NULL, NULL);
    237 }
    238 static inline nir_ssa_def *
    239 nir_b32all_fequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    240 {
    241    return nir_build_alu(build, nir_op_b32all_fequal5, src0, src1, NULL, NULL);
    242 }
    243 static inline nir_ssa_def *
    244 nir_b32all_fequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    245 {
    246    return nir_build_alu(build, nir_op_b32all_fequal8, src0, src1, NULL, NULL);
    247 }
    248 static inline nir_ssa_def *
    249 nir_b32all_iequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    250 {
    251    return nir_build_alu(build, nir_op_b32all_iequal16, src0, src1, NULL, NULL);
    252 }
    253 static inline nir_ssa_def *
    254 nir_b32all_iequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    255 {
    256    return nir_build_alu(build, nir_op_b32all_iequal2, src0, src1, NULL, NULL);
    257 }
    258 static inline nir_ssa_def *
    259 nir_b32all_iequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    260 {
    261    return nir_build_alu(build, nir_op_b32all_iequal3, src0, src1, NULL, NULL);
    262 }
    263 static inline nir_ssa_def *
    264 nir_b32all_iequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    265 {
    266    return nir_build_alu(build, nir_op_b32all_iequal4, src0, src1, NULL, NULL);
    267 }
    268 static inline nir_ssa_def *
    269 nir_b32all_iequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    270 {
    271    return nir_build_alu(build, nir_op_b32all_iequal5, src0, src1, NULL, NULL);
    272 }
    273 static inline nir_ssa_def *
    274 nir_b32all_iequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    275 {
    276    return nir_build_alu(build, nir_op_b32all_iequal8, src0, src1, NULL, NULL);
    277 }
    278 static inline nir_ssa_def *
    279 nir_b32any_fnequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    280 {
    281    return nir_build_alu(build, nir_op_b32any_fnequal16, src0, src1, NULL, NULL);
    282 }
    283 static inline nir_ssa_def *
    284 nir_b32any_fnequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    285 {
    286    return nir_build_alu(build, nir_op_b32any_fnequal2, src0, src1, NULL, NULL);
    287 }
    288 static inline nir_ssa_def *
    289 nir_b32any_fnequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    290 {
    291    return nir_build_alu(build, nir_op_b32any_fnequal3, src0, src1, NULL, NULL);
    292 }
    293 static inline nir_ssa_def *
    294 nir_b32any_fnequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    295 {
    296    return nir_build_alu(build, nir_op_b32any_fnequal4, src0, src1, NULL, NULL);
    297 }
    298 static inline nir_ssa_def *
    299 nir_b32any_fnequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    300 {
    301    return nir_build_alu(build, nir_op_b32any_fnequal5, src0, src1, NULL, NULL);
    302 }
    303 static inline nir_ssa_def *
    304 nir_b32any_fnequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    305 {
    306    return nir_build_alu(build, nir_op_b32any_fnequal8, src0, src1, NULL, NULL);
    307 }
    308 static inline nir_ssa_def *
    309 nir_b32any_inequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    310 {
    311    return nir_build_alu(build, nir_op_b32any_inequal16, src0, src1, NULL, NULL);
    312 }
    313 static inline nir_ssa_def *
    314 nir_b32any_inequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    315 {
    316    return nir_build_alu(build, nir_op_b32any_inequal2, src0, src1, NULL, NULL);
    317 }
    318 static inline nir_ssa_def *
    319 nir_b32any_inequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    320 {
    321    return nir_build_alu(build, nir_op_b32any_inequal3, src0, src1, NULL, NULL);
    322 }
    323 static inline nir_ssa_def *
    324 nir_b32any_inequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    325 {
    326    return nir_build_alu(build, nir_op_b32any_inequal4, src0, src1, NULL, NULL);
    327 }
    328 static inline nir_ssa_def *
    329 nir_b32any_inequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    330 {
    331    return nir_build_alu(build, nir_op_b32any_inequal5, src0, src1, NULL, NULL);
    332 }
    333 static inline nir_ssa_def *
    334 nir_b32any_inequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    335 {
    336    return nir_build_alu(build, nir_op_b32any_inequal8, src0, src1, NULL, NULL);
    337 }
    338 static inline nir_ssa_def *
    339 nir_b32csel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    340 {
    341    return nir_build_alu(build, nir_op_b32csel, src0, src1, src2, NULL);
    342 }
    343 static inline nir_ssa_def *
    344 nir_b8all_fequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    345 {
    346    return nir_build_alu(build, nir_op_b8all_fequal16, src0, src1, NULL, NULL);
    347 }
    348 static inline nir_ssa_def *
    349 nir_b8all_fequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    350 {
    351    return nir_build_alu(build, nir_op_b8all_fequal2, src0, src1, NULL, NULL);
    352 }
    353 static inline nir_ssa_def *
    354 nir_b8all_fequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    355 {
    356    return nir_build_alu(build, nir_op_b8all_fequal3, src0, src1, NULL, NULL);
    357 }
    358 static inline nir_ssa_def *
    359 nir_b8all_fequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    360 {
    361    return nir_build_alu(build, nir_op_b8all_fequal4, src0, src1, NULL, NULL);
    362 }
    363 static inline nir_ssa_def *
    364 nir_b8all_fequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    365 {
    366    return nir_build_alu(build, nir_op_b8all_fequal5, src0, src1, NULL, NULL);
    367 }
    368 static inline nir_ssa_def *
    369 nir_b8all_fequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    370 {
    371    return nir_build_alu(build, nir_op_b8all_fequal8, src0, src1, NULL, NULL);
    372 }
    373 static inline nir_ssa_def *
    374 nir_b8all_iequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    375 {
    376    return nir_build_alu(build, nir_op_b8all_iequal16, src0, src1, NULL, NULL);
    377 }
    378 static inline nir_ssa_def *
    379 nir_b8all_iequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    380 {
    381    return nir_build_alu(build, nir_op_b8all_iequal2, src0, src1, NULL, NULL);
    382 }
    383 static inline nir_ssa_def *
    384 nir_b8all_iequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    385 {
    386    return nir_build_alu(build, nir_op_b8all_iequal3, src0, src1, NULL, NULL);
    387 }
    388 static inline nir_ssa_def *
    389 nir_b8all_iequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    390 {
    391    return nir_build_alu(build, nir_op_b8all_iequal4, src0, src1, NULL, NULL);
    392 }
    393 static inline nir_ssa_def *
    394 nir_b8all_iequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    395 {
    396    return nir_build_alu(build, nir_op_b8all_iequal5, src0, src1, NULL, NULL);
    397 }
    398 static inline nir_ssa_def *
    399 nir_b8all_iequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    400 {
    401    return nir_build_alu(build, nir_op_b8all_iequal8, src0, src1, NULL, NULL);
    402 }
    403 static inline nir_ssa_def *
    404 nir_b8any_fnequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    405 {
    406    return nir_build_alu(build, nir_op_b8any_fnequal16, src0, src1, NULL, NULL);
    407 }
    408 static inline nir_ssa_def *
    409 nir_b8any_fnequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    410 {
    411    return nir_build_alu(build, nir_op_b8any_fnequal2, src0, src1, NULL, NULL);
    412 }
    413 static inline nir_ssa_def *
    414 nir_b8any_fnequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    415 {
    416    return nir_build_alu(build, nir_op_b8any_fnequal3, src0, src1, NULL, NULL);
    417 }
    418 static inline nir_ssa_def *
    419 nir_b8any_fnequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    420 {
    421    return nir_build_alu(build, nir_op_b8any_fnequal4, src0, src1, NULL, NULL);
    422 }
    423 static inline nir_ssa_def *
    424 nir_b8any_fnequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    425 {
    426    return nir_build_alu(build, nir_op_b8any_fnequal5, src0, src1, NULL, NULL);
    427 }
    428 static inline nir_ssa_def *
    429 nir_b8any_fnequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    430 {
    431    return nir_build_alu(build, nir_op_b8any_fnequal8, src0, src1, NULL, NULL);
    432 }
    433 static inline nir_ssa_def *
    434 nir_b8any_inequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    435 {
    436    return nir_build_alu(build, nir_op_b8any_inequal16, src0, src1, NULL, NULL);
    437 }
    438 static inline nir_ssa_def *
    439 nir_b8any_inequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    440 {
    441    return nir_build_alu(build, nir_op_b8any_inequal2, src0, src1, NULL, NULL);
    442 }
    443 static inline nir_ssa_def *
    444 nir_b8any_inequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    445 {
    446    return nir_build_alu(build, nir_op_b8any_inequal3, src0, src1, NULL, NULL);
    447 }
    448 static inline nir_ssa_def *
    449 nir_b8any_inequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    450 {
    451    return nir_build_alu(build, nir_op_b8any_inequal4, src0, src1, NULL, NULL);
    452 }
    453 static inline nir_ssa_def *
    454 nir_b8any_inequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    455 {
    456    return nir_build_alu(build, nir_op_b8any_inequal5, src0, src1, NULL, NULL);
    457 }
    458 static inline nir_ssa_def *
    459 nir_b8any_inequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    460 {
    461    return nir_build_alu(build, nir_op_b8any_inequal8, src0, src1, NULL, NULL);
    462 }
    463 static inline nir_ssa_def *
    464 nir_b8csel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    465 {
    466    return nir_build_alu(build, nir_op_b8csel, src0, src1, src2, NULL);
    467 }
    468 static inline nir_ssa_def *
    469 nir_ball_fequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    470 {
    471    return nir_build_alu(build, nir_op_ball_fequal16, src0, src1, NULL, NULL);
    472 }
    473 static inline nir_ssa_def *
    474 nir_ball_fequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    475 {
    476    return nir_build_alu(build, nir_op_ball_fequal2, src0, src1, NULL, NULL);
    477 }
    478 static inline nir_ssa_def *
    479 nir_ball_fequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    480 {
    481    return nir_build_alu(build, nir_op_ball_fequal3, src0, src1, NULL, NULL);
    482 }
    483 static inline nir_ssa_def *
    484 nir_ball_fequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    485 {
    486    return nir_build_alu(build, nir_op_ball_fequal4, src0, src1, NULL, NULL);
    487 }
    488 static inline nir_ssa_def *
    489 nir_ball_fequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    490 {
    491    return nir_build_alu(build, nir_op_ball_fequal5, src0, src1, NULL, NULL);
    492 }
    493 static inline nir_ssa_def *
    494 nir_ball_fequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    495 {
    496    return nir_build_alu(build, nir_op_ball_fequal8, src0, src1, NULL, NULL);
    497 }
    498 static inline nir_ssa_def *
    499 nir_ball_iequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    500 {
    501    return nir_build_alu(build, nir_op_ball_iequal16, src0, src1, NULL, NULL);
    502 }
    503 static inline nir_ssa_def *
    504 nir_ball_iequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    505 {
    506    return nir_build_alu(build, nir_op_ball_iequal2, src0, src1, NULL, NULL);
    507 }
    508 static inline nir_ssa_def *
    509 nir_ball_iequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    510 {
    511    return nir_build_alu(build, nir_op_ball_iequal3, src0, src1, NULL, NULL);
    512 }
    513 static inline nir_ssa_def *
    514 nir_ball_iequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    515 {
    516    return nir_build_alu(build, nir_op_ball_iequal4, src0, src1, NULL, NULL);
    517 }
    518 static inline nir_ssa_def *
    519 nir_ball_iequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    520 {
    521    return nir_build_alu(build, nir_op_ball_iequal5, src0, src1, NULL, NULL);
    522 }
    523 static inline nir_ssa_def *
    524 nir_ball_iequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    525 {
    526    return nir_build_alu(build, nir_op_ball_iequal8, src0, src1, NULL, NULL);
    527 }
    528 static inline nir_ssa_def *
    529 nir_bany_fnequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    530 {
    531    return nir_build_alu(build, nir_op_bany_fnequal16, src0, src1, NULL, NULL);
    532 }
    533 static inline nir_ssa_def *
    534 nir_bany_fnequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    535 {
    536    return nir_build_alu(build, nir_op_bany_fnequal2, src0, src1, NULL, NULL);
    537 }
    538 static inline nir_ssa_def *
    539 nir_bany_fnequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    540 {
    541    return nir_build_alu(build, nir_op_bany_fnequal3, src0, src1, NULL, NULL);
    542 }
    543 static inline nir_ssa_def *
    544 nir_bany_fnequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    545 {
    546    return nir_build_alu(build, nir_op_bany_fnequal4, src0, src1, NULL, NULL);
    547 }
    548 static inline nir_ssa_def *
    549 nir_bany_fnequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    550 {
    551    return nir_build_alu(build, nir_op_bany_fnequal5, src0, src1, NULL, NULL);
    552 }
    553 static inline nir_ssa_def *
    554 nir_bany_fnequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    555 {
    556    return nir_build_alu(build, nir_op_bany_fnequal8, src0, src1, NULL, NULL);
    557 }
    558 static inline nir_ssa_def *
    559 nir_bany_inequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    560 {
    561    return nir_build_alu(build, nir_op_bany_inequal16, src0, src1, NULL, NULL);
    562 }
    563 static inline nir_ssa_def *
    564 nir_bany_inequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    565 {
    566    return nir_build_alu(build, nir_op_bany_inequal2, src0, src1, NULL, NULL);
    567 }
    568 static inline nir_ssa_def *
    569 nir_bany_inequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    570 {
    571    return nir_build_alu(build, nir_op_bany_inequal3, src0, src1, NULL, NULL);
    572 }
    573 static inline nir_ssa_def *
    574 nir_bany_inequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    575 {
    576    return nir_build_alu(build, nir_op_bany_inequal4, src0, src1, NULL, NULL);
    577 }
    578 static inline nir_ssa_def *
    579 nir_bany_inequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    580 {
    581    return nir_build_alu(build, nir_op_bany_inequal5, src0, src1, NULL, NULL);
    582 }
    583 static inline nir_ssa_def *
    584 nir_bany_inequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    585 {
    586    return nir_build_alu(build, nir_op_bany_inequal8, src0, src1, NULL, NULL);
    587 }
    588 static inline nir_ssa_def *
    589 nir_bcsel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    590 {
    591    return nir_build_alu(build, nir_op_bcsel, src0, src1, src2, NULL);
    592 }
    593 static inline nir_ssa_def *
    594 nir_bfi(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    595 {
    596    return nir_build_alu(build, nir_op_bfi, src0, src1, src2, NULL);
    597 }
    598 static inline nir_ssa_def *
    599 nir_bfm(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    600 {
    601    return nir_build_alu(build, nir_op_bfm, src0, src1, NULL, NULL);
    602 }
    603 static inline nir_ssa_def *
    604 nir_bit_count(nir_builder *build, nir_ssa_def *src0)
    605 {
    606    return nir_build_alu(build, nir_op_bit_count, src0, NULL, NULL, NULL);
    607 }
    608 static inline nir_ssa_def *
    609 nir_bitfield_insert(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
    610 {
    611    return nir_build_alu(build, nir_op_bitfield_insert, src0, src1, src2, src3);
    612 }
    613 static inline nir_ssa_def *
    614 nir_bitfield_reverse(nir_builder *build, nir_ssa_def *src0)
    615 {
    616    return nir_build_alu(build, nir_op_bitfield_reverse, src0, NULL, NULL, NULL);
    617 }
    618 static inline nir_ssa_def *
    619 nir_bitfield_select(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    620 {
    621    return nir_build_alu(build, nir_op_bitfield_select, src0, src1, src2, NULL);
    622 }
    623 static inline nir_ssa_def *
    624 nir_cube_face_coord_amd(nir_builder *build, nir_ssa_def *src0)
    625 {
    626    return nir_build_alu(build, nir_op_cube_face_coord_amd, src0, NULL, NULL, NULL);
    627 }
    628 static inline nir_ssa_def *
    629 nir_cube_face_index_amd(nir_builder *build, nir_ssa_def *src0)
    630 {
    631    return nir_build_alu(build, nir_op_cube_face_index_amd, src0, NULL, NULL, NULL);
    632 }
    633 static inline nir_ssa_def *
    634 nir_cube_r600(nir_builder *build, nir_ssa_def *src0)
    635 {
    636    return nir_build_alu(build, nir_op_cube_r600, src0, NULL, NULL, NULL);
    637 }
    638 static inline nir_ssa_def *
    639 nir_extract_i16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    640 {
    641    return nir_build_alu(build, nir_op_extract_i16, src0, src1, NULL, NULL);
    642 }
    643 static inline nir_ssa_def *
    644 nir_extract_i8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    645 {
    646    return nir_build_alu(build, nir_op_extract_i8, src0, src1, NULL, NULL);
    647 }
    648 static inline nir_ssa_def *
    649 nir_extract_u16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    650 {
    651    return nir_build_alu(build, nir_op_extract_u16, src0, src1, NULL, NULL);
    652 }
    653 static inline nir_ssa_def *
    654 nir_extract_u8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    655 {
    656    return nir_build_alu(build, nir_op_extract_u8, src0, src1, NULL, NULL);
    657 }
    658 static inline nir_ssa_def *
    659 nir_f2b1(nir_builder *build, nir_ssa_def *src0)
    660 {
    661    return nir_build_alu(build, nir_op_f2b1, src0, NULL, NULL, NULL);
    662 }
    663 static inline nir_ssa_def *
    664 nir_f2b16(nir_builder *build, nir_ssa_def *src0)
    665 {
    666    return nir_build_alu(build, nir_op_f2b16, src0, NULL, NULL, NULL);
    667 }
    668 static inline nir_ssa_def *
    669 nir_f2b32(nir_builder *build, nir_ssa_def *src0)
    670 {
    671    return nir_build_alu(build, nir_op_f2b32, src0, NULL, NULL, NULL);
    672 }
    673 static inline nir_ssa_def *
    674 nir_f2b8(nir_builder *build, nir_ssa_def *src0)
    675 {
    676    return nir_build_alu(build, nir_op_f2b8, src0, NULL, NULL, NULL);
    677 }
    678 static inline nir_ssa_def *
    679 nir_f2f16(nir_builder *build, nir_ssa_def *src0)
    680 {
    681    return nir_build_alu(build, nir_op_f2f16, src0, NULL, NULL, NULL);
    682 }
    683 static inline nir_ssa_def *
    684 nir_f2f16_rtne(nir_builder *build, nir_ssa_def *src0)
    685 {
    686    return nir_build_alu(build, nir_op_f2f16_rtne, src0, NULL, NULL, NULL);
    687 }
    688 static inline nir_ssa_def *
    689 nir_f2f16_rtz(nir_builder *build, nir_ssa_def *src0)
    690 {
    691    return nir_build_alu(build, nir_op_f2f16_rtz, src0, NULL, NULL, NULL);
    692 }
    693 static inline nir_ssa_def *
    694 nir_f2f32(nir_builder *build, nir_ssa_def *src0)
    695 {
    696    return nir_build_alu(build, nir_op_f2f32, src0, NULL, NULL, NULL);
    697 }
    698 static inline nir_ssa_def *
    699 nir_f2f64(nir_builder *build, nir_ssa_def *src0)
    700 {
    701    return nir_build_alu(build, nir_op_f2f64, src0, NULL, NULL, NULL);
    702 }
    703 static inline nir_ssa_def *
    704 nir_f2fmp(nir_builder *build, nir_ssa_def *src0)
    705 {
    706    return nir_build_alu(build, nir_op_f2fmp, src0, NULL, NULL, NULL);
    707 }
    708 static inline nir_ssa_def *
    709 nir_f2i1(nir_builder *build, nir_ssa_def *src0)
    710 {
    711    return nir_build_alu(build, nir_op_f2i1, src0, NULL, NULL, NULL);
    712 }
    713 static inline nir_ssa_def *
    714 nir_f2i16(nir_builder *build, nir_ssa_def *src0)
    715 {
    716    return nir_build_alu(build, nir_op_f2i16, src0, NULL, NULL, NULL);
    717 }
    718 static inline nir_ssa_def *
    719 nir_f2i32(nir_builder *build, nir_ssa_def *src0)
    720 {
    721    return nir_build_alu(build, nir_op_f2i32, src0, NULL, NULL, NULL);
    722 }
    723 static inline nir_ssa_def *
    724 nir_f2i64(nir_builder *build, nir_ssa_def *src0)
    725 {
    726    return nir_build_alu(build, nir_op_f2i64, src0, NULL, NULL, NULL);
    727 }
    728 static inline nir_ssa_def *
    729 nir_f2i8(nir_builder *build, nir_ssa_def *src0)
    730 {
    731    return nir_build_alu(build, nir_op_f2i8, src0, NULL, NULL, NULL);
    732 }
    733 static inline nir_ssa_def *
    734 nir_f2imp(nir_builder *build, nir_ssa_def *src0)
    735 {
    736    return nir_build_alu(build, nir_op_f2imp, src0, NULL, NULL, NULL);
    737 }
    738 static inline nir_ssa_def *
    739 nir_f2u1(nir_builder *build, nir_ssa_def *src0)
    740 {
    741    return nir_build_alu(build, nir_op_f2u1, src0, NULL, NULL, NULL);
    742 }
    743 static inline nir_ssa_def *
    744 nir_f2u16(nir_builder *build, nir_ssa_def *src0)
    745 {
    746    return nir_build_alu(build, nir_op_f2u16, src0, NULL, NULL, NULL);
    747 }
    748 static inline nir_ssa_def *
    749 nir_f2u32(nir_builder *build, nir_ssa_def *src0)
    750 {
    751    return nir_build_alu(build, nir_op_f2u32, src0, NULL, NULL, NULL);
    752 }
    753 static inline nir_ssa_def *
    754 nir_f2u64(nir_builder *build, nir_ssa_def *src0)
    755 {
    756    return nir_build_alu(build, nir_op_f2u64, src0, NULL, NULL, NULL);
    757 }
    758 static inline nir_ssa_def *
    759 nir_f2u8(nir_builder *build, nir_ssa_def *src0)
    760 {
    761    return nir_build_alu(build, nir_op_f2u8, src0, NULL, NULL, NULL);
    762 }
    763 static inline nir_ssa_def *
    764 nir_f2ump(nir_builder *build, nir_ssa_def *src0)
    765 {
    766    return nir_build_alu(build, nir_op_f2ump, src0, NULL, NULL, NULL);
    767 }
    768 static inline nir_ssa_def *
    769 nir_fabs(nir_builder *build, nir_ssa_def *src0)
    770 {
    771    return nir_build_alu(build, nir_op_fabs, src0, NULL, NULL, NULL);
    772 }
    773 static inline nir_ssa_def *
    774 nir_fadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    775 {
    776    return nir_build_alu(build, nir_op_fadd, src0, src1, NULL, NULL);
    777 }
    778 static inline nir_ssa_def *
    779 nir_fall_equal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    780 {
    781    return nir_build_alu(build, nir_op_fall_equal16, src0, src1, NULL, NULL);
    782 }
    783 static inline nir_ssa_def *
    784 nir_fall_equal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    785 {
    786    return nir_build_alu(build, nir_op_fall_equal2, src0, src1, NULL, NULL);
    787 }
    788 static inline nir_ssa_def *
    789 nir_fall_equal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    790 {
    791    return nir_build_alu(build, nir_op_fall_equal3, src0, src1, NULL, NULL);
    792 }
    793 static inline nir_ssa_def *
    794 nir_fall_equal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    795 {
    796    return nir_build_alu(build, nir_op_fall_equal4, src0, src1, NULL, NULL);
    797 }
    798 static inline nir_ssa_def *
    799 nir_fall_equal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    800 {
    801    return nir_build_alu(build, nir_op_fall_equal5, src0, src1, NULL, NULL);
    802 }
    803 static inline nir_ssa_def *
    804 nir_fall_equal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    805 {
    806    return nir_build_alu(build, nir_op_fall_equal8, src0, src1, NULL, NULL);
    807 }
    808 static inline nir_ssa_def *
    809 nir_fany_nequal16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    810 {
    811    return nir_build_alu(build, nir_op_fany_nequal16, src0, src1, NULL, NULL);
    812 }
    813 static inline nir_ssa_def *
    814 nir_fany_nequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    815 {
    816    return nir_build_alu(build, nir_op_fany_nequal2, src0, src1, NULL, NULL);
    817 }
    818 static inline nir_ssa_def *
    819 nir_fany_nequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    820 {
    821    return nir_build_alu(build, nir_op_fany_nequal3, src0, src1, NULL, NULL);
    822 }
    823 static inline nir_ssa_def *
    824 nir_fany_nequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    825 {
    826    return nir_build_alu(build, nir_op_fany_nequal4, src0, src1, NULL, NULL);
    827 }
    828 static inline nir_ssa_def *
    829 nir_fany_nequal5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    830 {
    831    return nir_build_alu(build, nir_op_fany_nequal5, src0, src1, NULL, NULL);
    832 }
    833 static inline nir_ssa_def *
    834 nir_fany_nequal8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    835 {
    836    return nir_build_alu(build, nir_op_fany_nequal8, src0, src1, NULL, NULL);
    837 }
    838 static inline nir_ssa_def *
    839 nir_fceil(nir_builder *build, nir_ssa_def *src0)
    840 {
    841    return nir_build_alu(build, nir_op_fceil, src0, NULL, NULL, NULL);
    842 }
    843 static inline nir_ssa_def *
    844 nir_fclamp_pos_mali(nir_builder *build, nir_ssa_def *src0)
    845 {
    846    return nir_build_alu(build, nir_op_fclamp_pos_mali, src0, NULL, NULL, NULL);
    847 }
    848 static inline nir_ssa_def *
    849 nir_fcos(nir_builder *build, nir_ssa_def *src0)
    850 {
    851    return nir_build_alu(build, nir_op_fcos, src0, NULL, NULL, NULL);
    852 }
    853 static inline nir_ssa_def *
    854 nir_fcos_r600(nir_builder *build, nir_ssa_def *src0)
    855 {
    856    return nir_build_alu(build, nir_op_fcos_r600, src0, NULL, NULL, NULL);
    857 }
    858 static inline nir_ssa_def *
    859 nir_fcsel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    860 {
    861    return nir_build_alu(build, nir_op_fcsel, src0, src1, src2, NULL);
    862 }
    863 static inline nir_ssa_def *
    864 nir_fcsel_ge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    865 {
    866    return nir_build_alu(build, nir_op_fcsel_ge, src0, src1, src2, NULL);
    867 }
    868 static inline nir_ssa_def *
    869 nir_fcsel_gt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
    870 {
    871    return nir_build_alu(build, nir_op_fcsel_gt, src0, src1, src2, NULL);
    872 }
    873 static inline nir_ssa_def *
    874 nir_fddx(nir_builder *build, nir_ssa_def *src0)
    875 {
    876    return nir_build_alu(build, nir_op_fddx, src0, NULL, NULL, NULL);
    877 }
    878 static inline nir_ssa_def *
    879 nir_fddx_coarse(nir_builder *build, nir_ssa_def *src0)
    880 {
    881    return nir_build_alu(build, nir_op_fddx_coarse, src0, NULL, NULL, NULL);
    882 }
    883 static inline nir_ssa_def *
    884 nir_fddx_fine(nir_builder *build, nir_ssa_def *src0)
    885 {
    886    return nir_build_alu(build, nir_op_fddx_fine, src0, NULL, NULL, NULL);
    887 }
    888 static inline nir_ssa_def *
    889 nir_fddx_must_abs_mali(nir_builder *build, nir_ssa_def *src0)
    890 {
    891    return nir_build_alu(build, nir_op_fddx_must_abs_mali, src0, NULL, NULL, NULL);
    892 }
    893 static inline nir_ssa_def *
    894 nir_fddy(nir_builder *build, nir_ssa_def *src0)
    895 {
    896    return nir_build_alu(build, nir_op_fddy, src0, NULL, NULL, NULL);
    897 }
    898 static inline nir_ssa_def *
    899 nir_fddy_coarse(nir_builder *build, nir_ssa_def *src0)
    900 {
    901    return nir_build_alu(build, nir_op_fddy_coarse, src0, NULL, NULL, NULL);
    902 }
    903 static inline nir_ssa_def *
    904 nir_fddy_fine(nir_builder *build, nir_ssa_def *src0)
    905 {
    906    return nir_build_alu(build, nir_op_fddy_fine, src0, NULL, NULL, NULL);
    907 }
    908 static inline nir_ssa_def *
    909 nir_fddy_must_abs_mali(nir_builder *build, nir_ssa_def *src0)
    910 {
    911    return nir_build_alu(build, nir_op_fddy_must_abs_mali, src0, NULL, NULL, NULL);
    912 }
    913 static inline nir_ssa_def *
    914 nir_fdiv(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    915 {
    916    return nir_build_alu(build, nir_op_fdiv, src0, src1, NULL, NULL);
    917 }
    918 static inline nir_ssa_def *
    919 nir_fdot16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    920 {
    921    return nir_build_alu(build, nir_op_fdot16, src0, src1, NULL, NULL);
    922 }
    923 static inline nir_ssa_def *
    924 nir_fdot16_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    925 {
    926    return nir_build_alu(build, nir_op_fdot16_replicated, src0, src1, NULL, NULL);
    927 }
    928 static inline nir_ssa_def *
    929 nir_fdot2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    930 {
    931    return nir_build_alu(build, nir_op_fdot2, src0, src1, NULL, NULL);
    932 }
    933 static inline nir_ssa_def *
    934 nir_fdot2_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    935 {
    936    return nir_build_alu(build, nir_op_fdot2_replicated, src0, src1, NULL, NULL);
    937 }
    938 static inline nir_ssa_def *
    939 nir_fdot3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    940 {
    941    return nir_build_alu(build, nir_op_fdot3, src0, src1, NULL, NULL);
    942 }
    943 static inline nir_ssa_def *
    944 nir_fdot3_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    945 {
    946    return nir_build_alu(build, nir_op_fdot3_replicated, src0, src1, NULL, NULL);
    947 }
    948 static inline nir_ssa_def *
    949 nir_fdot4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    950 {
    951    return nir_build_alu(build, nir_op_fdot4, src0, src1, NULL, NULL);
    952 }
    953 static inline nir_ssa_def *
    954 nir_fdot4_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    955 {
    956    return nir_build_alu(build, nir_op_fdot4_replicated, src0, src1, NULL, NULL);
    957 }
    958 static inline nir_ssa_def *
    959 nir_fdot5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    960 {
    961    return nir_build_alu(build, nir_op_fdot5, src0, src1, NULL, NULL);
    962 }
    963 static inline nir_ssa_def *
    964 nir_fdot5_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    965 {
    966    return nir_build_alu(build, nir_op_fdot5_replicated, src0, src1, NULL, NULL);
    967 }
    968 static inline nir_ssa_def *
    969 nir_fdot8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    970 {
    971    return nir_build_alu(build, nir_op_fdot8, src0, src1, NULL, NULL);
    972 }
    973 static inline nir_ssa_def *
    974 nir_fdot8_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    975 {
    976    return nir_build_alu(build, nir_op_fdot8_replicated, src0, src1, NULL, NULL);
    977 }
    978 static inline nir_ssa_def *
    979 nir_fdph(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    980 {
    981    return nir_build_alu(build, nir_op_fdph, src0, src1, NULL, NULL);
    982 }
    983 static inline nir_ssa_def *
    984 nir_fdph_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    985 {
    986    return nir_build_alu(build, nir_op_fdph_replicated, src0, src1, NULL, NULL);
    987 }
    988 static inline nir_ssa_def *
    989 nir_feq(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    990 {
    991    return nir_build_alu(build, nir_op_feq, src0, src1, NULL, NULL);
    992 }
    993 static inline nir_ssa_def *
    994 nir_feq16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
    995 {
    996    return nir_build_alu(build, nir_op_feq16, src0, src1, NULL, NULL);
    997 }
    998 static inline nir_ssa_def *
    999 nir_feq32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1000 {
   1001    return nir_build_alu(build, nir_op_feq32, src0, src1, NULL, NULL);
   1002 }
   1003 static inline nir_ssa_def *
   1004 nir_feq8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1005 {
   1006    return nir_build_alu(build, nir_op_feq8, src0, src1, NULL, NULL);
   1007 }
   1008 static inline nir_ssa_def *
   1009 nir_fexp2(nir_builder *build, nir_ssa_def *src0)
   1010 {
   1011    return nir_build_alu(build, nir_op_fexp2, src0, NULL, NULL, NULL);
   1012 }
   1013 static inline nir_ssa_def *
   1014 nir_ffloor(nir_builder *build, nir_ssa_def *src0)
   1015 {
   1016    return nir_build_alu(build, nir_op_ffloor, src0, NULL, NULL, NULL);
   1017 }
   1018 static inline nir_ssa_def *
   1019 nir_ffma(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1020 {
   1021    return nir_build_alu(build, nir_op_ffma, src0, src1, src2, NULL);
   1022 }
   1023 static inline nir_ssa_def *
   1024 nir_ffract(nir_builder *build, nir_ssa_def *src0)
   1025 {
   1026    return nir_build_alu(build, nir_op_ffract, src0, NULL, NULL, NULL);
   1027 }
   1028 static inline nir_ssa_def *
   1029 nir_fge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1030 {
   1031    return nir_build_alu(build, nir_op_fge, src0, src1, NULL, NULL);
   1032 }
   1033 static inline nir_ssa_def *
   1034 nir_fge16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1035 {
   1036    return nir_build_alu(build, nir_op_fge16, src0, src1, NULL, NULL);
   1037 }
   1038 static inline nir_ssa_def *
   1039 nir_fge32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1040 {
   1041    return nir_build_alu(build, nir_op_fge32, src0, src1, NULL, NULL);
   1042 }
   1043 static inline nir_ssa_def *
   1044 nir_fge8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1045 {
   1046    return nir_build_alu(build, nir_op_fge8, src0, src1, NULL, NULL);
   1047 }
   1048 static inline nir_ssa_def *
   1049 nir_find_lsb(nir_builder *build, nir_ssa_def *src0)
   1050 {
   1051    return nir_build_alu(build, nir_op_find_lsb, src0, NULL, NULL, NULL);
   1052 }
   1053 static inline nir_ssa_def *
   1054 nir_fisfinite(nir_builder *build, nir_ssa_def *src0)
   1055 {
   1056    return nir_build_alu(build, nir_op_fisfinite, src0, NULL, NULL, NULL);
   1057 }
   1058 static inline nir_ssa_def *
   1059 nir_fisfinite32(nir_builder *build, nir_ssa_def *src0)
   1060 {
   1061    return nir_build_alu(build, nir_op_fisfinite32, src0, NULL, NULL, NULL);
   1062 }
   1063 static inline nir_ssa_def *
   1064 nir_fisnormal(nir_builder *build, nir_ssa_def *src0)
   1065 {
   1066    return nir_build_alu(build, nir_op_fisnormal, src0, NULL, NULL, NULL);
   1067 }
   1068 static inline nir_ssa_def *
   1069 nir_flog2(nir_builder *build, nir_ssa_def *src0)
   1070 {
   1071    return nir_build_alu(build, nir_op_flog2, src0, NULL, NULL, NULL);
   1072 }
   1073 static inline nir_ssa_def *
   1074 nir_flrp(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1075 {
   1076    return nir_build_alu(build, nir_op_flrp, src0, src1, src2, NULL);
   1077 }
   1078 static inline nir_ssa_def *
   1079 nir_flt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1080 {
   1081    return nir_build_alu(build, nir_op_flt, src0, src1, NULL, NULL);
   1082 }
   1083 static inline nir_ssa_def *
   1084 nir_flt16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1085 {
   1086    return nir_build_alu(build, nir_op_flt16, src0, src1, NULL, NULL);
   1087 }
   1088 static inline nir_ssa_def *
   1089 nir_flt32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1090 {
   1091    return nir_build_alu(build, nir_op_flt32, src0, src1, NULL, NULL);
   1092 }
   1093 static inline nir_ssa_def *
   1094 nir_flt8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1095 {
   1096    return nir_build_alu(build, nir_op_flt8, src0, src1, NULL, NULL);
   1097 }
   1098 static inline nir_ssa_def *
   1099 nir_fmax(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1100 {
   1101    return nir_build_alu(build, nir_op_fmax, src0, src1, NULL, NULL);
   1102 }
   1103 static inline nir_ssa_def *
   1104 nir_fmin(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1105 {
   1106    return nir_build_alu(build, nir_op_fmin, src0, src1, NULL, NULL);
   1107 }
   1108 static inline nir_ssa_def *
   1109 nir_fmod(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1110 {
   1111    return nir_build_alu(build, nir_op_fmod, src0, src1, NULL, NULL);
   1112 }
   1113 static inline nir_ssa_def *
   1114 nir_fmul(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1115 {
   1116    return nir_build_alu(build, nir_op_fmul, src0, src1, NULL, NULL);
   1117 }
   1118 static inline nir_ssa_def *
   1119 nir_fneg(nir_builder *build, nir_ssa_def *src0)
   1120 {
   1121    return nir_build_alu(build, nir_op_fneg, src0, NULL, NULL, NULL);
   1122 }
   1123 static inline nir_ssa_def *
   1124 nir_fneu(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1125 {
   1126    return nir_build_alu(build, nir_op_fneu, src0, src1, NULL, NULL);
   1127 }
   1128 static inline nir_ssa_def *
   1129 nir_fneu16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1130 {
   1131    return nir_build_alu(build, nir_op_fneu16, src0, src1, NULL, NULL);
   1132 }
   1133 static inline nir_ssa_def *
   1134 nir_fneu32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1135 {
   1136    return nir_build_alu(build, nir_op_fneu32, src0, src1, NULL, NULL);
   1137 }
   1138 static inline nir_ssa_def *
   1139 nir_fneu8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1140 {
   1141    return nir_build_alu(build, nir_op_fneu8, src0, src1, NULL, NULL);
   1142 }
   1143 static inline nir_ssa_def *
   1144 nir_fpow(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1145 {
   1146    return nir_build_alu(build, nir_op_fpow, src0, src1, NULL, NULL);
   1147 }
   1148 static inline nir_ssa_def *
   1149 nir_fquantize2f16(nir_builder *build, nir_ssa_def *src0)
   1150 {
   1151    return nir_build_alu(build, nir_op_fquantize2f16, src0, NULL, NULL, NULL);
   1152 }
   1153 static inline nir_ssa_def *
   1154 nir_frcp(nir_builder *build, nir_ssa_def *src0)
   1155 {
   1156    return nir_build_alu(build, nir_op_frcp, src0, NULL, NULL, NULL);
   1157 }
   1158 static inline nir_ssa_def *
   1159 nir_frem(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1160 {
   1161    return nir_build_alu(build, nir_op_frem, src0, src1, NULL, NULL);
   1162 }
   1163 static inline nir_ssa_def *
   1164 nir_frexp_exp(nir_builder *build, nir_ssa_def *src0)
   1165 {
   1166    return nir_build_alu(build, nir_op_frexp_exp, src0, NULL, NULL, NULL);
   1167 }
   1168 static inline nir_ssa_def *
   1169 nir_frexp_sig(nir_builder *build, nir_ssa_def *src0)
   1170 {
   1171    return nir_build_alu(build, nir_op_frexp_sig, src0, NULL, NULL, NULL);
   1172 }
   1173 static inline nir_ssa_def *
   1174 nir_fround_even(nir_builder *build, nir_ssa_def *src0)
   1175 {
   1176    return nir_build_alu(build, nir_op_fround_even, src0, NULL, NULL, NULL);
   1177 }
   1178 static inline nir_ssa_def *
   1179 nir_frsq(nir_builder *build, nir_ssa_def *src0)
   1180 {
   1181    return nir_build_alu(build, nir_op_frsq, src0, NULL, NULL, NULL);
   1182 }
   1183 static inline nir_ssa_def *
   1184 nir_fsat(nir_builder *build, nir_ssa_def *src0)
   1185 {
   1186    return nir_build_alu(build, nir_op_fsat, src0, NULL, NULL, NULL);
   1187 }
   1188 static inline nir_ssa_def *
   1189 nir_fsat_signed_mali(nir_builder *build, nir_ssa_def *src0)
   1190 {
   1191    return nir_build_alu(build, nir_op_fsat_signed_mali, src0, NULL, NULL, NULL);
   1192 }
   1193 static inline nir_ssa_def *
   1194 nir_fsign(nir_builder *build, nir_ssa_def *src0)
   1195 {
   1196    return nir_build_alu(build, nir_op_fsign, src0, NULL, NULL, NULL);
   1197 }
   1198 static inline nir_ssa_def *
   1199 nir_fsin(nir_builder *build, nir_ssa_def *src0)
   1200 {
   1201    return nir_build_alu(build, nir_op_fsin, src0, NULL, NULL, NULL);
   1202 }
   1203 static inline nir_ssa_def *
   1204 nir_fsin_agx(nir_builder *build, nir_ssa_def *src0)
   1205 {
   1206    return nir_build_alu(build, nir_op_fsin_agx, src0, NULL, NULL, NULL);
   1207 }
   1208 static inline nir_ssa_def *
   1209 nir_fsin_r600(nir_builder *build, nir_ssa_def *src0)
   1210 {
   1211    return nir_build_alu(build, nir_op_fsin_r600, src0, NULL, NULL, NULL);
   1212 }
   1213 static inline nir_ssa_def *
   1214 nir_fsqrt(nir_builder *build, nir_ssa_def *src0)
   1215 {
   1216    return nir_build_alu(build, nir_op_fsqrt, src0, NULL, NULL, NULL);
   1217 }
   1218 static inline nir_ssa_def *
   1219 nir_fsub(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1220 {
   1221    return nir_build_alu(build, nir_op_fsub, src0, src1, NULL, NULL);
   1222 }
   1223 static inline nir_ssa_def *
   1224 nir_fsum2(nir_builder *build, nir_ssa_def *src0)
   1225 {
   1226    return nir_build_alu(build, nir_op_fsum2, src0, NULL, NULL, NULL);
   1227 }
   1228 static inline nir_ssa_def *
   1229 nir_fsum3(nir_builder *build, nir_ssa_def *src0)
   1230 {
   1231    return nir_build_alu(build, nir_op_fsum3, src0, NULL, NULL, NULL);
   1232 }
   1233 static inline nir_ssa_def *
   1234 nir_fsum4(nir_builder *build, nir_ssa_def *src0)
   1235 {
   1236    return nir_build_alu(build, nir_op_fsum4, src0, NULL, NULL, NULL);
   1237 }
   1238 static inline nir_ssa_def *
   1239 nir_ftrunc(nir_builder *build, nir_ssa_def *src0)
   1240 {
   1241    return nir_build_alu(build, nir_op_ftrunc, src0, NULL, NULL, NULL);
   1242 }
   1243 static inline nir_ssa_def *
   1244 nir_i2b1(nir_builder *build, nir_ssa_def *src0)
   1245 {
   1246    return nir_build_alu(build, nir_op_i2b1, src0, NULL, NULL, NULL);
   1247 }
   1248 static inline nir_ssa_def *
   1249 nir_i2b16(nir_builder *build, nir_ssa_def *src0)
   1250 {
   1251    return nir_build_alu(build, nir_op_i2b16, src0, NULL, NULL, NULL);
   1252 }
   1253 static inline nir_ssa_def *
   1254 nir_i2b32(nir_builder *build, nir_ssa_def *src0)
   1255 {
   1256    return nir_build_alu(build, nir_op_i2b32, src0, NULL, NULL, NULL);
   1257 }
   1258 static inline nir_ssa_def *
   1259 nir_i2b8(nir_builder *build, nir_ssa_def *src0)
   1260 {
   1261    return nir_build_alu(build, nir_op_i2b8, src0, NULL, NULL, NULL);
   1262 }
   1263 static inline nir_ssa_def *
   1264 nir_i2f16(nir_builder *build, nir_ssa_def *src0)
   1265 {
   1266    return nir_build_alu(build, nir_op_i2f16, src0, NULL, NULL, NULL);
   1267 }
   1268 static inline nir_ssa_def *
   1269 nir_i2f32(nir_builder *build, nir_ssa_def *src0)
   1270 {
   1271    return nir_build_alu(build, nir_op_i2f32, src0, NULL, NULL, NULL);
   1272 }
   1273 static inline nir_ssa_def *
   1274 nir_i2f64(nir_builder *build, nir_ssa_def *src0)
   1275 {
   1276    return nir_build_alu(build, nir_op_i2f64, src0, NULL, NULL, NULL);
   1277 }
   1278 static inline nir_ssa_def *
   1279 nir_i2fmp(nir_builder *build, nir_ssa_def *src0)
   1280 {
   1281    return nir_build_alu(build, nir_op_i2fmp, src0, NULL, NULL, NULL);
   1282 }
   1283 static inline nir_ssa_def *
   1284 nir_i2i1(nir_builder *build, nir_ssa_def *src0)
   1285 {
   1286    return nir_build_alu(build, nir_op_i2i1, src0, NULL, NULL, NULL);
   1287 }
   1288 static inline nir_ssa_def *
   1289 nir_i2i16(nir_builder *build, nir_ssa_def *src0)
   1290 {
   1291    return nir_build_alu(build, nir_op_i2i16, src0, NULL, NULL, NULL);
   1292 }
   1293 static inline nir_ssa_def *
   1294 nir_i2i32(nir_builder *build, nir_ssa_def *src0)
   1295 {
   1296    return nir_build_alu(build, nir_op_i2i32, src0, NULL, NULL, NULL);
   1297 }
   1298 static inline nir_ssa_def *
   1299 nir_i2i64(nir_builder *build, nir_ssa_def *src0)
   1300 {
   1301    return nir_build_alu(build, nir_op_i2i64, src0, NULL, NULL, NULL);
   1302 }
   1303 static inline nir_ssa_def *
   1304 nir_i2i8(nir_builder *build, nir_ssa_def *src0)
   1305 {
   1306    return nir_build_alu(build, nir_op_i2i8, src0, NULL, NULL, NULL);
   1307 }
   1308 static inline nir_ssa_def *
   1309 nir_i2imp(nir_builder *build, nir_ssa_def *src0)
   1310 {
   1311    return nir_build_alu(build, nir_op_i2imp, src0, NULL, NULL, NULL);
   1312 }
   1313 static inline nir_ssa_def *
   1314 nir_i32csel_ge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1315 {
   1316    return nir_build_alu(build, nir_op_i32csel_ge, src0, src1, src2, NULL);
   1317 }
   1318 static inline nir_ssa_def *
   1319 nir_i32csel_gt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1320 {
   1321    return nir_build_alu(build, nir_op_i32csel_gt, src0, src1, src2, NULL);
   1322 }
   1323 static inline nir_ssa_def *
   1324 nir_iabs(nir_builder *build, nir_ssa_def *src0)
   1325 {
   1326    return nir_build_alu(build, nir_op_iabs, src0, NULL, NULL, NULL);
   1327 }
   1328 static inline nir_ssa_def *
   1329 nir_iadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1330 {
   1331    return nir_build_alu(build, nir_op_iadd, src0, src1, NULL, NULL);
   1332 }
   1333 static inline nir_ssa_def *
   1334 nir_iadd3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1335 {
   1336    return nir_build_alu(build, nir_op_iadd3, src0, src1, src2, NULL);
   1337 }
   1338 static inline nir_ssa_def *
   1339 nir_iadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1340 {
   1341    return nir_build_alu(build, nir_op_iadd_sat, src0, src1, NULL, NULL);
   1342 }
   1343 static inline nir_ssa_def *
   1344 nir_iand(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1345 {
   1346    return nir_build_alu(build, nir_op_iand, src0, src1, NULL, NULL);
   1347 }
   1348 static inline nir_ssa_def *
   1349 nir_ibfe(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1350 {
   1351    return nir_build_alu(build, nir_op_ibfe, src0, src1, src2, NULL);
   1352 }
   1353 static inline nir_ssa_def *
   1354 nir_ibitfield_extract(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1355 {
   1356    return nir_build_alu(build, nir_op_ibitfield_extract, src0, src1, src2, NULL);
   1357 }
   1358 static inline nir_ssa_def *
   1359 nir_idiv(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1360 {
   1361    return nir_build_alu(build, nir_op_idiv, src0, src1, NULL, NULL);
   1362 }
   1363 static inline nir_ssa_def *
   1364 nir_ieq(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1365 {
   1366    return nir_build_alu(build, nir_op_ieq, src0, src1, NULL, NULL);
   1367 }
   1368 static inline nir_ssa_def *
   1369 nir_ieq16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1370 {
   1371    return nir_build_alu(build, nir_op_ieq16, src0, src1, NULL, NULL);
   1372 }
   1373 static inline nir_ssa_def *
   1374 nir_ieq32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1375 {
   1376    return nir_build_alu(build, nir_op_ieq32, src0, src1, NULL, NULL);
   1377 }
   1378 static inline nir_ssa_def *
   1379 nir_ieq8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1380 {
   1381    return nir_build_alu(build, nir_op_ieq8, src0, src1, NULL, NULL);
   1382 }
   1383 static inline nir_ssa_def *
   1384 nir_ifind_msb(nir_builder *build, nir_ssa_def *src0)
   1385 {
   1386    return nir_build_alu(build, nir_op_ifind_msb, src0, NULL, NULL, NULL);
   1387 }
   1388 static inline nir_ssa_def *
   1389 nir_ifind_msb_rev(nir_builder *build, nir_ssa_def *src0)
   1390 {
   1391    return nir_build_alu(build, nir_op_ifind_msb_rev, src0, NULL, NULL, NULL);
   1392 }
   1393 static inline nir_ssa_def *
   1394 nir_ige(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1395 {
   1396    return nir_build_alu(build, nir_op_ige, src0, src1, NULL, NULL);
   1397 }
   1398 static inline nir_ssa_def *
   1399 nir_ige16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1400 {
   1401    return nir_build_alu(build, nir_op_ige16, src0, src1, NULL, NULL);
   1402 }
   1403 static inline nir_ssa_def *
   1404 nir_ige32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1405 {
   1406    return nir_build_alu(build, nir_op_ige32, src0, src1, NULL, NULL);
   1407 }
   1408 static inline nir_ssa_def *
   1409 nir_ige8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1410 {
   1411    return nir_build_alu(build, nir_op_ige8, src0, src1, NULL, NULL);
   1412 }
   1413 static inline nir_ssa_def *
   1414 nir_ihadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1415 {
   1416    return nir_build_alu(build, nir_op_ihadd, src0, src1, NULL, NULL);
   1417 }
   1418 static inline nir_ssa_def *
   1419 nir_ilt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1420 {
   1421    return nir_build_alu(build, nir_op_ilt, src0, src1, NULL, NULL);
   1422 }
   1423 static inline nir_ssa_def *
   1424 nir_ilt16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1425 {
   1426    return nir_build_alu(build, nir_op_ilt16, src0, src1, NULL, NULL);
   1427 }
   1428 static inline nir_ssa_def *
   1429 nir_ilt32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1430 {
   1431    return nir_build_alu(build, nir_op_ilt32, src0, src1, NULL, NULL);
   1432 }
   1433 static inline nir_ssa_def *
   1434 nir_ilt8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1435 {
   1436    return nir_build_alu(build, nir_op_ilt8, src0, src1, NULL, NULL);
   1437 }
   1438 static inline nir_ssa_def *
   1439 nir_imad24_ir3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1440 {
   1441    return nir_build_alu(build, nir_op_imad24_ir3, src0, src1, src2, NULL);
   1442 }
   1443 static inline nir_ssa_def *
   1444 nir_imadsh_mix16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1445 {
   1446    return nir_build_alu(build, nir_op_imadsh_mix16, src0, src1, src2, NULL);
   1447 }
   1448 static inline nir_ssa_def *
   1449 nir_imax(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1450 {
   1451    return nir_build_alu(build, nir_op_imax, src0, src1, NULL, NULL);
   1452 }
   1453 static inline nir_ssa_def *
   1454 nir_imin(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1455 {
   1456    return nir_build_alu(build, nir_op_imin, src0, src1, NULL, NULL);
   1457 }
   1458 static inline nir_ssa_def *
   1459 nir_imod(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1460 {
   1461    return nir_build_alu(build, nir_op_imod, src0, src1, NULL, NULL);
   1462 }
   1463 static inline nir_ssa_def *
   1464 nir_imul(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1465 {
   1466    return nir_build_alu(build, nir_op_imul, src0, src1, NULL, NULL);
   1467 }
   1468 static inline nir_ssa_def *
   1469 nir_imul24(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1470 {
   1471    return nir_build_alu(build, nir_op_imul24, src0, src1, NULL, NULL);
   1472 }
   1473 static inline nir_ssa_def *
   1474 nir_imul24_relaxed(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1475 {
   1476    return nir_build_alu(build, nir_op_imul24_relaxed, src0, src1, NULL, NULL);
   1477 }
   1478 static inline nir_ssa_def *
   1479 nir_imul_2x32_64(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1480 {
   1481    return nir_build_alu(build, nir_op_imul_2x32_64, src0, src1, NULL, NULL);
   1482 }
   1483 static inline nir_ssa_def *
   1484 nir_imul_32x16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1485 {
   1486    return nir_build_alu(build, nir_op_imul_32x16, src0, src1, NULL, NULL);
   1487 }
   1488 static inline nir_ssa_def *
   1489 nir_imul_high(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1490 {
   1491    return nir_build_alu(build, nir_op_imul_high, src0, src1, NULL, NULL);
   1492 }
   1493 static inline nir_ssa_def *
   1494 nir_ine(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1495 {
   1496    return nir_build_alu(build, nir_op_ine, src0, src1, NULL, NULL);
   1497 }
   1498 static inline nir_ssa_def *
   1499 nir_ine16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1500 {
   1501    return nir_build_alu(build, nir_op_ine16, src0, src1, NULL, NULL);
   1502 }
   1503 static inline nir_ssa_def *
   1504 nir_ine32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1505 {
   1506    return nir_build_alu(build, nir_op_ine32, src0, src1, NULL, NULL);
   1507 }
   1508 static inline nir_ssa_def *
   1509 nir_ine8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1510 {
   1511    return nir_build_alu(build, nir_op_ine8, src0, src1, NULL, NULL);
   1512 }
   1513 static inline nir_ssa_def *
   1514 nir_ineg(nir_builder *build, nir_ssa_def *src0)
   1515 {
   1516    return nir_build_alu(build, nir_op_ineg, src0, NULL, NULL, NULL);
   1517 }
   1518 static inline nir_ssa_def *
   1519 nir_inot(nir_builder *build, nir_ssa_def *src0)
   1520 {
   1521    return nir_build_alu(build, nir_op_inot, src0, NULL, NULL, NULL);
   1522 }
   1523 static inline nir_ssa_def *
   1524 nir_insert_u16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1525 {
   1526    return nir_build_alu(build, nir_op_insert_u16, src0, src1, NULL, NULL);
   1527 }
   1528 static inline nir_ssa_def *
   1529 nir_insert_u8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1530 {
   1531    return nir_build_alu(build, nir_op_insert_u8, src0, src1, NULL, NULL);
   1532 }
   1533 static inline nir_ssa_def *
   1534 nir_ior(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1535 {
   1536    return nir_build_alu(build, nir_op_ior, src0, src1, NULL, NULL);
   1537 }
   1538 static inline nir_ssa_def *
   1539 nir_irem(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1540 {
   1541    return nir_build_alu(build, nir_op_irem, src0, src1, NULL, NULL);
   1542 }
   1543 static inline nir_ssa_def *
   1544 nir_irhadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1545 {
   1546    return nir_build_alu(build, nir_op_irhadd, src0, src1, NULL, NULL);
   1547 }
   1548 static inline nir_ssa_def *
   1549 nir_ishl(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1550 {
   1551    return nir_build_alu(build, nir_op_ishl, src0, src1, NULL, NULL);
   1552 }
   1553 static inline nir_ssa_def *
   1554 nir_ishr(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1555 {
   1556    return nir_build_alu(build, nir_op_ishr, src0, src1, NULL, NULL);
   1557 }
   1558 static inline nir_ssa_def *
   1559 nir_isign(nir_builder *build, nir_ssa_def *src0)
   1560 {
   1561    return nir_build_alu(build, nir_op_isign, src0, NULL, NULL, NULL);
   1562 }
   1563 static inline nir_ssa_def *
   1564 nir_isub(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1565 {
   1566    return nir_build_alu(build, nir_op_isub, src0, src1, NULL, NULL);
   1567 }
   1568 static inline nir_ssa_def *
   1569 nir_isub_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1570 {
   1571    return nir_build_alu(build, nir_op_isub_sat, src0, src1, NULL, NULL);
   1572 }
   1573 static inline nir_ssa_def *
   1574 nir_ixor(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1575 {
   1576    return nir_build_alu(build, nir_op_ixor, src0, src1, NULL, NULL);
   1577 }
   1578 static inline nir_ssa_def *
   1579 nir_ldexp(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1580 {
   1581    return nir_build_alu(build, nir_op_ldexp, src0, src1, NULL, NULL);
   1582 }
   1583 static inline nir_ssa_def *
   1584 nir_mov(nir_builder *build, nir_ssa_def *src0)
   1585 {
   1586    return nir_build_alu(build, nir_op_mov, src0, NULL, NULL, NULL);
   1587 }
   1588 static inline nir_ssa_def *
   1589 nir_pack_32_2x16(nir_builder *build, nir_ssa_def *src0)
   1590 {
   1591    return nir_build_alu(build, nir_op_pack_32_2x16, src0, NULL, NULL, NULL);
   1592 }
   1593 static inline nir_ssa_def *
   1594 nir_pack_32_2x16_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1595 {
   1596    return nir_build_alu(build, nir_op_pack_32_2x16_split, src0, src1, NULL, NULL);
   1597 }
   1598 static inline nir_ssa_def *
   1599 nir_pack_32_4x8(nir_builder *build, nir_ssa_def *src0)
   1600 {
   1601    return nir_build_alu(build, nir_op_pack_32_4x8, src0, NULL, NULL, NULL);
   1602 }
   1603 static inline nir_ssa_def *
   1604 nir_pack_32_4x8_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
   1605 {
   1606    return nir_build_alu(build, nir_op_pack_32_4x8_split, src0, src1, src2, src3);
   1607 }
   1608 static inline nir_ssa_def *
   1609 nir_pack_64_2x32(nir_builder *build, nir_ssa_def *src0)
   1610 {
   1611    return nir_build_alu(build, nir_op_pack_64_2x32, src0, NULL, NULL, NULL);
   1612 }
   1613 static inline nir_ssa_def *
   1614 nir_pack_64_2x32_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1615 {
   1616    return nir_build_alu(build, nir_op_pack_64_2x32_split, src0, src1, NULL, NULL);
   1617 }
   1618 static inline nir_ssa_def *
   1619 nir_pack_64_4x16(nir_builder *build, nir_ssa_def *src0)
   1620 {
   1621    return nir_build_alu(build, nir_op_pack_64_4x16, src0, NULL, NULL, NULL);
   1622 }
   1623 static inline nir_ssa_def *
   1624 nir_pack_double_2x32_dxil(nir_builder *build, nir_ssa_def *src0)
   1625 {
   1626    return nir_build_alu(build, nir_op_pack_double_2x32_dxil, src0, NULL, NULL, NULL);
   1627 }
   1628 static inline nir_ssa_def *
   1629 nir_pack_half_2x16(nir_builder *build, nir_ssa_def *src0)
   1630 {
   1631    return nir_build_alu(build, nir_op_pack_half_2x16, src0, NULL, NULL, NULL);
   1632 }
   1633 static inline nir_ssa_def *
   1634 nir_pack_half_2x16_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1635 {
   1636    return nir_build_alu(build, nir_op_pack_half_2x16_split, src0, src1, NULL, NULL);
   1637 }
   1638 static inline nir_ssa_def *
   1639 nir_pack_snorm_2x16(nir_builder *build, nir_ssa_def *src0)
   1640 {
   1641    return nir_build_alu(build, nir_op_pack_snorm_2x16, src0, NULL, NULL, NULL);
   1642 }
   1643 static inline nir_ssa_def *
   1644 nir_pack_snorm_4x8(nir_builder *build, nir_ssa_def *src0)
   1645 {
   1646    return nir_build_alu(build, nir_op_pack_snorm_4x8, src0, NULL, NULL, NULL);
   1647 }
   1648 static inline nir_ssa_def *
   1649 nir_pack_unorm_2x16(nir_builder *build, nir_ssa_def *src0)
   1650 {
   1651    return nir_build_alu(build, nir_op_pack_unorm_2x16, src0, NULL, NULL, NULL);
   1652 }
   1653 static inline nir_ssa_def *
   1654 nir_pack_unorm_4x8(nir_builder *build, nir_ssa_def *src0)
   1655 {
   1656    return nir_build_alu(build, nir_op_pack_unorm_4x8, src0, NULL, NULL, NULL);
   1657 }
   1658 static inline nir_ssa_def *
   1659 nir_pack_uvec2_to_uint(nir_builder *build, nir_ssa_def *src0)
   1660 {
   1661    return nir_build_alu(build, nir_op_pack_uvec2_to_uint, src0, NULL, NULL, NULL);
   1662 }
   1663 static inline nir_ssa_def *
   1664 nir_pack_uvec4_to_uint(nir_builder *build, nir_ssa_def *src0)
   1665 {
   1666    return nir_build_alu(build, nir_op_pack_uvec4_to_uint, src0, NULL, NULL, NULL);
   1667 }
   1668 static inline nir_ssa_def *
   1669 nir_sad_u8x4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1670 {
   1671    return nir_build_alu(build, nir_op_sad_u8x4, src0, src1, src2, NULL);
   1672 }
   1673 static inline nir_ssa_def *
   1674 nir_sdot_2x16_iadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1675 {
   1676    return nir_build_alu(build, nir_op_sdot_2x16_iadd, src0, src1, src2, NULL);
   1677 }
   1678 static inline nir_ssa_def *
   1679 nir_sdot_2x16_iadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1680 {
   1681    return nir_build_alu(build, nir_op_sdot_2x16_iadd_sat, src0, src1, src2, NULL);
   1682 }
   1683 static inline nir_ssa_def *
   1684 nir_sdot_4x8_iadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1685 {
   1686    return nir_build_alu(build, nir_op_sdot_4x8_iadd, src0, src1, src2, NULL);
   1687 }
   1688 static inline nir_ssa_def *
   1689 nir_sdot_4x8_iadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1690 {
   1691    return nir_build_alu(build, nir_op_sdot_4x8_iadd_sat, src0, src1, src2, NULL);
   1692 }
   1693 static inline nir_ssa_def *
   1694 nir_seq(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1695 {
   1696    return nir_build_alu(build, nir_op_seq, src0, src1, NULL, NULL);
   1697 }
   1698 static inline nir_ssa_def *
   1699 nir_sge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1700 {
   1701    return nir_build_alu(build, nir_op_sge, src0, src1, NULL, NULL);
   1702 }
   1703 static inline nir_ssa_def *
   1704 nir_slt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1705 {
   1706    return nir_build_alu(build, nir_op_slt, src0, src1, NULL, NULL);
   1707 }
   1708 static inline nir_ssa_def *
   1709 nir_sne(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1710 {
   1711    return nir_build_alu(build, nir_op_sne, src0, src1, NULL, NULL);
   1712 }
   1713 static inline nir_ssa_def *
   1714 nir_sudot_4x8_iadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1715 {
   1716    return nir_build_alu(build, nir_op_sudot_4x8_iadd, src0, src1, src2, NULL);
   1717 }
   1718 static inline nir_ssa_def *
   1719 nir_sudot_4x8_iadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1720 {
   1721    return nir_build_alu(build, nir_op_sudot_4x8_iadd_sat, src0, src1, src2, NULL);
   1722 }
   1723 static inline nir_ssa_def *
   1724 nir_u2f16(nir_builder *build, nir_ssa_def *src0)
   1725 {
   1726    return nir_build_alu(build, nir_op_u2f16, src0, NULL, NULL, NULL);
   1727 }
   1728 static inline nir_ssa_def *
   1729 nir_u2f32(nir_builder *build, nir_ssa_def *src0)
   1730 {
   1731    return nir_build_alu(build, nir_op_u2f32, src0, NULL, NULL, NULL);
   1732 }
   1733 static inline nir_ssa_def *
   1734 nir_u2f64(nir_builder *build, nir_ssa_def *src0)
   1735 {
   1736    return nir_build_alu(build, nir_op_u2f64, src0, NULL, NULL, NULL);
   1737 }
   1738 static inline nir_ssa_def *
   1739 nir_u2fmp(nir_builder *build, nir_ssa_def *src0)
   1740 {
   1741    return nir_build_alu(build, nir_op_u2fmp, src0, NULL, NULL, NULL);
   1742 }
   1743 static inline nir_ssa_def *
   1744 nir_u2u1(nir_builder *build, nir_ssa_def *src0)
   1745 {
   1746    return nir_build_alu(build, nir_op_u2u1, src0, NULL, NULL, NULL);
   1747 }
   1748 static inline nir_ssa_def *
   1749 nir_u2u16(nir_builder *build, nir_ssa_def *src0)
   1750 {
   1751    return nir_build_alu(build, nir_op_u2u16, src0, NULL, NULL, NULL);
   1752 }
   1753 static inline nir_ssa_def *
   1754 nir_u2u32(nir_builder *build, nir_ssa_def *src0)
   1755 {
   1756    return nir_build_alu(build, nir_op_u2u32, src0, NULL, NULL, NULL);
   1757 }
   1758 static inline nir_ssa_def *
   1759 nir_u2u64(nir_builder *build, nir_ssa_def *src0)
   1760 {
   1761    return nir_build_alu(build, nir_op_u2u64, src0, NULL, NULL, NULL);
   1762 }
   1763 static inline nir_ssa_def *
   1764 nir_u2u8(nir_builder *build, nir_ssa_def *src0)
   1765 {
   1766    return nir_build_alu(build, nir_op_u2u8, src0, NULL, NULL, NULL);
   1767 }
   1768 static inline nir_ssa_def *
   1769 nir_uabs_isub(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1770 {
   1771    return nir_build_alu(build, nir_op_uabs_isub, src0, src1, NULL, NULL);
   1772 }
   1773 static inline nir_ssa_def *
   1774 nir_uabs_usub(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1775 {
   1776    return nir_build_alu(build, nir_op_uabs_usub, src0, src1, NULL, NULL);
   1777 }
   1778 static inline nir_ssa_def *
   1779 nir_uadd_carry(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1780 {
   1781    return nir_build_alu(build, nir_op_uadd_carry, src0, src1, NULL, NULL);
   1782 }
   1783 static inline nir_ssa_def *
   1784 nir_uadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1785 {
   1786    return nir_build_alu(build, nir_op_uadd_sat, src0, src1, NULL, NULL);
   1787 }
   1788 static inline nir_ssa_def *
   1789 nir_ubfe(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1790 {
   1791    return nir_build_alu(build, nir_op_ubfe, src0, src1, src2, NULL);
   1792 }
   1793 static inline nir_ssa_def *
   1794 nir_ubitfield_extract(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1795 {
   1796    return nir_build_alu(build, nir_op_ubitfield_extract, src0, src1, src2, NULL);
   1797 }
   1798 static inline nir_ssa_def *
   1799 nir_uclz(nir_builder *build, nir_ssa_def *src0)
   1800 {
   1801    return nir_build_alu(build, nir_op_uclz, src0, NULL, NULL, NULL);
   1802 }
   1803 static inline nir_ssa_def *
   1804 nir_udiv(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1805 {
   1806    return nir_build_alu(build, nir_op_udiv, src0, src1, NULL, NULL);
   1807 }
   1808 static inline nir_ssa_def *
   1809 nir_udot_2x16_uadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1810 {
   1811    return nir_build_alu(build, nir_op_udot_2x16_uadd, src0, src1, src2, NULL);
   1812 }
   1813 static inline nir_ssa_def *
   1814 nir_udot_2x16_uadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1815 {
   1816    return nir_build_alu(build, nir_op_udot_2x16_uadd_sat, src0, src1, src2, NULL);
   1817 }
   1818 static inline nir_ssa_def *
   1819 nir_udot_4x8_uadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1820 {
   1821    return nir_build_alu(build, nir_op_udot_4x8_uadd, src0, src1, src2, NULL);
   1822 }
   1823 static inline nir_ssa_def *
   1824 nir_udot_4x8_uadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1825 {
   1826    return nir_build_alu(build, nir_op_udot_4x8_uadd_sat, src0, src1, src2, NULL);
   1827 }
   1828 static inline nir_ssa_def *
   1829 nir_ufind_msb(nir_builder *build, nir_ssa_def *src0)
   1830 {
   1831    return nir_build_alu(build, nir_op_ufind_msb, src0, NULL, NULL, NULL);
   1832 }
   1833 static inline nir_ssa_def *
   1834 nir_ufind_msb_rev(nir_builder *build, nir_ssa_def *src0)
   1835 {
   1836    return nir_build_alu(build, nir_op_ufind_msb_rev, src0, NULL, NULL, NULL);
   1837 }
   1838 static inline nir_ssa_def *
   1839 nir_uge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1840 {
   1841    return nir_build_alu(build, nir_op_uge, src0, src1, NULL, NULL);
   1842 }
   1843 static inline nir_ssa_def *
   1844 nir_uge16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1845 {
   1846    return nir_build_alu(build, nir_op_uge16, src0, src1, NULL, NULL);
   1847 }
   1848 static inline nir_ssa_def *
   1849 nir_uge32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1850 {
   1851    return nir_build_alu(build, nir_op_uge32, src0, src1, NULL, NULL);
   1852 }
   1853 static inline nir_ssa_def *
   1854 nir_uge8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1855 {
   1856    return nir_build_alu(build, nir_op_uge8, src0, src1, NULL, NULL);
   1857 }
   1858 static inline nir_ssa_def *
   1859 nir_uhadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1860 {
   1861    return nir_build_alu(build, nir_op_uhadd, src0, src1, NULL, NULL);
   1862 }
   1863 static inline nir_ssa_def *
   1864 nir_ult(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1865 {
   1866    return nir_build_alu(build, nir_op_ult, src0, src1, NULL, NULL);
   1867 }
   1868 static inline nir_ssa_def *
   1869 nir_ult16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1870 {
   1871    return nir_build_alu(build, nir_op_ult16, src0, src1, NULL, NULL);
   1872 }
   1873 static inline nir_ssa_def *
   1874 nir_ult32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1875 {
   1876    return nir_build_alu(build, nir_op_ult32, src0, src1, NULL, NULL);
   1877 }
   1878 static inline nir_ssa_def *
   1879 nir_ult8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1880 {
   1881    return nir_build_alu(build, nir_op_ult8, src0, src1, NULL, NULL);
   1882 }
   1883 static inline nir_ssa_def *
   1884 nir_umad24(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1885 {
   1886    return nir_build_alu(build, nir_op_umad24, src0, src1, src2, NULL);
   1887 }
   1888 static inline nir_ssa_def *
   1889 nir_umad24_relaxed(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   1890 {
   1891    return nir_build_alu(build, nir_op_umad24_relaxed, src0, src1, src2, NULL);
   1892 }
   1893 static inline nir_ssa_def *
   1894 nir_umax(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1895 {
   1896    return nir_build_alu(build, nir_op_umax, src0, src1, NULL, NULL);
   1897 }
   1898 static inline nir_ssa_def *
   1899 nir_umax_4x8_vc4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1900 {
   1901    return nir_build_alu(build, nir_op_umax_4x8_vc4, src0, src1, NULL, NULL);
   1902 }
   1903 static inline nir_ssa_def *
   1904 nir_umin(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1905 {
   1906    return nir_build_alu(build, nir_op_umin, src0, src1, NULL, NULL);
   1907 }
   1908 static inline nir_ssa_def *
   1909 nir_umin_4x8_vc4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1910 {
   1911    return nir_build_alu(build, nir_op_umin_4x8_vc4, src0, src1, NULL, NULL);
   1912 }
   1913 static inline nir_ssa_def *
   1914 nir_umod(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1915 {
   1916    return nir_build_alu(build, nir_op_umod, src0, src1, NULL, NULL);
   1917 }
   1918 static inline nir_ssa_def *
   1919 nir_umul24(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1920 {
   1921    return nir_build_alu(build, nir_op_umul24, src0, src1, NULL, NULL);
   1922 }
   1923 static inline nir_ssa_def *
   1924 nir_umul24_relaxed(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1925 {
   1926    return nir_build_alu(build, nir_op_umul24_relaxed, src0, src1, NULL, NULL);
   1927 }
   1928 static inline nir_ssa_def *
   1929 nir_umul_2x32_64(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1930 {
   1931    return nir_build_alu(build, nir_op_umul_2x32_64, src0, src1, NULL, NULL);
   1932 }
   1933 static inline nir_ssa_def *
   1934 nir_umul_32x16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1935 {
   1936    return nir_build_alu(build, nir_op_umul_32x16, src0, src1, NULL, NULL);
   1937 }
   1938 static inline nir_ssa_def *
   1939 nir_umul_high(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1940 {
   1941    return nir_build_alu(build, nir_op_umul_high, src0, src1, NULL, NULL);
   1942 }
   1943 static inline nir_ssa_def *
   1944 nir_umul_low(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1945 {
   1946    return nir_build_alu(build, nir_op_umul_low, src0, src1, NULL, NULL);
   1947 }
   1948 static inline nir_ssa_def *
   1949 nir_umul_unorm_4x8_vc4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   1950 {
   1951    return nir_build_alu(build, nir_op_umul_unorm_4x8_vc4, src0, src1, NULL, NULL);
   1952 }
   1953 static inline nir_ssa_def *
   1954 nir_unpack_32_2x16(nir_builder *build, nir_ssa_def *src0)
   1955 {
   1956    return nir_build_alu(build, nir_op_unpack_32_2x16, src0, NULL, NULL, NULL);
   1957 }
   1958 static inline nir_ssa_def *
   1959 nir_unpack_32_2x16_split_x(nir_builder *build, nir_ssa_def *src0)
   1960 {
   1961    return nir_build_alu(build, nir_op_unpack_32_2x16_split_x, src0, NULL, NULL, NULL);
   1962 }
   1963 static inline nir_ssa_def *
   1964 nir_unpack_32_2x16_split_y(nir_builder *build, nir_ssa_def *src0)
   1965 {
   1966    return nir_build_alu(build, nir_op_unpack_32_2x16_split_y, src0, NULL, NULL, NULL);
   1967 }
   1968 static inline nir_ssa_def *
   1969 nir_unpack_32_4x8(nir_builder *build, nir_ssa_def *src0)
   1970 {
   1971    return nir_build_alu(build, nir_op_unpack_32_4x8, src0, NULL, NULL, NULL);
   1972 }
   1973 static inline nir_ssa_def *
   1974 nir_unpack_64_2x32(nir_builder *build, nir_ssa_def *src0)
   1975 {
   1976    return nir_build_alu(build, nir_op_unpack_64_2x32, src0, NULL, NULL, NULL);
   1977 }
   1978 static inline nir_ssa_def *
   1979 nir_unpack_64_2x32_split_x(nir_builder *build, nir_ssa_def *src0)
   1980 {
   1981    return nir_build_alu(build, nir_op_unpack_64_2x32_split_x, src0, NULL, NULL, NULL);
   1982 }
   1983 static inline nir_ssa_def *
   1984 nir_unpack_64_2x32_split_y(nir_builder *build, nir_ssa_def *src0)
   1985 {
   1986    return nir_build_alu(build, nir_op_unpack_64_2x32_split_y, src0, NULL, NULL, NULL);
   1987 }
   1988 static inline nir_ssa_def *
   1989 nir_unpack_64_4x16(nir_builder *build, nir_ssa_def *src0)
   1990 {
   1991    return nir_build_alu(build, nir_op_unpack_64_4x16, src0, NULL, NULL, NULL);
   1992 }
   1993 static inline nir_ssa_def *
   1994 nir_unpack_double_2x32_dxil(nir_builder *build, nir_ssa_def *src0)
   1995 {
   1996    return nir_build_alu(build, nir_op_unpack_double_2x32_dxil, src0, NULL, NULL, NULL);
   1997 }
   1998 static inline nir_ssa_def *
   1999 nir_unpack_half_2x16(nir_builder *build, nir_ssa_def *src0)
   2000 {
   2001    return nir_build_alu(build, nir_op_unpack_half_2x16, src0, NULL, NULL, NULL);
   2002 }
   2003 static inline nir_ssa_def *
   2004 nir_unpack_half_2x16_flush_to_zero(nir_builder *build, nir_ssa_def *src0)
   2005 {
   2006    return nir_build_alu(build, nir_op_unpack_half_2x16_flush_to_zero, src0, NULL, NULL, NULL);
   2007 }
   2008 static inline nir_ssa_def *
   2009 nir_unpack_half_2x16_split_x(nir_builder *build, nir_ssa_def *src0)
   2010 {
   2011    return nir_build_alu(build, nir_op_unpack_half_2x16_split_x, src0, NULL, NULL, NULL);
   2012 }
   2013 static inline nir_ssa_def *
   2014 nir_unpack_half_2x16_split_x_flush_to_zero(nir_builder *build, nir_ssa_def *src0)
   2015 {
   2016    return nir_build_alu(build, nir_op_unpack_half_2x16_split_x_flush_to_zero, src0, NULL, NULL, NULL);
   2017 }
   2018 static inline nir_ssa_def *
   2019 nir_unpack_half_2x16_split_y(nir_builder *build, nir_ssa_def *src0)
   2020 {
   2021    return nir_build_alu(build, nir_op_unpack_half_2x16_split_y, src0, NULL, NULL, NULL);
   2022 }
   2023 static inline nir_ssa_def *
   2024 nir_unpack_half_2x16_split_y_flush_to_zero(nir_builder *build, nir_ssa_def *src0)
   2025 {
   2026    return nir_build_alu(build, nir_op_unpack_half_2x16_split_y_flush_to_zero, src0, NULL, NULL, NULL);
   2027 }
   2028 static inline nir_ssa_def *
   2029 nir_unpack_snorm_2x16(nir_builder *build, nir_ssa_def *src0)
   2030 {
   2031    return nir_build_alu(build, nir_op_unpack_snorm_2x16, src0, NULL, NULL, NULL);
   2032 }
   2033 static inline nir_ssa_def *
   2034 nir_unpack_snorm_4x8(nir_builder *build, nir_ssa_def *src0)
   2035 {
   2036    return nir_build_alu(build, nir_op_unpack_snorm_4x8, src0, NULL, NULL, NULL);
   2037 }
   2038 static inline nir_ssa_def *
   2039 nir_unpack_unorm_2x16(nir_builder *build, nir_ssa_def *src0)
   2040 {
   2041    return nir_build_alu(build, nir_op_unpack_unorm_2x16, src0, NULL, NULL, NULL);
   2042 }
   2043 static inline nir_ssa_def *
   2044 nir_unpack_unorm_4x8(nir_builder *build, nir_ssa_def *src0)
   2045 {
   2046    return nir_build_alu(build, nir_op_unpack_unorm_4x8, src0, NULL, NULL, NULL);
   2047 }
   2048 static inline nir_ssa_def *
   2049 nir_urhadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2050 {
   2051    return nir_build_alu(build, nir_op_urhadd, src0, src1, NULL, NULL);
   2052 }
   2053 static inline nir_ssa_def *
   2054 nir_urol(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2055 {
   2056    return nir_build_alu(build, nir_op_urol, src0, src1, NULL, NULL);
   2057 }
   2058 static inline nir_ssa_def *
   2059 nir_uror(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2060 {
   2061    return nir_build_alu(build, nir_op_uror, src0, src1, NULL, NULL);
   2062 }
   2063 static inline nir_ssa_def *
   2064 nir_usadd_4x8_vc4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2065 {
   2066    return nir_build_alu(build, nir_op_usadd_4x8_vc4, src0, src1, NULL, NULL);
   2067 }
   2068 static inline nir_ssa_def *
   2069 nir_ushr(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2070 {
   2071    return nir_build_alu(build, nir_op_ushr, src0, src1, NULL, NULL);
   2072 }
   2073 static inline nir_ssa_def *
   2074 nir_ussub_4x8_vc4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2075 {
   2076    return nir_build_alu(build, nir_op_ussub_4x8_vc4, src0, src1, NULL, NULL);
   2077 }
   2078 static inline nir_ssa_def *
   2079 nir_usub_borrow(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2080 {
   2081    return nir_build_alu(build, nir_op_usub_borrow, src0, src1, NULL, NULL);
   2082 }
   2083 static inline nir_ssa_def *
   2084 nir_usub_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2085 {
   2086    return nir_build_alu(build, nir_op_usub_sat, src0, src1, NULL, NULL);
   2087 }
   2088 static inline nir_ssa_def *
   2089 nir_vec16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, nir_ssa_def *src5, nir_ssa_def *src6, nir_ssa_def *src7, nir_ssa_def *src8, nir_ssa_def *src9, nir_ssa_def *src10, nir_ssa_def *src11, nir_ssa_def *src12, nir_ssa_def *src13, nir_ssa_def *src14, nir_ssa_def *src15)
   2090 {
   2091    nir_ssa_def *srcs[16] = {src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, src11, src12, src13, src14, src15};
   2092    return nir_build_alu_src_arr(build, nir_op_vec16, srcs);
   2093 }
   2094 static inline nir_ssa_def *
   2095 nir_vec2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   2096 {
   2097    return nir_build_alu(build, nir_op_vec2, src0, src1, NULL, NULL);
   2098 }
   2099 static inline nir_ssa_def *
   2100 nir_vec3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   2101 {
   2102    return nir_build_alu(build, nir_op_vec3, src0, src1, src2, NULL);
   2103 }
   2104 static inline nir_ssa_def *
   2105 nir_vec4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
   2106 {
   2107    return nir_build_alu(build, nir_op_vec4, src0, src1, src2, src3);
   2108 }
   2109 static inline nir_ssa_def *
   2110 nir_vec5(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4)
   2111 {
   2112    nir_ssa_def *srcs[5] = {src0, src1, src2, src3, src4};
   2113    return nir_build_alu_src_arr(build, nir_op_vec5, srcs);
   2114 }
   2115 static inline nir_ssa_def *
   2116 nir_vec8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, nir_ssa_def *src5, nir_ssa_def *src6, nir_ssa_def *src7)
   2117 {
   2118    nir_ssa_def *srcs[8] = {src0, src1, src2, src3, src4, src5, src6, src7};
   2119    return nir_build_alu_src_arr(build, nir_op_vec8, srcs);
   2120 }
   2121 
   2122 struct _nir_accept_ray_intersection_indices {
   2123    int _; /* exists to avoid empty initializers */
   2124 };
   2125 struct _nir_addr_mode_is_indices {
   2126    int _; /* exists to avoid empty initializers */
   2127    nir_variable_mode memory_modes;
   2128 };
   2129 struct _nir_alloc_vertices_and_primitives_amd_indices {
   2130    int _; /* exists to avoid empty initializers */
   2131 };
   2132 struct _nir_atomic_counter_add_indices {
   2133    int _; /* exists to avoid empty initializers */
   2134    int base;
   2135 };
   2136 struct _nir_atomic_counter_add_deref_indices {
   2137    int _; /* exists to avoid empty initializers */
   2138 };
   2139 struct _nir_atomic_counter_and_indices {
   2140    int _; /* exists to avoid empty initializers */
   2141    int base;
   2142 };
   2143 struct _nir_atomic_counter_and_deref_indices {
   2144    int _; /* exists to avoid empty initializers */
   2145 };
   2146 struct _nir_atomic_counter_comp_swap_indices {
   2147    int _; /* exists to avoid empty initializers */
   2148    int base;
   2149 };
   2150 struct _nir_atomic_counter_comp_swap_deref_indices {
   2151    int _; /* exists to avoid empty initializers */
   2152 };
   2153 struct _nir_atomic_counter_exchange_indices {
   2154    int _; /* exists to avoid empty initializers */
   2155    int base;
   2156 };
   2157 struct _nir_atomic_counter_exchange_deref_indices {
   2158    int _; /* exists to avoid empty initializers */
   2159 };
   2160 struct _nir_atomic_counter_inc_indices {
   2161    int _; /* exists to avoid empty initializers */
   2162    int base;
   2163 };
   2164 struct _nir_atomic_counter_inc_deref_indices {
   2165    int _; /* exists to avoid empty initializers */
   2166 };
   2167 struct _nir_atomic_counter_max_indices {
   2168    int _; /* exists to avoid empty initializers */
   2169    int base;
   2170 };
   2171 struct _nir_atomic_counter_max_deref_indices {
   2172    int _; /* exists to avoid empty initializers */
   2173 };
   2174 struct _nir_atomic_counter_min_indices {
   2175    int _; /* exists to avoid empty initializers */
   2176    int base;
   2177 };
   2178 struct _nir_atomic_counter_min_deref_indices {
   2179    int _; /* exists to avoid empty initializers */
   2180 };
   2181 struct _nir_atomic_counter_or_indices {
   2182    int _; /* exists to avoid empty initializers */
   2183    int base;
   2184 };
   2185 struct _nir_atomic_counter_or_deref_indices {
   2186    int _; /* exists to avoid empty initializers */
   2187 };
   2188 struct _nir_atomic_counter_post_dec_indices {
   2189    int _; /* exists to avoid empty initializers */
   2190    int base;
   2191 };
   2192 struct _nir_atomic_counter_post_dec_deref_indices {
   2193    int _; /* exists to avoid empty initializers */
   2194 };
   2195 struct _nir_atomic_counter_pre_dec_indices {
   2196    int _; /* exists to avoid empty initializers */
   2197    int base;
   2198 };
   2199 struct _nir_atomic_counter_pre_dec_deref_indices {
   2200    int _; /* exists to avoid empty initializers */
   2201 };
   2202 struct _nir_atomic_counter_read_indices {
   2203    int _; /* exists to avoid empty initializers */
   2204    int base;
   2205 };
   2206 struct _nir_atomic_counter_read_deref_indices {
   2207    int _; /* exists to avoid empty initializers */
   2208 };
   2209 struct _nir_atomic_counter_xor_indices {
   2210    int _; /* exists to avoid empty initializers */
   2211    int base;
   2212 };
   2213 struct _nir_atomic_counter_xor_deref_indices {
   2214    int _; /* exists to avoid empty initializers */
   2215 };
   2216 struct _nir_ballot_indices {
   2217    int _; /* exists to avoid empty initializers */
   2218 };
   2219 struct _nir_ballot_bit_count_exclusive_indices {
   2220    int _; /* exists to avoid empty initializers */
   2221 };
   2222 struct _nir_ballot_bit_count_inclusive_indices {
   2223    int _; /* exists to avoid empty initializers */
   2224 };
   2225 struct _nir_ballot_bit_count_reduce_indices {
   2226    int _; /* exists to avoid empty initializers */
   2227 };
   2228 struct _nir_ballot_bitfield_extract_indices {
   2229    int _; /* exists to avoid empty initializers */
   2230 };
   2231 struct _nir_ballot_find_lsb_indices {
   2232    int _; /* exists to avoid empty initializers */
   2233 };
   2234 struct _nir_ballot_find_msb_indices {
   2235    int _; /* exists to avoid empty initializers */
   2236 };
   2237 struct _nir_begin_invocation_interlock_indices {
   2238    int _; /* exists to avoid empty initializers */
   2239 };
   2240 struct _nir_bindless_image_atomic_add_indices {
   2241    int _; /* exists to avoid empty initializers */
   2242    enum glsl_sampler_dim image_dim;
   2243    bool image_array;
   2244    enum pipe_format format;
   2245    enum gl_access_qualifier access;
   2246 };
   2247 struct _nir_bindless_image_atomic_and_indices {
   2248    int _; /* exists to avoid empty initializers */
   2249    enum glsl_sampler_dim image_dim;
   2250    bool image_array;
   2251    enum pipe_format format;
   2252    enum gl_access_qualifier access;
   2253 };
   2254 struct _nir_bindless_image_atomic_comp_swap_indices {
   2255    int _; /* exists to avoid empty initializers */
   2256    enum glsl_sampler_dim image_dim;
   2257    bool image_array;
   2258    enum pipe_format format;
   2259    enum gl_access_qualifier access;
   2260 };
   2261 struct _nir_bindless_image_atomic_dec_wrap_indices {
   2262    int _; /* exists to avoid empty initializers */
   2263    enum glsl_sampler_dim image_dim;
   2264    bool image_array;
   2265    enum pipe_format format;
   2266    enum gl_access_qualifier access;
   2267 };
   2268 struct _nir_bindless_image_atomic_exchange_indices {
   2269    int _; /* exists to avoid empty initializers */
   2270    enum glsl_sampler_dim image_dim;
   2271    bool image_array;
   2272    enum pipe_format format;
   2273    enum gl_access_qualifier access;
   2274 };
   2275 struct _nir_bindless_image_atomic_fadd_indices {
   2276    int _; /* exists to avoid empty initializers */
   2277    enum glsl_sampler_dim image_dim;
   2278    bool image_array;
   2279    enum pipe_format format;
   2280    enum gl_access_qualifier access;
   2281 };
   2282 struct _nir_bindless_image_atomic_fmax_indices {
   2283    int _; /* exists to avoid empty initializers */
   2284    enum glsl_sampler_dim image_dim;
   2285    bool image_array;
   2286    enum pipe_format format;
   2287    enum gl_access_qualifier access;
   2288 };
   2289 struct _nir_bindless_image_atomic_fmin_indices {
   2290    int _; /* exists to avoid empty initializers */
   2291    enum glsl_sampler_dim image_dim;
   2292    bool image_array;
   2293    enum pipe_format format;
   2294    enum gl_access_qualifier access;
   2295 };
   2296 struct _nir_bindless_image_atomic_imax_indices {
   2297    int _; /* exists to avoid empty initializers */
   2298    enum glsl_sampler_dim image_dim;
   2299    bool image_array;
   2300    enum pipe_format format;
   2301    enum gl_access_qualifier access;
   2302 };
   2303 struct _nir_bindless_image_atomic_imin_indices {
   2304    int _; /* exists to avoid empty initializers */
   2305    enum glsl_sampler_dim image_dim;
   2306    bool image_array;
   2307    enum pipe_format format;
   2308    enum gl_access_qualifier access;
   2309 };
   2310 struct _nir_bindless_image_atomic_inc_wrap_indices {
   2311    int _; /* exists to avoid empty initializers */
   2312    enum glsl_sampler_dim image_dim;
   2313    bool image_array;
   2314    enum pipe_format format;
   2315    enum gl_access_qualifier access;
   2316 };
   2317 struct _nir_bindless_image_atomic_or_indices {
   2318    int _; /* exists to avoid empty initializers */
   2319    enum glsl_sampler_dim image_dim;
   2320    bool image_array;
   2321    enum pipe_format format;
   2322    enum gl_access_qualifier access;
   2323 };
   2324 struct _nir_bindless_image_atomic_umax_indices {
   2325    int _; /* exists to avoid empty initializers */
   2326    enum glsl_sampler_dim image_dim;
   2327    bool image_array;
   2328    enum pipe_format format;
   2329    enum gl_access_qualifier access;
   2330 };
   2331 struct _nir_bindless_image_atomic_umin_indices {
   2332    int _; /* exists to avoid empty initializers */
   2333    enum glsl_sampler_dim image_dim;
   2334    bool image_array;
   2335    enum pipe_format format;
   2336    enum gl_access_qualifier access;
   2337 };
   2338 struct _nir_bindless_image_atomic_xor_indices {
   2339    int _; /* exists to avoid empty initializers */
   2340    enum glsl_sampler_dim image_dim;
   2341    bool image_array;
   2342    enum pipe_format format;
   2343    enum gl_access_qualifier access;
   2344 };
   2345 struct _nir_bindless_image_format_indices {
   2346    int _; /* exists to avoid empty initializers */
   2347    enum glsl_sampler_dim image_dim;
   2348    bool image_array;
   2349    enum pipe_format format;
   2350    enum gl_access_qualifier access;
   2351 };
   2352 struct _nir_bindless_image_load_indices {
   2353    int _; /* exists to avoid empty initializers */
   2354    enum glsl_sampler_dim image_dim;
   2355    bool image_array;
   2356    enum pipe_format format;
   2357    enum gl_access_qualifier access;
   2358    nir_alu_type dest_type;
   2359 };
   2360 struct _nir_bindless_image_load_raw_intel_indices {
   2361    int _; /* exists to avoid empty initializers */
   2362    enum glsl_sampler_dim image_dim;
   2363    bool image_array;
   2364    enum pipe_format format;
   2365    enum gl_access_qualifier access;
   2366 };
   2367 struct _nir_bindless_image_order_indices {
   2368    int _; /* exists to avoid empty initializers */
   2369    enum glsl_sampler_dim image_dim;
   2370    bool image_array;
   2371    enum pipe_format format;
   2372    enum gl_access_qualifier access;
   2373 };
   2374 struct _nir_bindless_image_samples_indices {
   2375    int _; /* exists to avoid empty initializers */
   2376    enum glsl_sampler_dim image_dim;
   2377    bool image_array;
   2378    enum pipe_format format;
   2379    enum gl_access_qualifier access;
   2380 };
   2381 struct _nir_bindless_image_size_indices {
   2382    int _; /* exists to avoid empty initializers */
   2383    enum glsl_sampler_dim image_dim;
   2384    bool image_array;
   2385    enum pipe_format format;
   2386    enum gl_access_qualifier access;
   2387 };
   2388 struct _nir_bindless_image_sparse_load_indices {
   2389    int _; /* exists to avoid empty initializers */
   2390    enum glsl_sampler_dim image_dim;
   2391    bool image_array;
   2392    enum pipe_format format;
   2393    enum gl_access_qualifier access;
   2394    nir_alu_type dest_type;
   2395 };
   2396 struct _nir_bindless_image_store_indices {
   2397    int _; /* exists to avoid empty initializers */
   2398    enum glsl_sampler_dim image_dim;
   2399    bool image_array;
   2400    enum pipe_format format;
   2401    enum gl_access_qualifier access;
   2402    nir_alu_type src_type;
   2403 };
   2404 struct _nir_bindless_image_store_raw_intel_indices {
   2405    int _; /* exists to avoid empty initializers */
   2406    enum glsl_sampler_dim image_dim;
   2407    bool image_array;
   2408    enum pipe_format format;
   2409    enum gl_access_qualifier access;
   2410 };
   2411 struct _nir_bindless_resource_ir3_indices {
   2412    int _; /* exists to avoid empty initializers */
   2413    unsigned desc_set;
   2414 };
   2415 struct _nir_btd_retire_intel_indices {
   2416    int _; /* exists to avoid empty initializers */
   2417 };
   2418 struct _nir_btd_spawn_intel_indices {
   2419    int _; /* exists to avoid empty initializers */
   2420 };
   2421 struct _nir_btd_stack_push_intel_indices {
   2422    int _; /* exists to avoid empty initializers */
   2423    unsigned stack_size;
   2424 };
   2425 struct _nir_bvh64_intersect_ray_amd_indices {
   2426    int _; /* exists to avoid empty initializers */
   2427 };
   2428 struct _nir_byte_permute_amd_indices {
   2429    int _; /* exists to avoid empty initializers */
   2430 };
   2431 struct _nir_cond_end_ir3_indices {
   2432    int _; /* exists to avoid empty initializers */
   2433 };
   2434 struct _nir_control_barrier_indices {
   2435    int _; /* exists to avoid empty initializers */
   2436 };
   2437 struct _nir_convert_alu_types_indices {
   2438    int _; /* exists to avoid empty initializers */
   2439    nir_alu_type src_type;
   2440    nir_alu_type dest_type;
   2441    nir_rounding_mode rounding_mode;
   2442    unsigned saturate;
   2443 };
   2444 struct _nir_copy_deref_indices {
   2445    int _; /* exists to avoid empty initializers */
   2446    enum gl_access_qualifier dst_access;
   2447    enum gl_access_qualifier src_access;
   2448 };
   2449 struct _nir_demote_indices {
   2450    int _; /* exists to avoid empty initializers */
   2451 };
   2452 struct _nir_demote_if_indices {
   2453    int _; /* exists to avoid empty initializers */
   2454 };
   2455 struct _nir_deref_atomic_add_indices {
   2456    int _; /* exists to avoid empty initializers */
   2457    enum gl_access_qualifier access;
   2458 };
   2459 struct _nir_deref_atomic_and_indices {
   2460    int _; /* exists to avoid empty initializers */
   2461    enum gl_access_qualifier access;
   2462 };
   2463 struct _nir_deref_atomic_comp_swap_indices {
   2464    int _; /* exists to avoid empty initializers */
   2465    enum gl_access_qualifier access;
   2466 };
   2467 struct _nir_deref_atomic_exchange_indices {
   2468    int _; /* exists to avoid empty initializers */
   2469    enum gl_access_qualifier access;
   2470 };
   2471 struct _nir_deref_atomic_fadd_indices {
   2472    int _; /* exists to avoid empty initializers */
   2473    enum gl_access_qualifier access;
   2474 };
   2475 struct _nir_deref_atomic_fcomp_swap_indices {
   2476    int _; /* exists to avoid empty initializers */
   2477    enum gl_access_qualifier access;
   2478 };
   2479 struct _nir_deref_atomic_fmax_indices {
   2480    int _; /* exists to avoid empty initializers */
   2481    enum gl_access_qualifier access;
   2482 };
   2483 struct _nir_deref_atomic_fmin_indices {
   2484    int _; /* exists to avoid empty initializers */
   2485    enum gl_access_qualifier access;
   2486 };
   2487 struct _nir_deref_atomic_imax_indices {
   2488    int _; /* exists to avoid empty initializers */
   2489    enum gl_access_qualifier access;
   2490 };
   2491 struct _nir_deref_atomic_imin_indices {
   2492    int _; /* exists to avoid empty initializers */
   2493    enum gl_access_qualifier access;
   2494 };
   2495 struct _nir_deref_atomic_or_indices {
   2496    int _; /* exists to avoid empty initializers */
   2497    enum gl_access_qualifier access;
   2498 };
   2499 struct _nir_deref_atomic_umax_indices {
   2500    int _; /* exists to avoid empty initializers */
   2501    enum gl_access_qualifier access;
   2502 };
   2503 struct _nir_deref_atomic_umin_indices {
   2504    int _; /* exists to avoid empty initializers */
   2505    enum gl_access_qualifier access;
   2506 };
   2507 struct _nir_deref_atomic_xor_indices {
   2508    int _; /* exists to avoid empty initializers */
   2509    enum gl_access_qualifier access;
   2510 };
   2511 struct _nir_deref_buffer_array_length_indices {
   2512    int _; /* exists to avoid empty initializers */
   2513    enum gl_access_qualifier access;
   2514 };
   2515 struct _nir_deref_mode_is_indices {
   2516    int _; /* exists to avoid empty initializers */
   2517    nir_variable_mode memory_modes;
   2518 };
   2519 struct _nir_discard_indices {
   2520    int _; /* exists to avoid empty initializers */
   2521 };
   2522 struct _nir_discard_if_indices {
   2523    int _; /* exists to avoid empty initializers */
   2524 };
   2525 struct _nir_elect_indices {
   2526    int _; /* exists to avoid empty initializers */
   2527 };
   2528 struct _nir_emit_vertex_indices {
   2529    int _; /* exists to avoid empty initializers */
   2530    unsigned stream_id;
   2531 };
   2532 struct _nir_emit_vertex_with_counter_indices {
   2533    int _; /* exists to avoid empty initializers */
   2534    unsigned stream_id;
   2535 };
   2536 struct _nir_end_invocation_interlock_indices {
   2537    int _; /* exists to avoid empty initializers */
   2538 };
   2539 struct _nir_end_patch_ir3_indices {
   2540    int _; /* exists to avoid empty initializers */
   2541 };
   2542 struct _nir_end_primitive_indices {
   2543    int _; /* exists to avoid empty initializers */
   2544    unsigned stream_id;
   2545 };
   2546 struct _nir_end_primitive_with_counter_indices {
   2547    int _; /* exists to avoid empty initializers */
   2548    unsigned stream_id;
   2549 };
   2550 struct _nir_exclusive_scan_indices {
   2551    int _; /* exists to avoid empty initializers */
   2552    unsigned reduction_op;
   2553 };
   2554 struct _nir_execute_callable_indices {
   2555    int _; /* exists to avoid empty initializers */
   2556 };
   2557 struct _nir_export_primitive_amd_indices {
   2558    int _; /* exists to avoid empty initializers */
   2559 };
   2560 struct _nir_export_vertex_amd_indices {
   2561    int _; /* exists to avoid empty initializers */
   2562 };
   2563 struct _nir_first_invocation_indices {
   2564    int _; /* exists to avoid empty initializers */
   2565 };
   2566 struct _nir_gds_atomic_add_amd_indices {
   2567    int _; /* exists to avoid empty initializers */
   2568    int base;
   2569 };
   2570 struct _nir_get_ssbo_size_indices {
   2571    int _; /* exists to avoid empty initializers */
   2572    enum gl_access_qualifier access;
   2573 };
   2574 struct _nir_get_ubo_size_indices {
   2575    int _; /* exists to avoid empty initializers */
   2576 };
   2577 struct _nir_global_atomic_add_indices {
   2578    int _; /* exists to avoid empty initializers */
   2579    int base;
   2580 };
   2581 struct _nir_global_atomic_and_indices {
   2582    int _; /* exists to avoid empty initializers */
   2583    int base;
   2584 };
   2585 struct _nir_global_atomic_comp_swap_indices {
   2586    int _; /* exists to avoid empty initializers */
   2587    int base;
   2588 };
   2589 struct _nir_global_atomic_exchange_indices {
   2590    int _; /* exists to avoid empty initializers */
   2591    int base;
   2592 };
   2593 struct _nir_global_atomic_fadd_indices {
   2594    int _; /* exists to avoid empty initializers */
   2595    int base;
   2596 };
   2597 struct _nir_global_atomic_fcomp_swap_indices {
   2598    int _; /* exists to avoid empty initializers */
   2599    int base;
   2600 };
   2601 struct _nir_global_atomic_fmax_indices {
   2602    int _; /* exists to avoid empty initializers */
   2603    int base;
   2604 };
   2605 struct _nir_global_atomic_fmin_indices {
   2606    int _; /* exists to avoid empty initializers */
   2607    int base;
   2608 };
   2609 struct _nir_global_atomic_imax_indices {
   2610    int _; /* exists to avoid empty initializers */
   2611    int base;
   2612 };
   2613 struct _nir_global_atomic_imin_indices {
   2614    int _; /* exists to avoid empty initializers */
   2615    int base;
   2616 };
   2617 struct _nir_global_atomic_or_indices {
   2618    int _; /* exists to avoid empty initializers */
   2619    int base;
   2620 };
   2621 struct _nir_global_atomic_umax_indices {
   2622    int _; /* exists to avoid empty initializers */
   2623    int base;
   2624 };
   2625 struct _nir_global_atomic_umin_indices {
   2626    int _; /* exists to avoid empty initializers */
   2627    int base;
   2628 };
   2629 struct _nir_global_atomic_xor_indices {
   2630    int _; /* exists to avoid empty initializers */
   2631    int base;
   2632 };
   2633 struct _nir_group_memory_barrier_indices {
   2634    int _; /* exists to avoid empty initializers */
   2635 };
   2636 struct _nir_has_input_primitive_amd_indices {
   2637    int _; /* exists to avoid empty initializers */
   2638 };
   2639 struct _nir_has_input_vertex_amd_indices {
   2640    int _; /* exists to avoid empty initializers */
   2641 };
   2642 struct _nir_ignore_ray_intersection_indices {
   2643    int _; /* exists to avoid empty initializers */
   2644 };
   2645 struct _nir_image_atomic_add_indices {
   2646    int _; /* exists to avoid empty initializers */
   2647    enum glsl_sampler_dim image_dim;
   2648    bool image_array;
   2649    enum pipe_format format;
   2650    enum gl_access_qualifier access;
   2651 };
   2652 struct _nir_image_atomic_and_indices {
   2653    int _; /* exists to avoid empty initializers */
   2654    enum glsl_sampler_dim image_dim;
   2655    bool image_array;
   2656    enum pipe_format format;
   2657    enum gl_access_qualifier access;
   2658 };
   2659 struct _nir_image_atomic_comp_swap_indices {
   2660    int _; /* exists to avoid empty initializers */
   2661    enum glsl_sampler_dim image_dim;
   2662    bool image_array;
   2663    enum pipe_format format;
   2664    enum gl_access_qualifier access;
   2665 };
   2666 struct _nir_image_atomic_dec_wrap_indices {
   2667    int _; /* exists to avoid empty initializers */
   2668    enum glsl_sampler_dim image_dim;
   2669    bool image_array;
   2670    enum pipe_format format;
   2671    enum gl_access_qualifier access;
   2672 };
   2673 struct _nir_image_atomic_exchange_indices {
   2674    int _; /* exists to avoid empty initializers */
   2675    enum glsl_sampler_dim image_dim;
   2676    bool image_array;
   2677    enum pipe_format format;
   2678    enum gl_access_qualifier access;
   2679 };
   2680 struct _nir_image_atomic_fadd_indices {
   2681    int _; /* exists to avoid empty initializers */
   2682    enum glsl_sampler_dim image_dim;
   2683    bool image_array;
   2684    enum pipe_format format;
   2685    enum gl_access_qualifier access;
   2686 };
   2687 struct _nir_image_atomic_fmax_indices {
   2688    int _; /* exists to avoid empty initializers */
   2689    enum glsl_sampler_dim image_dim;
   2690    bool image_array;
   2691    enum pipe_format format;
   2692    enum gl_access_qualifier access;
   2693 };
   2694 struct _nir_image_atomic_fmin_indices {
   2695    int _; /* exists to avoid empty initializers */
   2696    enum glsl_sampler_dim image_dim;
   2697    bool image_array;
   2698    enum pipe_format format;
   2699    enum gl_access_qualifier access;
   2700 };
   2701 struct _nir_image_atomic_imax_indices {
   2702    int _; /* exists to avoid empty initializers */
   2703    enum glsl_sampler_dim image_dim;
   2704    bool image_array;
   2705    enum pipe_format format;
   2706    enum gl_access_qualifier access;
   2707 };
   2708 struct _nir_image_atomic_imin_indices {
   2709    int _; /* exists to avoid empty initializers */
   2710    enum glsl_sampler_dim image_dim;
   2711    bool image_array;
   2712    enum pipe_format format;
   2713    enum gl_access_qualifier access;
   2714 };
   2715 struct _nir_image_atomic_inc_wrap_indices {
   2716    int _; /* exists to avoid empty initializers */
   2717    enum glsl_sampler_dim image_dim;
   2718    bool image_array;
   2719    enum pipe_format format;
   2720    enum gl_access_qualifier access;
   2721 };
   2722 struct _nir_image_atomic_or_indices {
   2723    int _; /* exists to avoid empty initializers */
   2724    enum glsl_sampler_dim image_dim;
   2725    bool image_array;
   2726    enum pipe_format format;
   2727    enum gl_access_qualifier access;
   2728 };
   2729 struct _nir_image_atomic_umax_indices {
   2730    int _; /* exists to avoid empty initializers */
   2731    enum glsl_sampler_dim image_dim;
   2732    bool image_array;
   2733    enum pipe_format format;
   2734    enum gl_access_qualifier access;
   2735 };
   2736 struct _nir_image_atomic_umin_indices {
   2737    int _; /* exists to avoid empty initializers */
   2738    enum glsl_sampler_dim image_dim;
   2739    bool image_array;
   2740    enum pipe_format format;
   2741    enum gl_access_qualifier access;
   2742 };
   2743 struct _nir_image_atomic_xor_indices {
   2744    int _; /* exists to avoid empty initializers */
   2745    enum glsl_sampler_dim image_dim;
   2746    bool image_array;
   2747    enum pipe_format format;
   2748    enum gl_access_qualifier access;
   2749 };
   2750 struct _nir_image_deref_atomic_add_indices {
   2751    int _; /* exists to avoid empty initializers */
   2752    enum glsl_sampler_dim image_dim;
   2753    bool image_array;
   2754    enum pipe_format format;
   2755    enum gl_access_qualifier access;
   2756 };
   2757 struct _nir_image_deref_atomic_and_indices {
   2758    int _; /* exists to avoid empty initializers */
   2759    enum glsl_sampler_dim image_dim;
   2760    bool image_array;
   2761    enum pipe_format format;
   2762    enum gl_access_qualifier access;
   2763 };
   2764 struct _nir_image_deref_atomic_comp_swap_indices {
   2765    int _; /* exists to avoid empty initializers */
   2766    enum glsl_sampler_dim image_dim;
   2767    bool image_array;
   2768    enum pipe_format format;
   2769    enum gl_access_qualifier access;
   2770 };
   2771 struct _nir_image_deref_atomic_dec_wrap_indices {
   2772    int _; /* exists to avoid empty initializers */
   2773    enum glsl_sampler_dim image_dim;
   2774    bool image_array;
   2775    enum pipe_format format;
   2776    enum gl_access_qualifier access;
   2777 };
   2778 struct _nir_image_deref_atomic_exchange_indices {
   2779    int _; /* exists to avoid empty initializers */
   2780    enum glsl_sampler_dim image_dim;
   2781    bool image_array;
   2782    enum pipe_format format;
   2783    enum gl_access_qualifier access;
   2784 };
   2785 struct _nir_image_deref_atomic_fadd_indices {
   2786    int _; /* exists to avoid empty initializers */
   2787    enum glsl_sampler_dim image_dim;
   2788    bool image_array;
   2789    enum pipe_format format;
   2790    enum gl_access_qualifier access;
   2791 };
   2792 struct _nir_image_deref_atomic_fmax_indices {
   2793    int _; /* exists to avoid empty initializers */
   2794    enum glsl_sampler_dim image_dim;
   2795    bool image_array;
   2796    enum pipe_format format;
   2797    enum gl_access_qualifier access;
   2798 };
   2799 struct _nir_image_deref_atomic_fmin_indices {
   2800    int _; /* exists to avoid empty initializers */
   2801    enum glsl_sampler_dim image_dim;
   2802    bool image_array;
   2803    enum pipe_format format;
   2804    enum gl_access_qualifier access;
   2805 };
   2806 struct _nir_image_deref_atomic_imax_indices {
   2807    int _; /* exists to avoid empty initializers */
   2808    enum glsl_sampler_dim image_dim;
   2809    bool image_array;
   2810    enum pipe_format format;
   2811    enum gl_access_qualifier access;
   2812 };
   2813 struct _nir_image_deref_atomic_imin_indices {
   2814    int _; /* exists to avoid empty initializers */
   2815    enum glsl_sampler_dim image_dim;
   2816    bool image_array;
   2817    enum pipe_format format;
   2818    enum gl_access_qualifier access;
   2819 };
   2820 struct _nir_image_deref_atomic_inc_wrap_indices {
   2821    int _; /* exists to avoid empty initializers */
   2822    enum glsl_sampler_dim image_dim;
   2823    bool image_array;
   2824    enum pipe_format format;
   2825    enum gl_access_qualifier access;
   2826 };
   2827 struct _nir_image_deref_atomic_or_indices {
   2828    int _; /* exists to avoid empty initializers */
   2829    enum glsl_sampler_dim image_dim;
   2830    bool image_array;
   2831    enum pipe_format format;
   2832    enum gl_access_qualifier access;
   2833 };
   2834 struct _nir_image_deref_atomic_umax_indices {
   2835    int _; /* exists to avoid empty initializers */
   2836    enum glsl_sampler_dim image_dim;
   2837    bool image_array;
   2838    enum pipe_format format;
   2839    enum gl_access_qualifier access;
   2840 };
   2841 struct _nir_image_deref_atomic_umin_indices {
   2842    int _; /* exists to avoid empty initializers */
   2843    enum glsl_sampler_dim image_dim;
   2844    bool image_array;
   2845    enum pipe_format format;
   2846    enum gl_access_qualifier access;
   2847 };
   2848 struct _nir_image_deref_atomic_xor_indices {
   2849    int _; /* exists to avoid empty initializers */
   2850    enum glsl_sampler_dim image_dim;
   2851    bool image_array;
   2852    enum pipe_format format;
   2853    enum gl_access_qualifier access;
   2854 };
   2855 struct _nir_image_deref_format_indices {
   2856    int _; /* exists to avoid empty initializers */
   2857    enum glsl_sampler_dim image_dim;
   2858    bool image_array;
   2859    enum pipe_format format;
   2860    enum gl_access_qualifier access;
   2861 };
   2862 struct _nir_image_deref_load_indices {
   2863    int _; /* exists to avoid empty initializers */
   2864    enum glsl_sampler_dim image_dim;
   2865    bool image_array;
   2866    enum pipe_format format;
   2867    enum gl_access_qualifier access;
   2868    nir_alu_type dest_type;
   2869 };
   2870 struct _nir_image_deref_load_param_intel_indices {
   2871    int _; /* exists to avoid empty initializers */
   2872    int base;
   2873 };
   2874 struct _nir_image_deref_load_raw_intel_indices {
   2875    int _; /* exists to avoid empty initializers */
   2876    enum glsl_sampler_dim image_dim;
   2877    bool image_array;
   2878    enum pipe_format format;
   2879    enum gl_access_qualifier access;
   2880 };
   2881 struct _nir_image_deref_order_indices {
   2882    int _; /* exists to avoid empty initializers */
   2883    enum glsl_sampler_dim image_dim;
   2884    bool image_array;
   2885    enum pipe_format format;
   2886    enum gl_access_qualifier access;
   2887 };
   2888 struct _nir_image_deref_samples_indices {
   2889    int _; /* exists to avoid empty initializers */
   2890    enum glsl_sampler_dim image_dim;
   2891    bool image_array;
   2892    enum pipe_format format;
   2893    enum gl_access_qualifier access;
   2894 };
   2895 struct _nir_image_deref_size_indices {
   2896    int _; /* exists to avoid empty initializers */
   2897    enum glsl_sampler_dim image_dim;
   2898    bool image_array;
   2899    enum pipe_format format;
   2900    enum gl_access_qualifier access;
   2901 };
   2902 struct _nir_image_deref_sparse_load_indices {
   2903    int _; /* exists to avoid empty initializers */
   2904    enum glsl_sampler_dim image_dim;
   2905    bool image_array;
   2906    enum pipe_format format;
   2907    enum gl_access_qualifier access;
   2908    nir_alu_type dest_type;
   2909 };
   2910 struct _nir_image_deref_store_indices {
   2911    int _; /* exists to avoid empty initializers */
   2912    enum glsl_sampler_dim image_dim;
   2913    bool image_array;
   2914    enum pipe_format format;
   2915    enum gl_access_qualifier access;
   2916    nir_alu_type src_type;
   2917 };
   2918 struct _nir_image_deref_store_raw_intel_indices {
   2919    int _; /* exists to avoid empty initializers */
   2920    enum glsl_sampler_dim image_dim;
   2921    bool image_array;
   2922    enum pipe_format format;
   2923    enum gl_access_qualifier access;
   2924 };
   2925 struct _nir_image_format_indices {
   2926    int _; /* exists to avoid empty initializers */
   2927    enum glsl_sampler_dim image_dim;
   2928    bool image_array;
   2929    enum pipe_format format;
   2930    enum gl_access_qualifier access;
   2931 };
   2932 struct _nir_image_load_indices {
   2933    int _; /* exists to avoid empty initializers */
   2934    enum glsl_sampler_dim image_dim;
   2935    bool image_array;
   2936    enum pipe_format format;
   2937    enum gl_access_qualifier access;
   2938    nir_alu_type dest_type;
   2939 };
   2940 struct _nir_image_load_raw_intel_indices {
   2941    int _; /* exists to avoid empty initializers */
   2942    enum glsl_sampler_dim image_dim;
   2943    bool image_array;
   2944    enum pipe_format format;
   2945    enum gl_access_qualifier access;
   2946 };
   2947 struct _nir_image_order_indices {
   2948    int _; /* exists to avoid empty initializers */
   2949    enum glsl_sampler_dim image_dim;
   2950    bool image_array;
   2951    enum pipe_format format;
   2952    enum gl_access_qualifier access;
   2953 };
   2954 struct _nir_image_samples_indices {
   2955    int _; /* exists to avoid empty initializers */
   2956    enum glsl_sampler_dim image_dim;
   2957    bool image_array;
   2958    enum pipe_format format;
   2959    enum gl_access_qualifier access;
   2960 };
   2961 struct _nir_image_size_indices {
   2962    int _; /* exists to avoid empty initializers */
   2963    enum glsl_sampler_dim image_dim;
   2964    bool image_array;
   2965    enum pipe_format format;
   2966    enum gl_access_qualifier access;
   2967 };
   2968 struct _nir_image_sparse_load_indices {
   2969    int _; /* exists to avoid empty initializers */
   2970    enum glsl_sampler_dim image_dim;
   2971    bool image_array;
   2972    enum pipe_format format;
   2973    enum gl_access_qualifier access;
   2974    nir_alu_type dest_type;
   2975 };
   2976 struct _nir_image_store_indices {
   2977    int _; /* exists to avoid empty initializers */
   2978    enum glsl_sampler_dim image_dim;
   2979    bool image_array;
   2980    enum pipe_format format;
   2981    enum gl_access_qualifier access;
   2982    nir_alu_type src_type;
   2983 };
   2984 struct _nir_image_store_raw_intel_indices {
   2985    int _; /* exists to avoid empty initializers */
   2986    enum glsl_sampler_dim image_dim;
   2987    bool image_array;
   2988    enum pipe_format format;
   2989    enum gl_access_qualifier access;
   2990 };
   2991 struct _nir_inclusive_scan_indices {
   2992    int _; /* exists to avoid empty initializers */
   2993    unsigned reduction_op;
   2994 };
   2995 struct _nir_interp_deref_at_centroid_indices {
   2996    int _; /* exists to avoid empty initializers */
   2997 };
   2998 struct _nir_interp_deref_at_offset_indices {
   2999    int _; /* exists to avoid empty initializers */
   3000 };
   3001 struct _nir_interp_deref_at_sample_indices {
   3002    int _; /* exists to avoid empty initializers */
   3003 };
   3004 struct _nir_interp_deref_at_vertex_indices {
   3005    int _; /* exists to avoid empty initializers */
   3006 };
   3007 struct _nir_is_helper_invocation_indices {
   3008    int _; /* exists to avoid empty initializers */
   3009 };
   3010 struct _nir_is_sparse_texels_resident_indices {
   3011    int _; /* exists to avoid empty initializers */
   3012 };
   3013 struct _nir_lane_permute_16_amd_indices {
   3014    int _; /* exists to avoid empty initializers */
   3015 };
   3016 struct _nir_last_invocation_indices {
   3017    int _; /* exists to avoid empty initializers */
   3018 };
   3019 struct _nir_load_aa_line_width_indices {
   3020    int _; /* exists to avoid empty initializers */
   3021 };
   3022 struct _nir_load_back_face_agx_indices {
   3023    int _; /* exists to avoid empty initializers */
   3024 };
   3025 struct _nir_load_barycentric_at_offset_indices {
   3026    int _; /* exists to avoid empty initializers */
   3027    unsigned interp_mode;
   3028 };
   3029 struct _nir_load_barycentric_at_sample_indices {
   3030    int _; /* exists to avoid empty initializers */
   3031    unsigned interp_mode;
   3032 };
   3033 struct _nir_load_barycentric_centroid_indices {
   3034    int _; /* exists to avoid empty initializers */
   3035    unsigned interp_mode;
   3036 };
   3037 struct _nir_load_barycentric_model_indices {
   3038    int _; /* exists to avoid empty initializers */
   3039    unsigned interp_mode;
   3040 };
   3041 struct _nir_load_barycentric_pixel_indices {
   3042    int _; /* exists to avoid empty initializers */
   3043    unsigned interp_mode;
   3044 };
   3045 struct _nir_load_barycentric_sample_indices {
   3046    int _; /* exists to avoid empty initializers */
   3047    unsigned interp_mode;
   3048 };
   3049 struct _nir_load_base_global_invocation_id_indices {
   3050    int _; /* exists to avoid empty initializers */
   3051 };
   3052 struct _nir_load_base_instance_indices {
   3053    int _; /* exists to avoid empty initializers */
   3054 };
   3055 struct _nir_load_base_vertex_indices {
   3056    int _; /* exists to avoid empty initializers */
   3057 };
   3058 struct _nir_load_base_workgroup_id_indices {
   3059    int _; /* exists to avoid empty initializers */
   3060 };
   3061 struct _nir_load_blend_const_color_a_float_indices {
   3062    int _; /* exists to avoid empty initializers */
   3063 };
   3064 struct _nir_load_blend_const_color_aaaa8888_unorm_indices {
   3065    int _; /* exists to avoid empty initializers */
   3066 };
   3067 struct _nir_load_blend_const_color_b_float_indices {
   3068    int _; /* exists to avoid empty initializers */
   3069 };
   3070 struct _nir_load_blend_const_color_g_float_indices {
   3071    int _; /* exists to avoid empty initializers */
   3072 };
   3073 struct _nir_load_blend_const_color_r_float_indices {
   3074    int _; /* exists to avoid empty initializers */
   3075 };
   3076 struct _nir_load_blend_const_color_rgba_indices {
   3077    int _; /* exists to avoid empty initializers */
   3078 };
   3079 struct _nir_load_blend_const_color_rgba8888_unorm_indices {
   3080    int _; /* exists to avoid empty initializers */
   3081 };
   3082 struct _nir_load_btd_dss_id_intel_indices {
   3083    int _; /* exists to avoid empty initializers */
   3084 };
   3085 struct _nir_load_btd_global_arg_addr_intel_indices {
   3086    int _; /* exists to avoid empty initializers */
   3087 };
   3088 struct _nir_load_btd_local_arg_addr_intel_indices {
   3089    int _; /* exists to avoid empty initializers */
   3090 };
   3091 struct _nir_load_btd_resume_sbt_addr_intel_indices {
   3092    int _; /* exists to avoid empty initializers */
   3093 };
   3094 struct _nir_load_btd_stack_id_intel_indices {
   3095    int _; /* exists to avoid empty initializers */
   3096 };
   3097 struct _nir_load_buffer_amd_indices {
   3098    int _; /* exists to avoid empty initializers */
   3099    int base;
   3100    bool is_swizzled;
   3101    bool slc_amd;
   3102    nir_variable_mode memory_modes;
   3103 };
   3104 struct _nir_load_callable_sbt_addr_intel_indices {
   3105    int _; /* exists to avoid empty initializers */
   3106 };
   3107 struct _nir_load_callable_sbt_stride_intel_indices {
   3108    int _; /* exists to avoid empty initializers */
   3109 };
   3110 struct _nir_load_color0_indices {
   3111    int _; /* exists to avoid empty initializers */
   3112 };
   3113 struct _nir_load_color1_indices {
   3114    int _; /* exists to avoid empty initializers */
   3115 };
   3116 struct _nir_load_constant_indices {
   3117    int _; /* exists to avoid empty initializers */
   3118    int base;
   3119    unsigned range;
   3120    unsigned align_mul;
   3121    unsigned align_offset;
   3122 };
   3123 struct _nir_load_constant_base_ptr_indices {
   3124    int _; /* exists to avoid empty initializers */
   3125 };
   3126 struct _nir_load_cull_any_enabled_amd_indices {
   3127    int _; /* exists to avoid empty initializers */
   3128 };
   3129 struct _nir_load_cull_back_face_enabled_amd_indices {
   3130    int _; /* exists to avoid empty initializers */
   3131 };
   3132 struct _nir_load_cull_ccw_amd_indices {
   3133    int _; /* exists to avoid empty initializers */
   3134 };
   3135 struct _nir_load_cull_front_face_enabled_amd_indices {
   3136    int _; /* exists to avoid empty initializers */
   3137 };
   3138 struct _nir_load_cull_small_prim_precision_amd_indices {
   3139    int _; /* exists to avoid empty initializers */
   3140 };
   3141 struct _nir_load_cull_small_primitives_enabled_amd_indices {
   3142    int _; /* exists to avoid empty initializers */
   3143 };
   3144 struct _nir_load_deref_indices {
   3145    int _; /* exists to avoid empty initializers */
   3146    enum gl_access_qualifier access;
   3147 };
   3148 struct _nir_load_deref_block_intel_indices {
   3149    int _; /* exists to avoid empty initializers */
   3150    enum gl_access_qualifier access;
   3151 };
   3152 struct _nir_load_desc_set_address_intel_indices {
   3153    int _; /* exists to avoid empty initializers */
   3154 };
   3155 struct _nir_load_draw_id_indices {
   3156    int _; /* exists to avoid empty initializers */
   3157 };
   3158 struct _nir_load_fb_layers_v3d_indices {
   3159    int _; /* exists to avoid empty initializers */
   3160 };
   3161 struct _nir_load_first_vertex_indices {
   3162    int _; /* exists to avoid empty initializers */
   3163 };
   3164 struct _nir_load_frag_coord_indices {
   3165    int _; /* exists to avoid empty initializers */
   3166 };
   3167 struct _nir_load_frag_shading_rate_indices {
   3168    int _; /* exists to avoid empty initializers */
   3169 };
   3170 struct _nir_load_front_face_indices {
   3171    int _; /* exists to avoid empty initializers */
   3172 };
   3173 struct _nir_load_fs_input_interp_deltas_indices {
   3174    int _; /* exists to avoid empty initializers */
   3175    int base;
   3176    unsigned component;
   3177    struct nir_io_semantics io_semantics;
   3178 };
   3179 struct _nir_load_global_indices {
   3180    int _; /* exists to avoid empty initializers */
   3181    enum gl_access_qualifier access;
   3182    unsigned align_mul;
   3183    unsigned align_offset;
   3184 };
   3185 struct _nir_load_global_block_intel_indices {
   3186    int _; /* exists to avoid empty initializers */
   3187    enum gl_access_qualifier access;
   3188    unsigned align_mul;
   3189    unsigned align_offset;
   3190 };
   3191 struct _nir_load_global_const_block_intel_indices {
   3192    int _; /* exists to avoid empty initializers */
   3193    int base;
   3194 };
   3195 struct _nir_load_global_constant_indices {
   3196    int _; /* exists to avoid empty initializers */
   3197    enum gl_access_qualifier access;
   3198    unsigned align_mul;
   3199    unsigned align_offset;
   3200 };
   3201 struct _nir_load_global_constant_bounded_indices {
   3202    int _; /* exists to avoid empty initializers */
   3203    enum gl_access_qualifier access;
   3204    unsigned align_mul;
   3205    unsigned align_offset;
   3206 };
   3207 struct _nir_load_global_constant_offset_indices {
   3208    int _; /* exists to avoid empty initializers */
   3209    enum gl_access_qualifier access;
   3210    unsigned align_mul;
   3211    unsigned align_offset;
   3212 };
   3213 struct _nir_load_global_invocation_id_indices {
   3214    int _; /* exists to avoid empty initializers */
   3215 };
   3216 struct _nir_load_global_invocation_id_zero_base_indices {
   3217    int _; /* exists to avoid empty initializers */
   3218 };
   3219 struct _nir_load_global_invocation_index_indices {
   3220    int _; /* exists to avoid empty initializers */
   3221 };
   3222 struct _nir_load_global_ir3_indices {
   3223    int _; /* exists to avoid empty initializers */
   3224    enum gl_access_qualifier access;
   3225    unsigned align_mul;
   3226    unsigned align_offset;
   3227 };
   3228 struct _nir_load_gs_header_ir3_indices {
   3229    int _; /* exists to avoid empty initializers */
   3230 };
   3231 struct _nir_load_gs_vertex_offset_amd_indices {
   3232    int _; /* exists to avoid empty initializers */
   3233    int base;
   3234 };
   3235 struct _nir_load_helper_invocation_indices {
   3236    int _; /* exists to avoid empty initializers */
   3237 };
   3238 struct _nir_load_hs_patch_stride_ir3_indices {
   3239    int _; /* exists to avoid empty initializers */
   3240 };
   3241 struct _nir_load_initial_edgeflags_amd_indices {
   3242    int _; /* exists to avoid empty initializers */
   3243 };
   3244 struct _nir_load_input_indices {
   3245    int _; /* exists to avoid empty initializers */
   3246    int base;
   3247    unsigned component;
   3248    nir_alu_type dest_type;
   3249    struct nir_io_semantics io_semantics;
   3250 };
   3251 struct _nir_load_input_vertex_indices {
   3252    int _; /* exists to avoid empty initializers */
   3253    int base;
   3254    unsigned component;
   3255    nir_alu_type dest_type;
   3256    struct nir_io_semantics io_semantics;
   3257 };
   3258 struct _nir_load_instance_id_indices {
   3259    int _; /* exists to avoid empty initializers */
   3260 };
   3261 struct _nir_load_interpolated_input_indices {
   3262    int _; /* exists to avoid empty initializers */
   3263    int base;
   3264    unsigned component;
   3265    nir_alu_type dest_type;
   3266    struct nir_io_semantics io_semantics;
   3267 };
   3268 struct _nir_load_intersection_opaque_amd_indices {
   3269    int _; /* exists to avoid empty initializers */
   3270 };
   3271 struct _nir_load_invocation_id_indices {
   3272    int _; /* exists to avoid empty initializers */
   3273 };
   3274 struct _nir_load_is_indexed_draw_indices {
   3275    int _; /* exists to avoid empty initializers */
   3276 };
   3277 struct _nir_load_kernel_input_indices {
   3278    int _; /* exists to avoid empty initializers */
   3279    int base;
   3280    unsigned range;
   3281    unsigned align_mul;
   3282    unsigned align_offset;
   3283 };
   3284 struct _nir_load_layer_id_indices {
   3285    int _; /* exists to avoid empty initializers */
   3286 };
   3287 struct _nir_load_leaf_opaque_intel_indices {
   3288    int _; /* exists to avoid empty initializers */
   3289 };
   3290 struct _nir_load_leaf_procedural_intel_indices {
   3291    int _; /* exists to avoid empty initializers */
   3292 };
   3293 struct _nir_load_line_coord_indices {
   3294    int _; /* exists to avoid empty initializers */
   3295 };
   3296 struct _nir_load_line_width_indices {
   3297    int _; /* exists to avoid empty initializers */
   3298 };
   3299 struct _nir_load_local_invocation_id_indices {
   3300    int _; /* exists to avoid empty initializers */
   3301 };
   3302 struct _nir_load_local_invocation_index_indices {
   3303    int _; /* exists to avoid empty initializers */
   3304 };
   3305 struct _nir_load_local_shared_r600_indices {
   3306    int _; /* exists to avoid empty initializers */
   3307 };
   3308 struct _nir_load_num_subgroups_indices {
   3309    int _; /* exists to avoid empty initializers */
   3310 };
   3311 struct _nir_load_num_workgroups_indices {
   3312    int _; /* exists to avoid empty initializers */
   3313 };
   3314 struct _nir_load_output_indices {
   3315    int _; /* exists to avoid empty initializers */
   3316    int base;
   3317    unsigned component;
   3318    nir_alu_type dest_type;
   3319    struct nir_io_semantics io_semantics;
   3320 };
   3321 struct _nir_load_packed_passthrough_primitive_amd_indices {
   3322    int _; /* exists to avoid empty initializers */
   3323 };
   3324 struct _nir_load_param_indices {
   3325    int _; /* exists to avoid empty initializers */
   3326    unsigned param_idx;
   3327 };
   3328 struct _nir_load_patch_vertices_in_indices {
   3329    int _; /* exists to avoid empty initializers */
   3330 };
   3331 struct _nir_load_per_primitive_output_indices {
   3332    int _; /* exists to avoid empty initializers */
   3333    int base;
   3334    unsigned component;
   3335    nir_alu_type dest_type;
   3336    struct nir_io_semantics io_semantics;
   3337 };
   3338 struct _nir_load_per_vertex_input_indices {
   3339    int _; /* exists to avoid empty initializers */
   3340    int base;
   3341    unsigned component;
   3342    nir_alu_type dest_type;
   3343    struct nir_io_semantics io_semantics;
   3344 };
   3345 struct _nir_load_per_vertex_output_indices {
   3346    int _; /* exists to avoid empty initializers */
   3347    int base;
   3348    unsigned component;
   3349    nir_alu_type dest_type;
   3350    struct nir_io_semantics io_semantics;
   3351 };
   3352 struct _nir_load_point_coord_indices {
   3353    int _; /* exists to avoid empty initializers */
   3354 };
   3355 struct _nir_load_primitive_id_indices {
   3356    int _; /* exists to avoid empty initializers */
   3357 };
   3358 struct _nir_load_primitive_location_ir3_indices {
   3359    int _; /* exists to avoid empty initializers */
   3360    unsigned driver_location;
   3361 };
   3362 struct _nir_load_printf_buffer_address_indices {
   3363    int _; /* exists to avoid empty initializers */
   3364 };
   3365 struct _nir_load_ptr_dxil_indices {
   3366    int _; /* exists to avoid empty initializers */
   3367 };
   3368 struct _nir_load_push_constant_indices {
   3369    int _; /* exists to avoid empty initializers */
   3370    int base;
   3371    unsigned range;
   3372 };
   3373 struct _nir_load_raw_output_pan_indices {
   3374    int _; /* exists to avoid empty initializers */
   3375    int base;
   3376 };
   3377 struct _nir_load_ray_base_mem_addr_intel_indices {
   3378    int _; /* exists to avoid empty initializers */
   3379 };
   3380 struct _nir_load_ray_flags_indices {
   3381    int _; /* exists to avoid empty initializers */
   3382 };
   3383 struct _nir_load_ray_geometry_index_indices {
   3384    int _; /* exists to avoid empty initializers */
   3385 };
   3386 struct _nir_load_ray_hit_kind_indices {
   3387    int _; /* exists to avoid empty initializers */
   3388 };
   3389 struct _nir_load_ray_hit_sbt_addr_intel_indices {
   3390    int _; /* exists to avoid empty initializers */
   3391 };
   3392 struct _nir_load_ray_hit_sbt_stride_intel_indices {
   3393    int _; /* exists to avoid empty initializers */
   3394 };
   3395 struct _nir_load_ray_hw_stack_size_intel_indices {
   3396    int _; /* exists to avoid empty initializers */
   3397 };
   3398 struct _nir_load_ray_instance_custom_index_indices {
   3399    int _; /* exists to avoid empty initializers */
   3400 };
   3401 struct _nir_load_ray_launch_id_indices {
   3402    int _; /* exists to avoid empty initializers */
   3403 };
   3404 struct _nir_load_ray_launch_size_indices {
   3405    int _; /* exists to avoid empty initializers */
   3406 };
   3407 struct _nir_load_ray_miss_sbt_addr_intel_indices {
   3408    int _; /* exists to avoid empty initializers */
   3409 };
   3410 struct _nir_load_ray_miss_sbt_stride_intel_indices {
   3411    int _; /* exists to avoid empty initializers */
   3412 };
   3413 struct _nir_load_ray_num_dss_rt_stacks_intel_indices {
   3414    int _; /* exists to avoid empty initializers */
   3415 };
   3416 struct _nir_load_ray_object_direction_indices {
   3417    int _; /* exists to avoid empty initializers */
   3418 };
   3419 struct _nir_load_ray_object_origin_indices {
   3420    int _; /* exists to avoid empty initializers */
   3421 };
   3422 struct _nir_load_ray_object_to_world_indices {
   3423    int _; /* exists to avoid empty initializers */
   3424    unsigned column;
   3425 };
   3426 struct _nir_load_ray_sw_stack_size_intel_indices {
   3427    int _; /* exists to avoid empty initializers */
   3428 };
   3429 struct _nir_load_ray_t_max_indices {
   3430    int _; /* exists to avoid empty initializers */
   3431 };
   3432 struct _nir_load_ray_t_min_indices {
   3433    int _; /* exists to avoid empty initializers */
   3434 };
   3435 struct _nir_load_ray_world_direction_indices {
   3436    int _; /* exists to avoid empty initializers */
   3437 };
   3438 struct _nir_load_ray_world_origin_indices {
   3439    int _; /* exists to avoid empty initializers */
   3440 };
   3441 struct _nir_load_ray_world_to_object_indices {
   3442    int _; /* exists to avoid empty initializers */
   3443    unsigned column;
   3444 };
   3445 struct _nir_load_rel_patch_id_ir3_indices {
   3446    int _; /* exists to avoid empty initializers */
   3447 };
   3448 struct _nir_load_reloc_const_intel_indices {
   3449    int _; /* exists to avoid empty initializers */
   3450    unsigned param_idx;
   3451 };
   3452 struct _nir_load_ring_es2gs_offset_amd_indices {
   3453    int _; /* exists to avoid empty initializers */
   3454 };
   3455 struct _nir_load_ring_esgs_amd_indices {
   3456    int _; /* exists to avoid empty initializers */
   3457 };
   3458 struct _nir_load_ring_tess_factors_amd_indices {
   3459    int _; /* exists to avoid empty initializers */
   3460 };
   3461 struct _nir_load_ring_tess_factors_offset_amd_indices {
   3462    int _; /* exists to avoid empty initializers */
   3463 };
   3464 struct _nir_load_ring_tess_offchip_amd_indices {
   3465    int _; /* exists to avoid empty initializers */
   3466 };
   3467 struct _nir_load_ring_tess_offchip_offset_amd_indices {
   3468    int _; /* exists to avoid empty initializers */
   3469 };
   3470 struct _nir_load_rt_arg_scratch_offset_amd_indices {
   3471    int _; /* exists to avoid empty initializers */
   3472 };
   3473 struct _nir_load_sample_id_indices {
   3474    int _; /* exists to avoid empty initializers */
   3475 };
   3476 struct _nir_load_sample_id_no_per_sample_indices {
   3477    int _; /* exists to avoid empty initializers */
   3478 };
   3479 struct _nir_load_sample_mask_in_indices {
   3480    int _; /* exists to avoid empty initializers */
   3481 };
   3482 struct _nir_load_sample_pos_indices {
   3483    int _; /* exists to avoid empty initializers */
   3484 };
   3485 struct _nir_load_sample_pos_from_id_indices {
   3486    int _; /* exists to avoid empty initializers */
   3487 };
   3488 struct _nir_load_sample_positions_pan_indices {
   3489    int _; /* exists to avoid empty initializers */
   3490 };
   3491 struct _nir_load_sampler_lod_parameters_pan_indices {
   3492    int _; /* exists to avoid empty initializers */
   3493 };
   3494 struct _nir_load_sbt_amd_indices {
   3495    int _; /* exists to avoid empty initializers */
   3496    unsigned binding;
   3497 };
   3498 struct _nir_load_scratch_indices {
   3499    int _; /* exists to avoid empty initializers */
   3500    unsigned align_mul;
   3501    unsigned align_offset;
   3502 };
   3503 struct _nir_load_scratch_base_ptr_indices {
   3504    int _; /* exists to avoid empty initializers */
   3505    int base;
   3506 };
   3507 struct _nir_load_scratch_dxil_indices {
   3508    int _; /* exists to avoid empty initializers */
   3509 };
   3510 struct _nir_load_shader_query_enabled_amd_indices {
   3511    int _; /* exists to avoid empty initializers */
   3512 };
   3513 struct _nir_load_shader_record_ptr_indices {
   3514    int _; /* exists to avoid empty initializers */
   3515 };
   3516 struct _nir_load_shared_indices {
   3517    int _; /* exists to avoid empty initializers */
   3518    int base;
   3519    unsigned align_mul;
   3520    unsigned align_offset;
   3521 };
   3522 struct _nir_load_shared_base_ptr_indices {
   3523    int _; /* exists to avoid empty initializers */
   3524 };
   3525 struct _nir_load_shared_block_intel_indices {
   3526    int _; /* exists to avoid empty initializers */
   3527    int base;
   3528    unsigned align_mul;
   3529    unsigned align_offset;
   3530 };
   3531 struct _nir_load_shared_dxil_indices {
   3532    int _; /* exists to avoid empty initializers */
   3533 };
   3534 struct _nir_load_shared_ir3_indices {
   3535    int _; /* exists to avoid empty initializers */
   3536    int base;
   3537    unsigned align_mul;
   3538    unsigned align_offset;
   3539 };
   3540 struct _nir_load_simd_width_intel_indices {
   3541    int _; /* exists to avoid empty initializers */
   3542 };
   3543 struct _nir_load_size_ir3_indices {
   3544    int _; /* exists to avoid empty initializers */
   3545 };
   3546 struct _nir_load_ssbo_indices {
   3547    int _; /* exists to avoid empty initializers */
   3548    enum gl_access_qualifier access;
   3549    unsigned align_mul;
   3550    unsigned align_offset;
   3551 };
   3552 struct _nir_load_ssbo_address_indices {
   3553    int _; /* exists to avoid empty initializers */
   3554 };
   3555 struct _nir_load_ssbo_block_intel_indices {
   3556    int _; /* exists to avoid empty initializers */
   3557    enum gl_access_qualifier access;
   3558    unsigned align_mul;
   3559    unsigned align_offset;
   3560 };
   3561 struct _nir_load_ssbo_ir3_indices {
   3562    int _; /* exists to avoid empty initializers */
   3563    enum gl_access_qualifier access;
   3564    unsigned align_mul;
   3565    unsigned align_offset;
   3566 };
   3567 struct _nir_load_subgroup_eq_mask_indices {
   3568    int _; /* exists to avoid empty initializers */
   3569 };
   3570 struct _nir_load_subgroup_ge_mask_indices {
   3571    int _; /* exists to avoid empty initializers */
   3572 };
   3573 struct _nir_load_subgroup_gt_mask_indices {
   3574    int _; /* exists to avoid empty initializers */
   3575 };
   3576 struct _nir_load_subgroup_id_indices {
   3577    int _; /* exists to avoid empty initializers */
   3578 };
   3579 struct _nir_load_subgroup_id_shift_ir3_indices {
   3580    int _; /* exists to avoid empty initializers */
   3581 };
   3582 struct _nir_load_subgroup_invocation_indices {
   3583    int _; /* exists to avoid empty initializers */
   3584 };
   3585 struct _nir_load_subgroup_le_mask_indices {
   3586    int _; /* exists to avoid empty initializers */
   3587 };
   3588 struct _nir_load_subgroup_lt_mask_indices {
   3589    int _; /* exists to avoid empty initializers */
   3590 };
   3591 struct _nir_load_subgroup_size_indices {
   3592    int _; /* exists to avoid empty initializers */
   3593 };
   3594 struct _nir_load_tcs_header_ir3_indices {
   3595    int _; /* exists to avoid empty initializers */
   3596 };
   3597 struct _nir_load_tcs_in_param_base_r600_indices {
   3598    int _; /* exists to avoid empty initializers */
   3599 };
   3600 struct _nir_load_tcs_num_patches_amd_indices {
   3601    int _; /* exists to avoid empty initializers */
   3602 };
   3603 struct _nir_load_tcs_out_param_base_r600_indices {
   3604    int _; /* exists to avoid empty initializers */
   3605 };
   3606 struct _nir_load_tcs_rel_patch_id_r600_indices {
   3607    int _; /* exists to avoid empty initializers */
   3608 };
   3609 struct _nir_load_tcs_tess_factor_base_r600_indices {
   3610    int _; /* exists to avoid empty initializers */
   3611 };
   3612 struct _nir_load_tess_coord_indices {
   3613    int _; /* exists to avoid empty initializers */
   3614 };
   3615 struct _nir_load_tess_coord_r600_indices {
   3616    int _; /* exists to avoid empty initializers */
   3617 };
   3618 struct _nir_load_tess_factor_base_ir3_indices {
   3619    int _; /* exists to avoid empty initializers */
   3620 };
   3621 struct _nir_load_tess_level_inner_indices {
   3622    int _; /* exists to avoid empty initializers */
   3623 };
   3624 struct _nir_load_tess_level_inner_default_indices {
   3625    int _; /* exists to avoid empty initializers */
   3626 };
   3627 struct _nir_load_tess_level_outer_indices {
   3628    int _; /* exists to avoid empty initializers */
   3629 };
   3630 struct _nir_load_tess_level_outer_default_indices {
   3631    int _; /* exists to avoid empty initializers */
   3632 };
   3633 struct _nir_load_tess_param_base_ir3_indices {
   3634    int _; /* exists to avoid empty initializers */
   3635 };
   3636 struct _nir_load_tess_rel_patch_id_amd_indices {
   3637    int _; /* exists to avoid empty initializers */
   3638 };
   3639 struct _nir_load_texture_rect_scaling_indices {
   3640    int _; /* exists to avoid empty initializers */
   3641 };
   3642 struct _nir_load_tlb_color_v3d_indices {
   3643    int _; /* exists to avoid empty initializers */
   3644    int base;
   3645    unsigned component;
   3646 };
   3647 struct _nir_load_ubo_indices {
   3648    int _; /* exists to avoid empty initializers */
   3649    enum gl_access_qualifier access;
   3650    unsigned align_mul;
   3651    unsigned align_offset;
   3652    unsigned range_base;
   3653    unsigned range;
   3654 };
   3655 struct _nir_load_ubo_dxil_indices {
   3656    int _; /* exists to avoid empty initializers */
   3657 };
   3658 struct _nir_load_ubo_vec4_indices {
   3659    int _; /* exists to avoid empty initializers */
   3660    enum gl_access_qualifier access;
   3661    unsigned component;
   3662 };
   3663 struct _nir_load_uniform_indices {
   3664    int _; /* exists to avoid empty initializers */
   3665    int base;
   3666    unsigned range;
   3667    nir_alu_type dest_type;
   3668 };
   3669 struct _nir_load_user_clip_plane_indices {
   3670    int _; /* exists to avoid empty initializers */
   3671    unsigned ucp_id;
   3672 };
   3673 struct _nir_load_user_data_amd_indices {
   3674    int _; /* exists to avoid empty initializers */
   3675 };
   3676 struct _nir_load_vertex_id_indices {
   3677    int _; /* exists to avoid empty initializers */
   3678 };
   3679 struct _nir_load_vertex_id_zero_base_indices {
   3680    int _; /* exists to avoid empty initializers */
   3681 };
   3682 struct _nir_load_view_index_indices {
   3683    int _; /* exists to avoid empty initializers */
   3684 };
   3685 struct _nir_load_viewport_offset_indices {
   3686    int _; /* exists to avoid empty initializers */
   3687 };
   3688 struct _nir_load_viewport_scale_indices {
   3689    int _; /* exists to avoid empty initializers */
   3690 };
   3691 struct _nir_load_viewport_x_offset_indices {
   3692    int _; /* exists to avoid empty initializers */
   3693 };
   3694 struct _nir_load_viewport_x_scale_indices {
   3695    int _; /* exists to avoid empty initializers */
   3696 };
   3697 struct _nir_load_viewport_y_offset_indices {
   3698    int _; /* exists to avoid empty initializers */
   3699 };
   3700 struct _nir_load_viewport_y_scale_indices {
   3701    int _; /* exists to avoid empty initializers */
   3702 };
   3703 struct _nir_load_viewport_z_offset_indices {
   3704    int _; /* exists to avoid empty initializers */
   3705 };
   3706 struct _nir_load_viewport_z_scale_indices {
   3707    int _; /* exists to avoid empty initializers */
   3708 };
   3709 struct _nir_load_vs_primitive_stride_ir3_indices {
   3710    int _; /* exists to avoid empty initializers */
   3711 };
   3712 struct _nir_load_vs_vertex_stride_ir3_indices {
   3713    int _; /* exists to avoid empty initializers */
   3714 };
   3715 struct _nir_load_vulkan_descriptor_indices {
   3716    int _; /* exists to avoid empty initializers */
   3717    unsigned desc_type;
   3718 };
   3719 struct _nir_load_work_dim_indices {
   3720    int _; /* exists to avoid empty initializers */
   3721 };
   3722 struct _nir_load_workgroup_id_indices {
   3723    int _; /* exists to avoid empty initializers */
   3724 };
   3725 struct _nir_load_workgroup_id_zero_base_indices {
   3726    int _; /* exists to avoid empty initializers */
   3727 };
   3728 struct _nir_load_workgroup_num_input_primitives_amd_indices {
   3729    int _; /* exists to avoid empty initializers */
   3730 };
   3731 struct _nir_load_workgroup_num_input_vertices_amd_indices {
   3732    int _; /* exists to avoid empty initializers */
   3733 };
   3734 struct _nir_load_workgroup_size_indices {
   3735    int _; /* exists to avoid empty initializers */
   3736 };
   3737 struct _nir_masked_swizzle_amd_indices {
   3738    int _; /* exists to avoid empty initializers */
   3739    unsigned swizzle_mask;
   3740 };
   3741 struct _nir_mbcnt_amd_indices {
   3742    int _; /* exists to avoid empty initializers */
   3743 };
   3744 struct _nir_memcpy_deref_indices {
   3745    int _; /* exists to avoid empty initializers */
   3746    enum gl_access_qualifier dst_access;
   3747    enum gl_access_qualifier src_access;
   3748 };
   3749 struct _nir_memory_barrier_indices {
   3750    int _; /* exists to avoid empty initializers */
   3751 };
   3752 struct _nir_memory_barrier_atomic_counter_indices {
   3753    int _; /* exists to avoid empty initializers */
   3754 };
   3755 struct _nir_memory_barrier_buffer_indices {
   3756    int _; /* exists to avoid empty initializers */
   3757 };
   3758 struct _nir_memory_barrier_image_indices {
   3759    int _; /* exists to avoid empty initializers */
   3760 };
   3761 struct _nir_memory_barrier_shared_indices {
   3762    int _; /* exists to avoid empty initializers */
   3763 };
   3764 struct _nir_memory_barrier_tcs_patch_indices {
   3765    int _; /* exists to avoid empty initializers */
   3766 };
   3767 struct _nir_nop_indices {
   3768    int _; /* exists to avoid empty initializers */
   3769 };
   3770 struct _nir_overwrite_tes_arguments_amd_indices {
   3771    int _; /* exists to avoid empty initializers */
   3772 };
   3773 struct _nir_overwrite_vs_arguments_amd_indices {
   3774    int _; /* exists to avoid empty initializers */
   3775 };
   3776 struct _nir_printf_indices {
   3777    int _; /* exists to avoid empty initializers */
   3778 };
   3779 struct _nir_quad_broadcast_indices {
   3780    int _; /* exists to avoid empty initializers */
   3781 };
   3782 struct _nir_quad_swap_diagonal_indices {
   3783    int _; /* exists to avoid empty initializers */
   3784 };
   3785 struct _nir_quad_swap_horizontal_indices {
   3786    int _; /* exists to avoid empty initializers */
   3787 };
   3788 struct _nir_quad_swap_vertical_indices {
   3789    int _; /* exists to avoid empty initializers */
   3790 };
   3791 struct _nir_quad_swizzle_amd_indices {
   3792    int _; /* exists to avoid empty initializers */
   3793    unsigned swizzle_mask;
   3794 };
   3795 struct _nir_read_first_invocation_indices {
   3796    int _; /* exists to avoid empty initializers */
   3797 };
   3798 struct _nir_read_invocation_indices {
   3799    int _; /* exists to avoid empty initializers */
   3800 };
   3801 struct _nir_read_invocation_cond_ir3_indices {
   3802    int _; /* exists to avoid empty initializers */
   3803 };
   3804 struct _nir_reduce_indices {
   3805    int _; /* exists to avoid empty initializers */
   3806    unsigned reduction_op;
   3807    unsigned cluster_size;
   3808 };
   3809 struct _nir_report_ray_intersection_indices {
   3810    int _; /* exists to avoid empty initializers */
   3811 };
   3812 struct _nir_rt_execute_callable_indices {
   3813    int _; /* exists to avoid empty initializers */
   3814    unsigned call_idx;
   3815    unsigned stack_size;
   3816 };
   3817 struct _nir_rt_resume_indices {
   3818    int _; /* exists to avoid empty initializers */
   3819    unsigned call_idx;
   3820    unsigned stack_size;
   3821 };
   3822 struct _nir_rt_return_amd_indices {
   3823    int _; /* exists to avoid empty initializers */
   3824 };
   3825 struct _nir_rt_trace_ray_indices {
   3826    int _; /* exists to avoid empty initializers */
   3827    unsigned call_idx;
   3828    unsigned stack_size;
   3829 };
   3830 struct _nir_scoped_barrier_indices {
   3831    int _; /* exists to avoid empty initializers */
   3832    nir_scope execution_scope;
   3833    nir_scope memory_scope;
   3834    nir_memory_semantics memory_semantics;
   3835    nir_variable_mode memory_modes;
   3836 };
   3837 struct _nir_set_vertex_and_primitive_count_indices {
   3838    int _; /* exists to avoid empty initializers */
   3839    unsigned stream_id;
   3840 };
   3841 struct _nir_shader_clock_indices {
   3842    int _; /* exists to avoid empty initializers */
   3843    nir_scope memory_scope;
   3844 };
   3845 struct _nir_shared_atomic_add_indices {
   3846    int _; /* exists to avoid empty initializers */
   3847    int base;
   3848 };
   3849 struct _nir_shared_atomic_add_dxil_indices {
   3850    int _; /* exists to avoid empty initializers */
   3851 };
   3852 struct _nir_shared_atomic_and_indices {
   3853    int _; /* exists to avoid empty initializers */
   3854    int base;
   3855 };
   3856 struct _nir_shared_atomic_and_dxil_indices {
   3857    int _; /* exists to avoid empty initializers */
   3858 };
   3859 struct _nir_shared_atomic_comp_swap_indices {
   3860    int _; /* exists to avoid empty initializers */
   3861    int base;
   3862 };
   3863 struct _nir_shared_atomic_comp_swap_dxil_indices {
   3864    int _; /* exists to avoid empty initializers */
   3865 };
   3866 struct _nir_shared_atomic_exchange_indices {
   3867    int _; /* exists to avoid empty initializers */
   3868    int base;
   3869 };
   3870 struct _nir_shared_atomic_exchange_dxil_indices {
   3871    int _; /* exists to avoid empty initializers */
   3872 };
   3873 struct _nir_shared_atomic_fadd_indices {
   3874    int _; /* exists to avoid empty initializers */
   3875    int base;
   3876 };
   3877 struct _nir_shared_atomic_fcomp_swap_indices {
   3878    int _; /* exists to avoid empty initializers */
   3879    int base;
   3880 };
   3881 struct _nir_shared_atomic_fmax_indices {
   3882    int _; /* exists to avoid empty initializers */
   3883    int base;
   3884 };
   3885 struct _nir_shared_atomic_fmin_indices {
   3886    int _; /* exists to avoid empty initializers */
   3887    int base;
   3888 };
   3889 struct _nir_shared_atomic_imax_indices {
   3890    int _; /* exists to avoid empty initializers */
   3891    int base;
   3892 };
   3893 struct _nir_shared_atomic_imax_dxil_indices {
   3894    int _; /* exists to avoid empty initializers */
   3895 };
   3896 struct _nir_shared_atomic_imin_indices {
   3897    int _; /* exists to avoid empty initializers */
   3898    int base;
   3899 };
   3900 struct _nir_shared_atomic_imin_dxil_indices {
   3901    int _; /* exists to avoid empty initializers */
   3902 };
   3903 struct _nir_shared_atomic_or_indices {
   3904    int _; /* exists to avoid empty initializers */
   3905    int base;
   3906 };
   3907 struct _nir_shared_atomic_or_dxil_indices {
   3908    int _; /* exists to avoid empty initializers */
   3909 };
   3910 struct _nir_shared_atomic_umax_indices {
   3911    int _; /* exists to avoid empty initializers */
   3912    int base;
   3913 };
   3914 struct _nir_shared_atomic_umax_dxil_indices {
   3915    int _; /* exists to avoid empty initializers */
   3916 };
   3917 struct _nir_shared_atomic_umin_indices {
   3918    int _; /* exists to avoid empty initializers */
   3919    int base;
   3920 };
   3921 struct _nir_shared_atomic_umin_dxil_indices {
   3922    int _; /* exists to avoid empty initializers */
   3923 };
   3924 struct _nir_shared_atomic_xor_indices {
   3925    int _; /* exists to avoid empty initializers */
   3926    int base;
   3927 };
   3928 struct _nir_shared_atomic_xor_dxil_indices {
   3929    int _; /* exists to avoid empty initializers */
   3930 };
   3931 struct _nir_shuffle_indices {
   3932    int _; /* exists to avoid empty initializers */
   3933 };
   3934 struct _nir_shuffle_down_indices {
   3935    int _; /* exists to avoid empty initializers */
   3936 };
   3937 struct _nir_shuffle_up_indices {
   3938    int _; /* exists to avoid empty initializers */
   3939 };
   3940 struct _nir_shuffle_xor_indices {
   3941    int _; /* exists to avoid empty initializers */
   3942 };
   3943 struct _nir_sparse_residency_code_and_indices {
   3944    int _; /* exists to avoid empty initializers */
   3945 };
   3946 struct _nir_ssbo_atomic_add_indices {
   3947    int _; /* exists to avoid empty initializers */
   3948    enum gl_access_qualifier access;
   3949 };
   3950 struct _nir_ssbo_atomic_add_ir3_indices {
   3951    int _; /* exists to avoid empty initializers */
   3952    enum gl_access_qualifier access;
   3953 };
   3954 struct _nir_ssbo_atomic_and_indices {
   3955    int _; /* exists to avoid empty initializers */
   3956    enum gl_access_qualifier access;
   3957 };
   3958 struct _nir_ssbo_atomic_and_ir3_indices {
   3959    int _; /* exists to avoid empty initializers */
   3960    enum gl_access_qualifier access;
   3961 };
   3962 struct _nir_ssbo_atomic_comp_swap_indices {
   3963    int _; /* exists to avoid empty initializers */
   3964    enum gl_access_qualifier access;
   3965 };
   3966 struct _nir_ssbo_atomic_comp_swap_ir3_indices {
   3967    int _; /* exists to avoid empty initializers */
   3968    enum gl_access_qualifier access;
   3969 };
   3970 struct _nir_ssbo_atomic_exchange_indices {
   3971    int _; /* exists to avoid empty initializers */
   3972    enum gl_access_qualifier access;
   3973 };
   3974 struct _nir_ssbo_atomic_exchange_ir3_indices {
   3975    int _; /* exists to avoid empty initializers */
   3976    enum gl_access_qualifier access;
   3977 };
   3978 struct _nir_ssbo_atomic_fadd_indices {
   3979    int _; /* exists to avoid empty initializers */
   3980    enum gl_access_qualifier access;
   3981 };
   3982 struct _nir_ssbo_atomic_fcomp_swap_indices {
   3983    int _; /* exists to avoid empty initializers */
   3984    enum gl_access_qualifier access;
   3985 };
   3986 struct _nir_ssbo_atomic_fmax_indices {
   3987    int _; /* exists to avoid empty initializers */
   3988    enum gl_access_qualifier access;
   3989 };
   3990 struct _nir_ssbo_atomic_fmin_indices {
   3991    int _; /* exists to avoid empty initializers */
   3992    enum gl_access_qualifier access;
   3993 };
   3994 struct _nir_ssbo_atomic_imax_indices {
   3995    int _; /* exists to avoid empty initializers */
   3996    enum gl_access_qualifier access;
   3997 };
   3998 struct _nir_ssbo_atomic_imax_ir3_indices {
   3999    int _; /* exists to avoid empty initializers */
   4000    enum gl_access_qualifier access;
   4001 };
   4002 struct _nir_ssbo_atomic_imin_indices {
   4003    int _; /* exists to avoid empty initializers */
   4004    enum gl_access_qualifier access;
   4005 };
   4006 struct _nir_ssbo_atomic_imin_ir3_indices {
   4007    int _; /* exists to avoid empty initializers */
   4008    enum gl_access_qualifier access;
   4009 };
   4010 struct _nir_ssbo_atomic_or_indices {
   4011    int _; /* exists to avoid empty initializers */
   4012    enum gl_access_qualifier access;
   4013 };
   4014 struct _nir_ssbo_atomic_or_ir3_indices {
   4015    int _; /* exists to avoid empty initializers */
   4016    enum gl_access_qualifier access;
   4017 };
   4018 struct _nir_ssbo_atomic_umax_indices {
   4019    int _; /* exists to avoid empty initializers */
   4020    enum gl_access_qualifier access;
   4021 };
   4022 struct _nir_ssbo_atomic_umax_ir3_indices {
   4023    int _; /* exists to avoid empty initializers */
   4024    enum gl_access_qualifier access;
   4025 };
   4026 struct _nir_ssbo_atomic_umin_indices {
   4027    int _; /* exists to avoid empty initializers */
   4028    enum gl_access_qualifier access;
   4029 };
   4030 struct _nir_ssbo_atomic_umin_ir3_indices {
   4031    int _; /* exists to avoid empty initializers */
   4032    enum gl_access_qualifier access;
   4033 };
   4034 struct _nir_ssbo_atomic_xor_indices {
   4035    int _; /* exists to avoid empty initializers */
   4036    enum gl_access_qualifier access;
   4037 };
   4038 struct _nir_ssbo_atomic_xor_ir3_indices {
   4039    int _; /* exists to avoid empty initializers */
   4040    enum gl_access_qualifier access;
   4041 };
   4042 struct _nir_store_buffer_amd_indices {
   4043    int _; /* exists to avoid empty initializers */
   4044    int base;
   4045    unsigned write_mask;
   4046    bool is_swizzled;
   4047    bool slc_amd;
   4048    nir_variable_mode memory_modes;
   4049 };
   4050 struct _nir_store_combined_output_pan_indices {
   4051    int _; /* exists to avoid empty initializers */
   4052    int base;
   4053    unsigned component;
   4054    nir_alu_type src_type;
   4055 };
   4056 struct _nir_store_deref_indices {
   4057    int _; /* exists to avoid empty initializers */
   4058    unsigned write_mask;
   4059    enum gl_access_qualifier access;
   4060 };
   4061 struct _nir_store_deref_block_intel_indices {
   4062    int _; /* exists to avoid empty initializers */
   4063    unsigned write_mask;
   4064    enum gl_access_qualifier access;
   4065 };
   4066 struct _nir_store_global_indices {
   4067    int _; /* exists to avoid empty initializers */
   4068    unsigned write_mask;
   4069    enum gl_access_qualifier access;
   4070    unsigned align_mul;
   4071    unsigned align_offset;
   4072 };
   4073 struct _nir_store_global_block_intel_indices {
   4074    int _; /* exists to avoid empty initializers */
   4075    unsigned write_mask;
   4076    enum gl_access_qualifier access;
   4077    unsigned align_mul;
   4078    unsigned align_offset;
   4079 };
   4080 struct _nir_store_global_ir3_indices {
   4081    int _; /* exists to avoid empty initializers */
   4082    enum gl_access_qualifier access;
   4083    unsigned align_mul;
   4084    unsigned align_offset;
   4085 };
   4086 struct _nir_store_local_shared_r600_indices {
   4087    int _; /* exists to avoid empty initializers */
   4088    unsigned write_mask;
   4089 };
   4090 struct _nir_store_output_indices {
   4091    int _; /* exists to avoid empty initializers */
   4092    int base;
   4093    unsigned write_mask;
   4094    unsigned component;
   4095    nir_alu_type src_type;
   4096    struct nir_io_semantics io_semantics;
   4097 };
   4098 struct _nir_store_per_primitive_output_indices {
   4099    int _; /* exists to avoid empty initializers */
   4100    int base;
   4101    unsigned write_mask;
   4102    unsigned component;
   4103    nir_alu_type src_type;
   4104    struct nir_io_semantics io_semantics;
   4105 };
   4106 struct _nir_store_per_vertex_output_indices {
   4107    int _; /* exists to avoid empty initializers */
   4108    int base;
   4109    unsigned write_mask;
   4110    unsigned component;
   4111    nir_alu_type src_type;
   4112    struct nir_io_semantics io_semantics;
   4113 };
   4114 struct _nir_store_raw_output_pan_indices {
   4115    int _; /* exists to avoid empty initializers */
   4116 };
   4117 struct _nir_store_scratch_indices {
   4118    int _; /* exists to avoid empty initializers */
   4119    unsigned align_mul;
   4120    unsigned align_offset;
   4121    unsigned write_mask;
   4122 };
   4123 struct _nir_store_scratch_dxil_indices {
   4124    int _; /* exists to avoid empty initializers */
   4125 };
   4126 struct _nir_store_shared_indices {
   4127    int _; /* exists to avoid empty initializers */
   4128    int base;
   4129    unsigned write_mask;
   4130    unsigned align_mul;
   4131    unsigned align_offset;
   4132 };
   4133 struct _nir_store_shared_block_intel_indices {
   4134    int _; /* exists to avoid empty initializers */
   4135    int base;
   4136    unsigned write_mask;
   4137    unsigned align_mul;
   4138    unsigned align_offset;
   4139 };
   4140 struct _nir_store_shared_dxil_indices {
   4141    int _; /* exists to avoid empty initializers */
   4142 };
   4143 struct _nir_store_shared_ir3_indices {
   4144    int _; /* exists to avoid empty initializers */
   4145    int base;
   4146    unsigned align_mul;
   4147    unsigned align_offset;
   4148 };
   4149 struct _nir_store_shared_masked_dxil_indices {
   4150    int _; /* exists to avoid empty initializers */
   4151 };
   4152 struct _nir_store_ssbo_indices {
   4153    int _; /* exists to avoid empty initializers */
   4154    unsigned write_mask;
   4155    enum gl_access_qualifier access;
   4156    unsigned align_mul;
   4157    unsigned align_offset;
   4158 };
   4159 struct _nir_store_ssbo_block_intel_indices {
   4160    int _; /* exists to avoid empty initializers */
   4161    unsigned write_mask;
   4162    enum gl_access_qualifier access;
   4163    unsigned align_mul;
   4164    unsigned align_offset;
   4165 };
   4166 struct _nir_store_ssbo_ir3_indices {
   4167    int _; /* exists to avoid empty initializers */
   4168    unsigned write_mask;
   4169    enum gl_access_qualifier access;
   4170    unsigned align_mul;
   4171    unsigned align_offset;
   4172 };
   4173 struct _nir_store_ssbo_masked_dxil_indices {
   4174    int _; /* exists to avoid empty initializers */
   4175 };
   4176 struct _nir_store_tf_r600_indices {
   4177    int _; /* exists to avoid empty initializers */
   4178 };
   4179 struct _nir_store_tlb_sample_color_v3d_indices {
   4180    int _; /* exists to avoid empty initializers */
   4181    int base;
   4182    unsigned component;
   4183    nir_alu_type src_type;
   4184 };
   4185 struct _nir_terminate_indices {
   4186    int _; /* exists to avoid empty initializers */
   4187 };
   4188 struct _nir_terminate_if_indices {
   4189    int _; /* exists to avoid empty initializers */
   4190 };
   4191 struct _nir_terminate_ray_indices {
   4192    int _; /* exists to avoid empty initializers */
   4193 };
   4194 struct _nir_trace_ray_indices {
   4195    int _; /* exists to avoid empty initializers */
   4196 };
   4197 struct _nir_trace_ray_commit_intel_indices {
   4198    int _; /* exists to avoid empty initializers */
   4199 };
   4200 struct _nir_trace_ray_continue_intel_indices {
   4201    int _; /* exists to avoid empty initializers */
   4202 };
   4203 struct _nir_trace_ray_initial_intel_indices {
   4204    int _; /* exists to avoid empty initializers */
   4205 };
   4206 struct _nir_vote_all_indices {
   4207    int _; /* exists to avoid empty initializers */
   4208 };
   4209 struct _nir_vote_any_indices {
   4210    int _; /* exists to avoid empty initializers */
   4211 };
   4212 struct _nir_vote_feq_indices {
   4213    int _; /* exists to avoid empty initializers */
   4214 };
   4215 struct _nir_vote_ieq_indices {
   4216    int _; /* exists to avoid empty initializers */
   4217 };
   4218 struct _nir_vulkan_resource_index_indices {
   4219    int _; /* exists to avoid empty initializers */
   4220    unsigned desc_set;
   4221    unsigned binding;
   4222    unsigned desc_type;
   4223 };
   4224 struct _nir_vulkan_resource_reindex_indices {
   4225    int _; /* exists to avoid empty initializers */
   4226    unsigned desc_type;
   4227 };
   4228 struct _nir_write_invocation_amd_indices {
   4229    int _; /* exists to avoid empty initializers */
   4230 };
   4231 
   4232 
   4233 
   4234 static inline nir_intrinsic_instr *
   4235 _nir_build_accept_ray_intersection(nir_builder *build)
   4236 {
   4237    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4238       build->shader, nir_intrinsic_accept_ray_intersection);
   4239 
   4240 
   4241    nir_builder_instr_insert(build, &intrin->instr);
   4242    return intrin;
   4243 }
   4244 static inline nir_ssa_def *
   4245 _nir_build_addr_mode_is(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_addr_mode_is_indices indices)
   4246 {
   4247    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4248       build->shader, nir_intrinsic_addr_mode_is);
   4249 
   4250       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4251    intrin->src[0] = nir_src_for_ssa(src0);
   4252    nir_intrinsic_set_memory_modes(intrin, indices.memory_modes);
   4253 
   4254    nir_builder_instr_insert(build, &intrin->instr);
   4255    return &intrin->dest.ssa;
   4256 }
   4257 static inline nir_intrinsic_instr *
   4258 _nir_build_alloc_vertices_and_primitives_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   4259 {
   4260    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4261       build->shader, nir_intrinsic_alloc_vertices_and_primitives_amd);
   4262 
   4263    intrin->src[0] = nir_src_for_ssa(src0);
   4264    intrin->src[1] = nir_src_for_ssa(src1);
   4265 
   4266    nir_builder_instr_insert(build, &intrin->instr);
   4267    return intrin;
   4268 }
   4269 static inline nir_ssa_def *
   4270 _nir_build_atomic_counter_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_add_indices indices)
   4271 {
   4272    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4273       build->shader, nir_intrinsic_atomic_counter_add);
   4274 
   4275       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4276    intrin->src[0] = nir_src_for_ssa(src0);
   4277    intrin->src[1] = nir_src_for_ssa(src1);
   4278    nir_intrinsic_set_base(intrin, indices.base);
   4279 
   4280    nir_builder_instr_insert(build, &intrin->instr);
   4281    return &intrin->dest.ssa;
   4282 }
   4283 static inline nir_ssa_def *
   4284 _nir_build_atomic_counter_add_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4285 {
   4286    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4287       build->shader, nir_intrinsic_atomic_counter_add_deref);
   4288 
   4289       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4290    intrin->src[0] = nir_src_for_ssa(src0);
   4291    intrin->src[1] = nir_src_for_ssa(src1);
   4292 
   4293    nir_builder_instr_insert(build, &intrin->instr);
   4294    return &intrin->dest.ssa;
   4295 }
   4296 static inline nir_ssa_def *
   4297 _nir_build_atomic_counter_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_and_indices indices)
   4298 {
   4299    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4300       build->shader, nir_intrinsic_atomic_counter_and);
   4301 
   4302       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4303    intrin->src[0] = nir_src_for_ssa(src0);
   4304    intrin->src[1] = nir_src_for_ssa(src1);
   4305    nir_intrinsic_set_base(intrin, indices.base);
   4306 
   4307    nir_builder_instr_insert(build, &intrin->instr);
   4308    return &intrin->dest.ssa;
   4309 }
   4310 static inline nir_ssa_def *
   4311 _nir_build_atomic_counter_and_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4312 {
   4313    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4314       build->shader, nir_intrinsic_atomic_counter_and_deref);
   4315 
   4316       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4317    intrin->src[0] = nir_src_for_ssa(src0);
   4318    intrin->src[1] = nir_src_for_ssa(src1);
   4319 
   4320    nir_builder_instr_insert(build, &intrin->instr);
   4321    return &intrin->dest.ssa;
   4322 }
   4323 static inline nir_ssa_def *
   4324 _nir_build_atomic_counter_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_atomic_counter_comp_swap_indices indices)
   4325 {
   4326    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4327       build->shader, nir_intrinsic_atomic_counter_comp_swap);
   4328 
   4329       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4330    intrin->src[0] = nir_src_for_ssa(src0);
   4331    intrin->src[1] = nir_src_for_ssa(src1);
   4332    intrin->src[2] = nir_src_for_ssa(src2);
   4333    nir_intrinsic_set_base(intrin, indices.base);
   4334 
   4335    nir_builder_instr_insert(build, &intrin->instr);
   4336    return &intrin->dest.ssa;
   4337 }
   4338 static inline nir_ssa_def *
   4339 _nir_build_atomic_counter_comp_swap_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   4340 {
   4341    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4342       build->shader, nir_intrinsic_atomic_counter_comp_swap_deref);
   4343 
   4344       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4345    intrin->src[0] = nir_src_for_ssa(src0);
   4346    intrin->src[1] = nir_src_for_ssa(src1);
   4347    intrin->src[2] = nir_src_for_ssa(src2);
   4348 
   4349    nir_builder_instr_insert(build, &intrin->instr);
   4350    return &intrin->dest.ssa;
   4351 }
   4352 static inline nir_ssa_def *
   4353 _nir_build_atomic_counter_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_exchange_indices indices)
   4354 {
   4355    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4356       build->shader, nir_intrinsic_atomic_counter_exchange);
   4357 
   4358       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4359    intrin->src[0] = nir_src_for_ssa(src0);
   4360    intrin->src[1] = nir_src_for_ssa(src1);
   4361    nir_intrinsic_set_base(intrin, indices.base);
   4362 
   4363    nir_builder_instr_insert(build, &intrin->instr);
   4364    return &intrin->dest.ssa;
   4365 }
   4366 static inline nir_ssa_def *
   4367 _nir_build_atomic_counter_exchange_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4368 {
   4369    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4370       build->shader, nir_intrinsic_atomic_counter_exchange_deref);
   4371 
   4372       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4373    intrin->src[0] = nir_src_for_ssa(src0);
   4374    intrin->src[1] = nir_src_for_ssa(src1);
   4375 
   4376    nir_builder_instr_insert(build, &intrin->instr);
   4377    return &intrin->dest.ssa;
   4378 }
   4379 static inline nir_ssa_def *
   4380 _nir_build_atomic_counter_inc(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_atomic_counter_inc_indices indices)
   4381 {
   4382    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4383       build->shader, nir_intrinsic_atomic_counter_inc);
   4384 
   4385       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4386    intrin->src[0] = nir_src_for_ssa(src0);
   4387    nir_intrinsic_set_base(intrin, indices.base);
   4388 
   4389    nir_builder_instr_insert(build, &intrin->instr);
   4390    return &intrin->dest.ssa;
   4391 }
   4392 static inline nir_ssa_def *
   4393 _nir_build_atomic_counter_inc_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4394 {
   4395    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4396       build->shader, nir_intrinsic_atomic_counter_inc_deref);
   4397 
   4398       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4399    intrin->src[0] = nir_src_for_ssa(src0);
   4400 
   4401    nir_builder_instr_insert(build, &intrin->instr);
   4402    return &intrin->dest.ssa;
   4403 }
   4404 static inline nir_ssa_def *
   4405 _nir_build_atomic_counter_max(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_max_indices indices)
   4406 {
   4407    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4408       build->shader, nir_intrinsic_atomic_counter_max);
   4409 
   4410       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4411    intrin->src[0] = nir_src_for_ssa(src0);
   4412    intrin->src[1] = nir_src_for_ssa(src1);
   4413    nir_intrinsic_set_base(intrin, indices.base);
   4414 
   4415    nir_builder_instr_insert(build, &intrin->instr);
   4416    return &intrin->dest.ssa;
   4417 }
   4418 static inline nir_ssa_def *
   4419 _nir_build_atomic_counter_max_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4420 {
   4421    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4422       build->shader, nir_intrinsic_atomic_counter_max_deref);
   4423 
   4424       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4425    intrin->src[0] = nir_src_for_ssa(src0);
   4426    intrin->src[1] = nir_src_for_ssa(src1);
   4427 
   4428    nir_builder_instr_insert(build, &intrin->instr);
   4429    return &intrin->dest.ssa;
   4430 }
   4431 static inline nir_ssa_def *
   4432 _nir_build_atomic_counter_min(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_min_indices indices)
   4433 {
   4434    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4435       build->shader, nir_intrinsic_atomic_counter_min);
   4436 
   4437       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4438    intrin->src[0] = nir_src_for_ssa(src0);
   4439    intrin->src[1] = nir_src_for_ssa(src1);
   4440    nir_intrinsic_set_base(intrin, indices.base);
   4441 
   4442    nir_builder_instr_insert(build, &intrin->instr);
   4443    return &intrin->dest.ssa;
   4444 }
   4445 static inline nir_ssa_def *
   4446 _nir_build_atomic_counter_min_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4447 {
   4448    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4449       build->shader, nir_intrinsic_atomic_counter_min_deref);
   4450 
   4451       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4452    intrin->src[0] = nir_src_for_ssa(src0);
   4453    intrin->src[1] = nir_src_for_ssa(src1);
   4454 
   4455    nir_builder_instr_insert(build, &intrin->instr);
   4456    return &intrin->dest.ssa;
   4457 }
   4458 static inline nir_ssa_def *
   4459 _nir_build_atomic_counter_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_or_indices indices)
   4460 {
   4461    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4462       build->shader, nir_intrinsic_atomic_counter_or);
   4463 
   4464       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4465    intrin->src[0] = nir_src_for_ssa(src0);
   4466    intrin->src[1] = nir_src_for_ssa(src1);
   4467    nir_intrinsic_set_base(intrin, indices.base);
   4468 
   4469    nir_builder_instr_insert(build, &intrin->instr);
   4470    return &intrin->dest.ssa;
   4471 }
   4472 static inline nir_ssa_def *
   4473 _nir_build_atomic_counter_or_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4474 {
   4475    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4476       build->shader, nir_intrinsic_atomic_counter_or_deref);
   4477 
   4478       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4479    intrin->src[0] = nir_src_for_ssa(src0);
   4480    intrin->src[1] = nir_src_for_ssa(src1);
   4481 
   4482    nir_builder_instr_insert(build, &intrin->instr);
   4483    return &intrin->dest.ssa;
   4484 }
   4485 static inline nir_ssa_def *
   4486 _nir_build_atomic_counter_post_dec(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_atomic_counter_post_dec_indices indices)
   4487 {
   4488    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4489       build->shader, nir_intrinsic_atomic_counter_post_dec);
   4490 
   4491       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4492    intrin->src[0] = nir_src_for_ssa(src0);
   4493    nir_intrinsic_set_base(intrin, indices.base);
   4494 
   4495    nir_builder_instr_insert(build, &intrin->instr);
   4496    return &intrin->dest.ssa;
   4497 }
   4498 static inline nir_ssa_def *
   4499 _nir_build_atomic_counter_post_dec_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4500 {
   4501    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4502       build->shader, nir_intrinsic_atomic_counter_post_dec_deref);
   4503 
   4504       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4505    intrin->src[0] = nir_src_for_ssa(src0);
   4506 
   4507    nir_builder_instr_insert(build, &intrin->instr);
   4508    return &intrin->dest.ssa;
   4509 }
   4510 static inline nir_ssa_def *
   4511 _nir_build_atomic_counter_pre_dec(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_atomic_counter_pre_dec_indices indices)
   4512 {
   4513    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4514       build->shader, nir_intrinsic_atomic_counter_pre_dec);
   4515 
   4516       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4517    intrin->src[0] = nir_src_for_ssa(src0);
   4518    nir_intrinsic_set_base(intrin, indices.base);
   4519 
   4520    nir_builder_instr_insert(build, &intrin->instr);
   4521    return &intrin->dest.ssa;
   4522 }
   4523 static inline nir_ssa_def *
   4524 _nir_build_atomic_counter_pre_dec_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4525 {
   4526    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4527       build->shader, nir_intrinsic_atomic_counter_pre_dec_deref);
   4528 
   4529       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4530    intrin->src[0] = nir_src_for_ssa(src0);
   4531 
   4532    nir_builder_instr_insert(build, &intrin->instr);
   4533    return &intrin->dest.ssa;
   4534 }
   4535 static inline nir_ssa_def *
   4536 _nir_build_atomic_counter_read(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_atomic_counter_read_indices indices)
   4537 {
   4538    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4539       build->shader, nir_intrinsic_atomic_counter_read);
   4540 
   4541       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4542    intrin->src[0] = nir_src_for_ssa(src0);
   4543    nir_intrinsic_set_base(intrin, indices.base);
   4544 
   4545    nir_builder_instr_insert(build, &intrin->instr);
   4546    return &intrin->dest.ssa;
   4547 }
   4548 static inline nir_ssa_def *
   4549 _nir_build_atomic_counter_read_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4550 {
   4551    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4552       build->shader, nir_intrinsic_atomic_counter_read_deref);
   4553 
   4554       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4555    intrin->src[0] = nir_src_for_ssa(src0);
   4556 
   4557    nir_builder_instr_insert(build, &intrin->instr);
   4558    return &intrin->dest.ssa;
   4559 }
   4560 static inline nir_ssa_def *
   4561 _nir_build_atomic_counter_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_atomic_counter_xor_indices indices)
   4562 {
   4563    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4564       build->shader, nir_intrinsic_atomic_counter_xor);
   4565 
   4566       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4567    intrin->src[0] = nir_src_for_ssa(src0);
   4568    intrin->src[1] = nir_src_for_ssa(src1);
   4569    nir_intrinsic_set_base(intrin, indices.base);
   4570 
   4571    nir_builder_instr_insert(build, &intrin->instr);
   4572    return &intrin->dest.ssa;
   4573 }
   4574 static inline nir_ssa_def *
   4575 _nir_build_atomic_counter_xor_deref(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4576 {
   4577    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4578       build->shader, nir_intrinsic_atomic_counter_xor_deref);
   4579 
   4580       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4581    intrin->src[0] = nir_src_for_ssa(src0);
   4582    intrin->src[1] = nir_src_for_ssa(src1);
   4583 
   4584    nir_builder_instr_insert(build, &intrin->instr);
   4585    return &intrin->dest.ssa;
   4586 }
   4587 static inline nir_ssa_def *
   4588 _nir_build_ballot(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0)
   4589 {
   4590    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4591       build->shader, nir_intrinsic_ballot);
   4592 
   4593    intrin->num_components = num_components;
   4594       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   4595    intrin->src[0] = nir_src_for_ssa(src0);
   4596 
   4597    nir_builder_instr_insert(build, &intrin->instr);
   4598    return &intrin->dest.ssa;
   4599 }
   4600 static inline nir_ssa_def *
   4601 _nir_build_ballot_bit_count_exclusive(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4602 {
   4603    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4604       build->shader, nir_intrinsic_ballot_bit_count_exclusive);
   4605 
   4606       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4607    intrin->src[0] = nir_src_for_ssa(src0);
   4608 
   4609    nir_builder_instr_insert(build, &intrin->instr);
   4610    return &intrin->dest.ssa;
   4611 }
   4612 static inline nir_ssa_def *
   4613 _nir_build_ballot_bit_count_inclusive(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4614 {
   4615    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4616       build->shader, nir_intrinsic_ballot_bit_count_inclusive);
   4617 
   4618       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4619    intrin->src[0] = nir_src_for_ssa(src0);
   4620 
   4621    nir_builder_instr_insert(build, &intrin->instr);
   4622    return &intrin->dest.ssa;
   4623 }
   4624 static inline nir_ssa_def *
   4625 _nir_build_ballot_bit_count_reduce(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4626 {
   4627    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4628       build->shader, nir_intrinsic_ballot_bit_count_reduce);
   4629 
   4630       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4631    intrin->src[0] = nir_src_for_ssa(src0);
   4632 
   4633    nir_builder_instr_insert(build, &intrin->instr);
   4634    return &intrin->dest.ssa;
   4635 }
   4636 static inline nir_ssa_def *
   4637 _nir_build_ballot_bitfield_extract(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   4638 {
   4639    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4640       build->shader, nir_intrinsic_ballot_bitfield_extract);
   4641 
   4642       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4643    intrin->src[0] = nir_src_for_ssa(src0);
   4644    intrin->src[1] = nir_src_for_ssa(src1);
   4645 
   4646    nir_builder_instr_insert(build, &intrin->instr);
   4647    return &intrin->dest.ssa;
   4648 }
   4649 static inline nir_ssa_def *
   4650 _nir_build_ballot_find_lsb(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4651 {
   4652    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4653       build->shader, nir_intrinsic_ballot_find_lsb);
   4654 
   4655       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4656    intrin->src[0] = nir_src_for_ssa(src0);
   4657 
   4658    nir_builder_instr_insert(build, &intrin->instr);
   4659    return &intrin->dest.ssa;
   4660 }
   4661 static inline nir_ssa_def *
   4662 _nir_build_ballot_find_msb(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   4663 {
   4664    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4665       build->shader, nir_intrinsic_ballot_find_msb);
   4666 
   4667       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4668    intrin->src[0] = nir_src_for_ssa(src0);
   4669 
   4670    nir_builder_instr_insert(build, &intrin->instr);
   4671    return &intrin->dest.ssa;
   4672 }
   4673 static inline nir_intrinsic_instr *
   4674 _nir_build_begin_invocation_interlock(nir_builder *build)
   4675 {
   4676    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4677       build->shader, nir_intrinsic_begin_invocation_interlock);
   4678 
   4679 
   4680    nir_builder_instr_insert(build, &intrin->instr);
   4681    return intrin;
   4682 }
   4683 static inline nir_ssa_def *
   4684 _nir_build_bindless_image_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_add_indices indices)
   4685 {
   4686    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4687       build->shader, nir_intrinsic_bindless_image_atomic_add);
   4688 
   4689       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4690    intrin->src[0] = nir_src_for_ssa(src0);
   4691    intrin->src[1] = nir_src_for_ssa(src1);
   4692    intrin->src[2] = nir_src_for_ssa(src2);
   4693    intrin->src[3] = nir_src_for_ssa(src3);
   4694    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4695    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4696    nir_intrinsic_set_format(intrin, indices.format);
   4697    nir_intrinsic_set_access(intrin, indices.access);
   4698 
   4699    nir_builder_instr_insert(build, &intrin->instr);
   4700    return &intrin->dest.ssa;
   4701 }
   4702 static inline nir_ssa_def *
   4703 _nir_build_bindless_image_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_and_indices indices)
   4704 {
   4705    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4706       build->shader, nir_intrinsic_bindless_image_atomic_and);
   4707 
   4708       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4709    intrin->src[0] = nir_src_for_ssa(src0);
   4710    intrin->src[1] = nir_src_for_ssa(src1);
   4711    intrin->src[2] = nir_src_for_ssa(src2);
   4712    intrin->src[3] = nir_src_for_ssa(src3);
   4713    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4714    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4715    nir_intrinsic_set_format(intrin, indices.format);
   4716    nir_intrinsic_set_access(intrin, indices.access);
   4717 
   4718    nir_builder_instr_insert(build, &intrin->instr);
   4719    return &intrin->dest.ssa;
   4720 }
   4721 static inline nir_ssa_def *
   4722 _nir_build_bindless_image_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_bindless_image_atomic_comp_swap_indices indices)
   4723 {
   4724    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4725       build->shader, nir_intrinsic_bindless_image_atomic_comp_swap);
   4726 
   4727       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4728    intrin->src[0] = nir_src_for_ssa(src0);
   4729    intrin->src[1] = nir_src_for_ssa(src1);
   4730    intrin->src[2] = nir_src_for_ssa(src2);
   4731    intrin->src[3] = nir_src_for_ssa(src3);
   4732    intrin->src[4] = nir_src_for_ssa(src4);
   4733    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4734    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4735    nir_intrinsic_set_format(intrin, indices.format);
   4736    nir_intrinsic_set_access(intrin, indices.access);
   4737 
   4738    nir_builder_instr_insert(build, &intrin->instr);
   4739    return &intrin->dest.ssa;
   4740 }
   4741 static inline nir_ssa_def *
   4742 _nir_build_bindless_image_atomic_dec_wrap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_dec_wrap_indices indices)
   4743 {
   4744    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4745       build->shader, nir_intrinsic_bindless_image_atomic_dec_wrap);
   4746 
   4747       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4748    intrin->src[0] = nir_src_for_ssa(src0);
   4749    intrin->src[1] = nir_src_for_ssa(src1);
   4750    intrin->src[2] = nir_src_for_ssa(src2);
   4751    intrin->src[3] = nir_src_for_ssa(src3);
   4752    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4753    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4754    nir_intrinsic_set_format(intrin, indices.format);
   4755    nir_intrinsic_set_access(intrin, indices.access);
   4756 
   4757    nir_builder_instr_insert(build, &intrin->instr);
   4758    return &intrin->dest.ssa;
   4759 }
   4760 static inline nir_ssa_def *
   4761 _nir_build_bindless_image_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_exchange_indices indices)
   4762 {
   4763    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4764       build->shader, nir_intrinsic_bindless_image_atomic_exchange);
   4765 
   4766       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4767    intrin->src[0] = nir_src_for_ssa(src0);
   4768    intrin->src[1] = nir_src_for_ssa(src1);
   4769    intrin->src[2] = nir_src_for_ssa(src2);
   4770    intrin->src[3] = nir_src_for_ssa(src3);
   4771    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4772    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4773    nir_intrinsic_set_format(intrin, indices.format);
   4774    nir_intrinsic_set_access(intrin, indices.access);
   4775 
   4776    nir_builder_instr_insert(build, &intrin->instr);
   4777    return &intrin->dest.ssa;
   4778 }
   4779 static inline nir_ssa_def *
   4780 _nir_build_bindless_image_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_fadd_indices indices)
   4781 {
   4782    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4783       build->shader, nir_intrinsic_bindless_image_atomic_fadd);
   4784 
   4785       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4786    intrin->src[0] = nir_src_for_ssa(src0);
   4787    intrin->src[1] = nir_src_for_ssa(src1);
   4788    intrin->src[2] = nir_src_for_ssa(src2);
   4789    intrin->src[3] = nir_src_for_ssa(src3);
   4790    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4791    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4792    nir_intrinsic_set_format(intrin, indices.format);
   4793    nir_intrinsic_set_access(intrin, indices.access);
   4794 
   4795    nir_builder_instr_insert(build, &intrin->instr);
   4796    return &intrin->dest.ssa;
   4797 }
   4798 static inline nir_ssa_def *
   4799 _nir_build_bindless_image_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_fmax_indices indices)
   4800 {
   4801    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4802       build->shader, nir_intrinsic_bindless_image_atomic_fmax);
   4803 
   4804       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4805    intrin->src[0] = nir_src_for_ssa(src0);
   4806    intrin->src[1] = nir_src_for_ssa(src1);
   4807    intrin->src[2] = nir_src_for_ssa(src2);
   4808    intrin->src[3] = nir_src_for_ssa(src3);
   4809    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4810    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4811    nir_intrinsic_set_format(intrin, indices.format);
   4812    nir_intrinsic_set_access(intrin, indices.access);
   4813 
   4814    nir_builder_instr_insert(build, &intrin->instr);
   4815    return &intrin->dest.ssa;
   4816 }
   4817 static inline nir_ssa_def *
   4818 _nir_build_bindless_image_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_fmin_indices indices)
   4819 {
   4820    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4821       build->shader, nir_intrinsic_bindless_image_atomic_fmin);
   4822 
   4823       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4824    intrin->src[0] = nir_src_for_ssa(src0);
   4825    intrin->src[1] = nir_src_for_ssa(src1);
   4826    intrin->src[2] = nir_src_for_ssa(src2);
   4827    intrin->src[3] = nir_src_for_ssa(src3);
   4828    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4829    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4830    nir_intrinsic_set_format(intrin, indices.format);
   4831    nir_intrinsic_set_access(intrin, indices.access);
   4832 
   4833    nir_builder_instr_insert(build, &intrin->instr);
   4834    return &intrin->dest.ssa;
   4835 }
   4836 static inline nir_ssa_def *
   4837 _nir_build_bindless_image_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_imax_indices indices)
   4838 {
   4839    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4840       build->shader, nir_intrinsic_bindless_image_atomic_imax);
   4841 
   4842       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4843    intrin->src[0] = nir_src_for_ssa(src0);
   4844    intrin->src[1] = nir_src_for_ssa(src1);
   4845    intrin->src[2] = nir_src_for_ssa(src2);
   4846    intrin->src[3] = nir_src_for_ssa(src3);
   4847    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4848    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4849    nir_intrinsic_set_format(intrin, indices.format);
   4850    nir_intrinsic_set_access(intrin, indices.access);
   4851 
   4852    nir_builder_instr_insert(build, &intrin->instr);
   4853    return &intrin->dest.ssa;
   4854 }
   4855 static inline nir_ssa_def *
   4856 _nir_build_bindless_image_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_imin_indices indices)
   4857 {
   4858    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4859       build->shader, nir_intrinsic_bindless_image_atomic_imin);
   4860 
   4861       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4862    intrin->src[0] = nir_src_for_ssa(src0);
   4863    intrin->src[1] = nir_src_for_ssa(src1);
   4864    intrin->src[2] = nir_src_for_ssa(src2);
   4865    intrin->src[3] = nir_src_for_ssa(src3);
   4866    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4867    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4868    nir_intrinsic_set_format(intrin, indices.format);
   4869    nir_intrinsic_set_access(intrin, indices.access);
   4870 
   4871    nir_builder_instr_insert(build, &intrin->instr);
   4872    return &intrin->dest.ssa;
   4873 }
   4874 static inline nir_ssa_def *
   4875 _nir_build_bindless_image_atomic_inc_wrap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_inc_wrap_indices indices)
   4876 {
   4877    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4878       build->shader, nir_intrinsic_bindless_image_atomic_inc_wrap);
   4879 
   4880       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4881    intrin->src[0] = nir_src_for_ssa(src0);
   4882    intrin->src[1] = nir_src_for_ssa(src1);
   4883    intrin->src[2] = nir_src_for_ssa(src2);
   4884    intrin->src[3] = nir_src_for_ssa(src3);
   4885    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4886    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4887    nir_intrinsic_set_format(intrin, indices.format);
   4888    nir_intrinsic_set_access(intrin, indices.access);
   4889 
   4890    nir_builder_instr_insert(build, &intrin->instr);
   4891    return &intrin->dest.ssa;
   4892 }
   4893 static inline nir_ssa_def *
   4894 _nir_build_bindless_image_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_or_indices indices)
   4895 {
   4896    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4897       build->shader, nir_intrinsic_bindless_image_atomic_or);
   4898 
   4899       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4900    intrin->src[0] = nir_src_for_ssa(src0);
   4901    intrin->src[1] = nir_src_for_ssa(src1);
   4902    intrin->src[2] = nir_src_for_ssa(src2);
   4903    intrin->src[3] = nir_src_for_ssa(src3);
   4904    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4905    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4906    nir_intrinsic_set_format(intrin, indices.format);
   4907    nir_intrinsic_set_access(intrin, indices.access);
   4908 
   4909    nir_builder_instr_insert(build, &intrin->instr);
   4910    return &intrin->dest.ssa;
   4911 }
   4912 static inline nir_ssa_def *
   4913 _nir_build_bindless_image_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_umax_indices indices)
   4914 {
   4915    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4916       build->shader, nir_intrinsic_bindless_image_atomic_umax);
   4917 
   4918       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4919    intrin->src[0] = nir_src_for_ssa(src0);
   4920    intrin->src[1] = nir_src_for_ssa(src1);
   4921    intrin->src[2] = nir_src_for_ssa(src2);
   4922    intrin->src[3] = nir_src_for_ssa(src3);
   4923    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4924    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4925    nir_intrinsic_set_format(intrin, indices.format);
   4926    nir_intrinsic_set_access(intrin, indices.access);
   4927 
   4928    nir_builder_instr_insert(build, &intrin->instr);
   4929    return &intrin->dest.ssa;
   4930 }
   4931 static inline nir_ssa_def *
   4932 _nir_build_bindless_image_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_umin_indices indices)
   4933 {
   4934    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4935       build->shader, nir_intrinsic_bindless_image_atomic_umin);
   4936 
   4937       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4938    intrin->src[0] = nir_src_for_ssa(src0);
   4939    intrin->src[1] = nir_src_for_ssa(src1);
   4940    intrin->src[2] = nir_src_for_ssa(src2);
   4941    intrin->src[3] = nir_src_for_ssa(src3);
   4942    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4943    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4944    nir_intrinsic_set_format(intrin, indices.format);
   4945    nir_intrinsic_set_access(intrin, indices.access);
   4946 
   4947    nir_builder_instr_insert(build, &intrin->instr);
   4948    return &intrin->dest.ssa;
   4949 }
   4950 static inline nir_ssa_def *
   4951 _nir_build_bindless_image_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_atomic_xor_indices indices)
   4952 {
   4953    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4954       build->shader, nir_intrinsic_bindless_image_atomic_xor);
   4955 
   4956       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4957    intrin->src[0] = nir_src_for_ssa(src0);
   4958    intrin->src[1] = nir_src_for_ssa(src1);
   4959    intrin->src[2] = nir_src_for_ssa(src2);
   4960    intrin->src[3] = nir_src_for_ssa(src3);
   4961    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4962    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4963    nir_intrinsic_set_format(intrin, indices.format);
   4964    nir_intrinsic_set_access(intrin, indices.access);
   4965 
   4966    nir_builder_instr_insert(build, &intrin->instr);
   4967    return &intrin->dest.ssa;
   4968 }
   4969 static inline nir_ssa_def *
   4970 _nir_build_bindless_image_format(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_bindless_image_format_indices indices)
   4971 {
   4972    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4973       build->shader, nir_intrinsic_bindless_image_format);
   4974 
   4975       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   4976    intrin->src[0] = nir_src_for_ssa(src0);
   4977    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4978    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4979    nir_intrinsic_set_format(intrin, indices.format);
   4980    nir_intrinsic_set_access(intrin, indices.access);
   4981 
   4982    nir_builder_instr_insert(build, &intrin->instr);
   4983    return &intrin->dest.ssa;
   4984 }
   4985 static inline nir_ssa_def *
   4986 _nir_build_bindless_image_load(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_load_indices indices)
   4987 {
   4988    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   4989       build->shader, nir_intrinsic_bindless_image_load);
   4990 
   4991    intrin->num_components = num_components;
   4992       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   4993    intrin->src[0] = nir_src_for_ssa(src0);
   4994    intrin->src[1] = nir_src_for_ssa(src1);
   4995    intrin->src[2] = nir_src_for_ssa(src2);
   4996    intrin->src[3] = nir_src_for_ssa(src3);
   4997    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   4998    nir_intrinsic_set_image_array(intrin, indices.image_array);
   4999    nir_intrinsic_set_format(intrin, indices.format);
   5000    nir_intrinsic_set_access(intrin, indices.access);
   5001    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   5002 
   5003    nir_builder_instr_insert(build, &intrin->instr);
   5004    return &intrin->dest.ssa;
   5005 }
   5006 static inline nir_ssa_def *
   5007 _nir_build_bindless_image_load_raw_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_bindless_image_load_raw_intel_indices indices)
   5008 {
   5009    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5010       build->shader, nir_intrinsic_bindless_image_load_raw_intel);
   5011 
   5012    intrin->num_components = num_components;
   5013       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   5014    intrin->src[0] = nir_src_for_ssa(src0);
   5015    intrin->src[1] = nir_src_for_ssa(src1);
   5016    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5017    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5018    nir_intrinsic_set_format(intrin, indices.format);
   5019    nir_intrinsic_set_access(intrin, indices.access);
   5020 
   5021    nir_builder_instr_insert(build, &intrin->instr);
   5022    return &intrin->dest.ssa;
   5023 }
   5024 static inline nir_ssa_def *
   5025 _nir_build_bindless_image_order(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_bindless_image_order_indices indices)
   5026 {
   5027    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5028       build->shader, nir_intrinsic_bindless_image_order);
   5029 
   5030       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5031    intrin->src[0] = nir_src_for_ssa(src0);
   5032    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5033    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5034    nir_intrinsic_set_format(intrin, indices.format);
   5035    nir_intrinsic_set_access(intrin, indices.access);
   5036 
   5037    nir_builder_instr_insert(build, &intrin->instr);
   5038    return &intrin->dest.ssa;
   5039 }
   5040 static inline nir_ssa_def *
   5041 _nir_build_bindless_image_samples(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_bindless_image_samples_indices indices)
   5042 {
   5043    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5044       build->shader, nir_intrinsic_bindless_image_samples);
   5045 
   5046       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5047    intrin->src[0] = nir_src_for_ssa(src0);
   5048    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5049    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5050    nir_intrinsic_set_format(intrin, indices.format);
   5051    nir_intrinsic_set_access(intrin, indices.access);
   5052 
   5053    nir_builder_instr_insert(build, &intrin->instr);
   5054    return &intrin->dest.ssa;
   5055 }
   5056 static inline nir_ssa_def *
   5057 _nir_build_bindless_image_size(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_bindless_image_size_indices indices)
   5058 {
   5059    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5060       build->shader, nir_intrinsic_bindless_image_size);
   5061 
   5062    intrin->num_components = num_components;
   5063       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   5064    intrin->src[0] = nir_src_for_ssa(src0);
   5065    intrin->src[1] = nir_src_for_ssa(src1);
   5066    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5067    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5068    nir_intrinsic_set_format(intrin, indices.format);
   5069    nir_intrinsic_set_access(intrin, indices.access);
   5070 
   5071    nir_builder_instr_insert(build, &intrin->instr);
   5072    return &intrin->dest.ssa;
   5073 }
   5074 static inline nir_ssa_def *
   5075 _nir_build_bindless_image_sparse_load(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_bindless_image_sparse_load_indices indices)
   5076 {
   5077    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5078       build->shader, nir_intrinsic_bindless_image_sparse_load);
   5079 
   5080    intrin->num_components = num_components;
   5081       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   5082    intrin->src[0] = nir_src_for_ssa(src0);
   5083    intrin->src[1] = nir_src_for_ssa(src1);
   5084    intrin->src[2] = nir_src_for_ssa(src2);
   5085    intrin->src[3] = nir_src_for_ssa(src3);
   5086    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5087    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5088    nir_intrinsic_set_format(intrin, indices.format);
   5089    nir_intrinsic_set_access(intrin, indices.access);
   5090    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   5091 
   5092    nir_builder_instr_insert(build, &intrin->instr);
   5093    return &intrin->dest.ssa;
   5094 }
   5095 static inline nir_intrinsic_instr *
   5096 _nir_build_bindless_image_store(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_bindless_image_store_indices indices)
   5097 {
   5098    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5099       build->shader, nir_intrinsic_bindless_image_store);
   5100 
   5101    intrin->num_components = src3->num_components;
   5102    intrin->src[0] = nir_src_for_ssa(src0);
   5103    intrin->src[1] = nir_src_for_ssa(src1);
   5104    intrin->src[2] = nir_src_for_ssa(src2);
   5105    intrin->src[3] = nir_src_for_ssa(src3);
   5106    intrin->src[4] = nir_src_for_ssa(src4);
   5107    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5108    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5109    nir_intrinsic_set_format(intrin, indices.format);
   5110    nir_intrinsic_set_access(intrin, indices.access);
   5111    nir_intrinsic_set_src_type(intrin, indices.src_type);
   5112 
   5113    nir_builder_instr_insert(build, &intrin->instr);
   5114    return intrin;
   5115 }
   5116 static inline nir_intrinsic_instr *
   5117 _nir_build_bindless_image_store_raw_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_bindless_image_store_raw_intel_indices indices)
   5118 {
   5119    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5120       build->shader, nir_intrinsic_bindless_image_store_raw_intel);
   5121 
   5122    intrin->num_components = src2->num_components;
   5123    intrin->src[0] = nir_src_for_ssa(src0);
   5124    intrin->src[1] = nir_src_for_ssa(src1);
   5125    intrin->src[2] = nir_src_for_ssa(src2);
   5126    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5127    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5128    nir_intrinsic_set_format(intrin, indices.format);
   5129    nir_intrinsic_set_access(intrin, indices.access);
   5130 
   5131    nir_builder_instr_insert(build, &intrin->instr);
   5132    return intrin;
   5133 }
   5134 static inline nir_ssa_def *
   5135 _nir_build_bindless_resource_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_bindless_resource_ir3_indices indices)
   5136 {
   5137    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5138       build->shader, nir_intrinsic_bindless_resource_ir3);
   5139 
   5140       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5141    intrin->src[0] = nir_src_for_ssa(src0);
   5142    nir_intrinsic_set_desc_set(intrin, indices.desc_set);
   5143 
   5144    nir_builder_instr_insert(build, &intrin->instr);
   5145    return &intrin->dest.ssa;
   5146 }
   5147 static inline nir_intrinsic_instr *
   5148 _nir_build_btd_retire_intel(nir_builder *build)
   5149 {
   5150    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5151       build->shader, nir_intrinsic_btd_retire_intel);
   5152 
   5153 
   5154    nir_builder_instr_insert(build, &intrin->instr);
   5155    return intrin;
   5156 }
   5157 static inline nir_intrinsic_instr *
   5158 _nir_build_btd_spawn_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   5159 {
   5160    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5161       build->shader, nir_intrinsic_btd_spawn_intel);
   5162 
   5163    intrin->src[0] = nir_src_for_ssa(src0);
   5164    intrin->src[1] = nir_src_for_ssa(src1);
   5165 
   5166    nir_builder_instr_insert(build, &intrin->instr);
   5167    return intrin;
   5168 }
   5169 static inline nir_intrinsic_instr *
   5170 _nir_build_btd_stack_push_intel(nir_builder *build, struct _nir_btd_stack_push_intel_indices indices)
   5171 {
   5172    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5173       build->shader, nir_intrinsic_btd_stack_push_intel);
   5174 
   5175    nir_intrinsic_set_stack_size(intrin, indices.stack_size);
   5176 
   5177    nir_builder_instr_insert(build, &intrin->instr);
   5178    return intrin;
   5179 }
   5180 static inline nir_ssa_def *
   5181 _nir_build_bvh64_intersect_ray_amd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, nir_ssa_def *src5)
   5182 {
   5183    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5184       build->shader, nir_intrinsic_bvh64_intersect_ray_amd);
   5185 
   5186       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, bit_size, NULL);
   5187    intrin->src[0] = nir_src_for_ssa(src0);
   5188    intrin->src[1] = nir_src_for_ssa(src1);
   5189    intrin->src[2] = nir_src_for_ssa(src2);
   5190    intrin->src[3] = nir_src_for_ssa(src3);
   5191    intrin->src[4] = nir_src_for_ssa(src4);
   5192    intrin->src[5] = nir_src_for_ssa(src5);
   5193 
   5194    nir_builder_instr_insert(build, &intrin->instr);
   5195    return &intrin->dest.ssa;
   5196 }
   5197 static inline nir_ssa_def *
   5198 _nir_build_byte_permute_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   5199 {
   5200    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5201       build->shader, nir_intrinsic_byte_permute_amd);
   5202 
   5203       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   5204    intrin->src[0] = nir_src_for_ssa(src0);
   5205    intrin->src[1] = nir_src_for_ssa(src1);
   5206    intrin->src[2] = nir_src_for_ssa(src2);
   5207 
   5208    nir_builder_instr_insert(build, &intrin->instr);
   5209    return &intrin->dest.ssa;
   5210 }
   5211 static inline nir_intrinsic_instr *
   5212 _nir_build_cond_end_ir3(nir_builder *build, nir_ssa_def *src0)
   5213 {
   5214    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5215       build->shader, nir_intrinsic_cond_end_ir3);
   5216 
   5217    intrin->src[0] = nir_src_for_ssa(src0);
   5218 
   5219    nir_builder_instr_insert(build, &intrin->instr);
   5220    return intrin;
   5221 }
   5222 static inline nir_intrinsic_instr *
   5223 _nir_build_control_barrier(nir_builder *build)
   5224 {
   5225    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5226       build->shader, nir_intrinsic_control_barrier);
   5227 
   5228 
   5229    nir_builder_instr_insert(build, &intrin->instr);
   5230    return intrin;
   5231 }
   5232 static inline nir_ssa_def *
   5233 _nir_build_convert_alu_types(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_convert_alu_types_indices indices)
   5234 {
   5235    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5236       build->shader, nir_intrinsic_convert_alu_types);
   5237 
   5238    intrin->num_components = src0->num_components;
   5239       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   5240    intrin->src[0] = nir_src_for_ssa(src0);
   5241    nir_intrinsic_set_src_type(intrin, indices.src_type);
   5242    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   5243    nir_intrinsic_set_rounding_mode(intrin, indices.rounding_mode);
   5244    nir_intrinsic_set_saturate(intrin, indices.saturate);
   5245 
   5246    nir_builder_instr_insert(build, &intrin->instr);
   5247    return &intrin->dest.ssa;
   5248 }
   5249 static inline nir_intrinsic_instr *
   5250 _nir_build_copy_deref(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_copy_deref_indices indices)
   5251 {
   5252    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5253       build->shader, nir_intrinsic_copy_deref);
   5254 
   5255    intrin->src[0] = nir_src_for_ssa(src0);
   5256    intrin->src[1] = nir_src_for_ssa(src1);
   5257    nir_intrinsic_set_dst_access(intrin, indices.dst_access);
   5258    nir_intrinsic_set_src_access(intrin, indices.src_access);
   5259 
   5260    nir_builder_instr_insert(build, &intrin->instr);
   5261    return intrin;
   5262 }
   5263 static inline nir_intrinsic_instr *
   5264 _nir_build_demote(nir_builder *build)
   5265 {
   5266    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5267       build->shader, nir_intrinsic_demote);
   5268 
   5269 
   5270    nir_builder_instr_insert(build, &intrin->instr);
   5271    return intrin;
   5272 }
   5273 static inline nir_intrinsic_instr *
   5274 _nir_build_demote_if(nir_builder *build, nir_ssa_def *src0)
   5275 {
   5276    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5277       build->shader, nir_intrinsic_demote_if);
   5278 
   5279    intrin->src[0] = nir_src_for_ssa(src0);
   5280 
   5281    nir_builder_instr_insert(build, &intrin->instr);
   5282    return intrin;
   5283 }
   5284 static inline nir_ssa_def *
   5285 _nir_build_deref_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_add_indices indices)
   5286 {
   5287    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5288       build->shader, nir_intrinsic_deref_atomic_add);
   5289 
   5290       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5291    intrin->src[0] = nir_src_for_ssa(src0);
   5292    intrin->src[1] = nir_src_for_ssa(src1);
   5293    nir_intrinsic_set_access(intrin, indices.access);
   5294 
   5295    nir_builder_instr_insert(build, &intrin->instr);
   5296    return &intrin->dest.ssa;
   5297 }
   5298 static inline nir_ssa_def *
   5299 _nir_build_deref_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_and_indices indices)
   5300 {
   5301    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5302       build->shader, nir_intrinsic_deref_atomic_and);
   5303 
   5304       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5305    intrin->src[0] = nir_src_for_ssa(src0);
   5306    intrin->src[1] = nir_src_for_ssa(src1);
   5307    nir_intrinsic_set_access(intrin, indices.access);
   5308 
   5309    nir_builder_instr_insert(build, &intrin->instr);
   5310    return &intrin->dest.ssa;
   5311 }
   5312 static inline nir_ssa_def *
   5313 _nir_build_deref_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_deref_atomic_comp_swap_indices indices)
   5314 {
   5315    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5316       build->shader, nir_intrinsic_deref_atomic_comp_swap);
   5317 
   5318       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5319    intrin->src[0] = nir_src_for_ssa(src0);
   5320    intrin->src[1] = nir_src_for_ssa(src1);
   5321    intrin->src[2] = nir_src_for_ssa(src2);
   5322    nir_intrinsic_set_access(intrin, indices.access);
   5323 
   5324    nir_builder_instr_insert(build, &intrin->instr);
   5325    return &intrin->dest.ssa;
   5326 }
   5327 static inline nir_ssa_def *
   5328 _nir_build_deref_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_exchange_indices indices)
   5329 {
   5330    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5331       build->shader, nir_intrinsic_deref_atomic_exchange);
   5332 
   5333       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5334    intrin->src[0] = nir_src_for_ssa(src0);
   5335    intrin->src[1] = nir_src_for_ssa(src1);
   5336    nir_intrinsic_set_access(intrin, indices.access);
   5337 
   5338    nir_builder_instr_insert(build, &intrin->instr);
   5339    return &intrin->dest.ssa;
   5340 }
   5341 static inline nir_ssa_def *
   5342 _nir_build_deref_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_fadd_indices indices)
   5343 {
   5344    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5345       build->shader, nir_intrinsic_deref_atomic_fadd);
   5346 
   5347       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5348    intrin->src[0] = nir_src_for_ssa(src0);
   5349    intrin->src[1] = nir_src_for_ssa(src1);
   5350    nir_intrinsic_set_access(intrin, indices.access);
   5351 
   5352    nir_builder_instr_insert(build, &intrin->instr);
   5353    return &intrin->dest.ssa;
   5354 }
   5355 static inline nir_ssa_def *
   5356 _nir_build_deref_atomic_fcomp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_deref_atomic_fcomp_swap_indices indices)
   5357 {
   5358    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5359       build->shader, nir_intrinsic_deref_atomic_fcomp_swap);
   5360 
   5361       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5362    intrin->src[0] = nir_src_for_ssa(src0);
   5363    intrin->src[1] = nir_src_for_ssa(src1);
   5364    intrin->src[2] = nir_src_for_ssa(src2);
   5365    nir_intrinsic_set_access(intrin, indices.access);
   5366 
   5367    nir_builder_instr_insert(build, &intrin->instr);
   5368    return &intrin->dest.ssa;
   5369 }
   5370 static inline nir_ssa_def *
   5371 _nir_build_deref_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_fmax_indices indices)
   5372 {
   5373    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5374       build->shader, nir_intrinsic_deref_atomic_fmax);
   5375 
   5376       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5377    intrin->src[0] = nir_src_for_ssa(src0);
   5378    intrin->src[1] = nir_src_for_ssa(src1);
   5379    nir_intrinsic_set_access(intrin, indices.access);
   5380 
   5381    nir_builder_instr_insert(build, &intrin->instr);
   5382    return &intrin->dest.ssa;
   5383 }
   5384 static inline nir_ssa_def *
   5385 _nir_build_deref_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_fmin_indices indices)
   5386 {
   5387    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5388       build->shader, nir_intrinsic_deref_atomic_fmin);
   5389 
   5390       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5391    intrin->src[0] = nir_src_for_ssa(src0);
   5392    intrin->src[1] = nir_src_for_ssa(src1);
   5393    nir_intrinsic_set_access(intrin, indices.access);
   5394 
   5395    nir_builder_instr_insert(build, &intrin->instr);
   5396    return &intrin->dest.ssa;
   5397 }
   5398 static inline nir_ssa_def *
   5399 _nir_build_deref_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_imax_indices indices)
   5400 {
   5401    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5402       build->shader, nir_intrinsic_deref_atomic_imax);
   5403 
   5404       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5405    intrin->src[0] = nir_src_for_ssa(src0);
   5406    intrin->src[1] = nir_src_for_ssa(src1);
   5407    nir_intrinsic_set_access(intrin, indices.access);
   5408 
   5409    nir_builder_instr_insert(build, &intrin->instr);
   5410    return &intrin->dest.ssa;
   5411 }
   5412 static inline nir_ssa_def *
   5413 _nir_build_deref_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_imin_indices indices)
   5414 {
   5415    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5416       build->shader, nir_intrinsic_deref_atomic_imin);
   5417 
   5418       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5419    intrin->src[0] = nir_src_for_ssa(src0);
   5420    intrin->src[1] = nir_src_for_ssa(src1);
   5421    nir_intrinsic_set_access(intrin, indices.access);
   5422 
   5423    nir_builder_instr_insert(build, &intrin->instr);
   5424    return &intrin->dest.ssa;
   5425 }
   5426 static inline nir_ssa_def *
   5427 _nir_build_deref_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_or_indices indices)
   5428 {
   5429    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5430       build->shader, nir_intrinsic_deref_atomic_or);
   5431 
   5432       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5433    intrin->src[0] = nir_src_for_ssa(src0);
   5434    intrin->src[1] = nir_src_for_ssa(src1);
   5435    nir_intrinsic_set_access(intrin, indices.access);
   5436 
   5437    nir_builder_instr_insert(build, &intrin->instr);
   5438    return &intrin->dest.ssa;
   5439 }
   5440 static inline nir_ssa_def *
   5441 _nir_build_deref_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_umax_indices indices)
   5442 {
   5443    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5444       build->shader, nir_intrinsic_deref_atomic_umax);
   5445 
   5446       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5447    intrin->src[0] = nir_src_for_ssa(src0);
   5448    intrin->src[1] = nir_src_for_ssa(src1);
   5449    nir_intrinsic_set_access(intrin, indices.access);
   5450 
   5451    nir_builder_instr_insert(build, &intrin->instr);
   5452    return &intrin->dest.ssa;
   5453 }
   5454 static inline nir_ssa_def *
   5455 _nir_build_deref_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_umin_indices indices)
   5456 {
   5457    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5458       build->shader, nir_intrinsic_deref_atomic_umin);
   5459 
   5460       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5461    intrin->src[0] = nir_src_for_ssa(src0);
   5462    intrin->src[1] = nir_src_for_ssa(src1);
   5463    nir_intrinsic_set_access(intrin, indices.access);
   5464 
   5465    nir_builder_instr_insert(build, &intrin->instr);
   5466    return &intrin->dest.ssa;
   5467 }
   5468 static inline nir_ssa_def *
   5469 _nir_build_deref_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_deref_atomic_xor_indices indices)
   5470 {
   5471    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5472       build->shader, nir_intrinsic_deref_atomic_xor);
   5473 
   5474       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5475    intrin->src[0] = nir_src_for_ssa(src0);
   5476    intrin->src[1] = nir_src_for_ssa(src1);
   5477    nir_intrinsic_set_access(intrin, indices.access);
   5478 
   5479    nir_builder_instr_insert(build, &intrin->instr);
   5480    return &intrin->dest.ssa;
   5481 }
   5482 static inline nir_ssa_def *
   5483 _nir_build_deref_buffer_array_length(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_deref_buffer_array_length_indices indices)
   5484 {
   5485    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5486       build->shader, nir_intrinsic_deref_buffer_array_length);
   5487 
   5488       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5489    intrin->src[0] = nir_src_for_ssa(src0);
   5490    nir_intrinsic_set_access(intrin, indices.access);
   5491 
   5492    nir_builder_instr_insert(build, &intrin->instr);
   5493    return &intrin->dest.ssa;
   5494 }
   5495 static inline nir_ssa_def *
   5496 _nir_build_deref_mode_is(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_deref_mode_is_indices indices)
   5497 {
   5498    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5499       build->shader, nir_intrinsic_deref_mode_is);
   5500 
   5501       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5502    intrin->src[0] = nir_src_for_ssa(src0);
   5503    nir_intrinsic_set_memory_modes(intrin, indices.memory_modes);
   5504 
   5505    nir_builder_instr_insert(build, &intrin->instr);
   5506    return &intrin->dest.ssa;
   5507 }
   5508 static inline nir_intrinsic_instr *
   5509 _nir_build_discard(nir_builder *build)
   5510 {
   5511    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5512       build->shader, nir_intrinsic_discard);
   5513 
   5514 
   5515    nir_builder_instr_insert(build, &intrin->instr);
   5516    return intrin;
   5517 }
   5518 static inline nir_intrinsic_instr *
   5519 _nir_build_discard_if(nir_builder *build, nir_ssa_def *src0)
   5520 {
   5521    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5522       build->shader, nir_intrinsic_discard_if);
   5523 
   5524    intrin->src[0] = nir_src_for_ssa(src0);
   5525 
   5526    nir_builder_instr_insert(build, &intrin->instr);
   5527    return intrin;
   5528 }
   5529 static inline nir_ssa_def *
   5530 _nir_build_elect(nir_builder *build, unsigned bit_size)
   5531 {
   5532    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5533       build->shader, nir_intrinsic_elect);
   5534 
   5535       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5536 
   5537    nir_builder_instr_insert(build, &intrin->instr);
   5538    return &intrin->dest.ssa;
   5539 }
   5540 static inline nir_intrinsic_instr *
   5541 _nir_build_emit_vertex(nir_builder *build, struct _nir_emit_vertex_indices indices)
   5542 {
   5543    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5544       build->shader, nir_intrinsic_emit_vertex);
   5545 
   5546    nir_intrinsic_set_stream_id(intrin, indices.stream_id);
   5547 
   5548    nir_builder_instr_insert(build, &intrin->instr);
   5549    return intrin;
   5550 }
   5551 static inline nir_intrinsic_instr *
   5552 _nir_build_emit_vertex_with_counter(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_emit_vertex_with_counter_indices indices)
   5553 {
   5554    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5555       build->shader, nir_intrinsic_emit_vertex_with_counter);
   5556 
   5557    intrin->src[0] = nir_src_for_ssa(src0);
   5558    intrin->src[1] = nir_src_for_ssa(src1);
   5559    nir_intrinsic_set_stream_id(intrin, indices.stream_id);
   5560 
   5561    nir_builder_instr_insert(build, &intrin->instr);
   5562    return intrin;
   5563 }
   5564 static inline nir_intrinsic_instr *
   5565 _nir_build_end_invocation_interlock(nir_builder *build)
   5566 {
   5567    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5568       build->shader, nir_intrinsic_end_invocation_interlock);
   5569 
   5570 
   5571    nir_builder_instr_insert(build, &intrin->instr);
   5572    return intrin;
   5573 }
   5574 static inline nir_intrinsic_instr *
   5575 _nir_build_end_patch_ir3(nir_builder *build)
   5576 {
   5577    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5578       build->shader, nir_intrinsic_end_patch_ir3);
   5579 
   5580 
   5581    nir_builder_instr_insert(build, &intrin->instr);
   5582    return intrin;
   5583 }
   5584 static inline nir_intrinsic_instr *
   5585 _nir_build_end_primitive(nir_builder *build, struct _nir_end_primitive_indices indices)
   5586 {
   5587    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5588       build->shader, nir_intrinsic_end_primitive);
   5589 
   5590    nir_intrinsic_set_stream_id(intrin, indices.stream_id);
   5591 
   5592    nir_builder_instr_insert(build, &intrin->instr);
   5593    return intrin;
   5594 }
   5595 static inline nir_intrinsic_instr *
   5596 _nir_build_end_primitive_with_counter(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_end_primitive_with_counter_indices indices)
   5597 {
   5598    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5599       build->shader, nir_intrinsic_end_primitive_with_counter);
   5600 
   5601    intrin->src[0] = nir_src_for_ssa(src0);
   5602    intrin->src[1] = nir_src_for_ssa(src1);
   5603    nir_intrinsic_set_stream_id(intrin, indices.stream_id);
   5604 
   5605    nir_builder_instr_insert(build, &intrin->instr);
   5606    return intrin;
   5607 }
   5608 static inline nir_ssa_def *
   5609 _nir_build_exclusive_scan(nir_builder *build, nir_ssa_def *src0, struct _nir_exclusive_scan_indices indices)
   5610 {
   5611    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5612       build->shader, nir_intrinsic_exclusive_scan);
   5613 
   5614    intrin->num_components = src0->num_components;
   5615       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   5616    intrin->src[0] = nir_src_for_ssa(src0);
   5617    nir_intrinsic_set_reduction_op(intrin, indices.reduction_op);
   5618 
   5619    nir_builder_instr_insert(build, &intrin->instr);
   5620    return &intrin->dest.ssa;
   5621 }
   5622 static inline nir_intrinsic_instr *
   5623 _nir_build_execute_callable(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   5624 {
   5625    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5626       build->shader, nir_intrinsic_execute_callable);
   5627 
   5628    intrin->src[0] = nir_src_for_ssa(src0);
   5629    intrin->src[1] = nir_src_for_ssa(src1);
   5630 
   5631    nir_builder_instr_insert(build, &intrin->instr);
   5632    return intrin;
   5633 }
   5634 static inline nir_intrinsic_instr *
   5635 _nir_build_export_primitive_amd(nir_builder *build, nir_ssa_def *src0)
   5636 {
   5637    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5638       build->shader, nir_intrinsic_export_primitive_amd);
   5639 
   5640    intrin->src[0] = nir_src_for_ssa(src0);
   5641 
   5642    nir_builder_instr_insert(build, &intrin->instr);
   5643    return intrin;
   5644 }
   5645 static inline nir_intrinsic_instr *
   5646 _nir_build_export_vertex_amd(nir_builder *build)
   5647 {
   5648    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5649       build->shader, nir_intrinsic_export_vertex_amd);
   5650 
   5651 
   5652    nir_builder_instr_insert(build, &intrin->instr);
   5653    return intrin;
   5654 }
   5655 static inline nir_ssa_def *
   5656 _nir_build_first_invocation(nir_builder *build)
   5657 {
   5658    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5659       build->shader, nir_intrinsic_first_invocation);
   5660 
   5661       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   5662 
   5663    nir_builder_instr_insert(build, &intrin->instr);
   5664    return &intrin->dest.ssa;
   5665 }
   5666 static inline nir_ssa_def *
   5667 _nir_build_gds_atomic_add_amd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_gds_atomic_add_amd_indices indices)
   5668 {
   5669    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5670       build->shader, nir_intrinsic_gds_atomic_add_amd);
   5671 
   5672       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5673    intrin->src[0] = nir_src_for_ssa(src0);
   5674    intrin->src[1] = nir_src_for_ssa(src1);
   5675    intrin->src[2] = nir_src_for_ssa(src2);
   5676    nir_intrinsic_set_base(intrin, indices.base);
   5677 
   5678    nir_builder_instr_insert(build, &intrin->instr);
   5679    return &intrin->dest.ssa;
   5680 }
   5681 static inline nir_ssa_def *
   5682 _nir_build_get_ssbo_size(nir_builder *build, nir_ssa_def *src0, struct _nir_get_ssbo_size_indices indices)
   5683 {
   5684    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5685       build->shader, nir_intrinsic_get_ssbo_size);
   5686 
   5687       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   5688    intrin->src[0] = nir_src_for_ssa(src0);
   5689    nir_intrinsic_set_access(intrin, indices.access);
   5690 
   5691    nir_builder_instr_insert(build, &intrin->instr);
   5692    return &intrin->dest.ssa;
   5693 }
   5694 static inline nir_ssa_def *
   5695 _nir_build_get_ubo_size(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   5696 {
   5697    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5698       build->shader, nir_intrinsic_get_ubo_size);
   5699 
   5700       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5701    intrin->src[0] = nir_src_for_ssa(src0);
   5702 
   5703    nir_builder_instr_insert(build, &intrin->instr);
   5704    return &intrin->dest.ssa;
   5705 }
   5706 static inline nir_ssa_def *
   5707 _nir_build_global_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_add_indices indices)
   5708 {
   5709    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5710       build->shader, nir_intrinsic_global_atomic_add);
   5711 
   5712       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5713    intrin->src[0] = nir_src_for_ssa(src0);
   5714    intrin->src[1] = nir_src_for_ssa(src1);
   5715    nir_intrinsic_set_base(intrin, indices.base);
   5716 
   5717    nir_builder_instr_insert(build, &intrin->instr);
   5718    return &intrin->dest.ssa;
   5719 }
   5720 static inline nir_ssa_def *
   5721 _nir_build_global_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_and_indices indices)
   5722 {
   5723    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5724       build->shader, nir_intrinsic_global_atomic_and);
   5725 
   5726       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5727    intrin->src[0] = nir_src_for_ssa(src0);
   5728    intrin->src[1] = nir_src_for_ssa(src1);
   5729    nir_intrinsic_set_base(intrin, indices.base);
   5730 
   5731    nir_builder_instr_insert(build, &intrin->instr);
   5732    return &intrin->dest.ssa;
   5733 }
   5734 static inline nir_ssa_def *
   5735 _nir_build_global_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_global_atomic_comp_swap_indices indices)
   5736 {
   5737    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5738       build->shader, nir_intrinsic_global_atomic_comp_swap);
   5739 
   5740       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5741    intrin->src[0] = nir_src_for_ssa(src0);
   5742    intrin->src[1] = nir_src_for_ssa(src1);
   5743    intrin->src[2] = nir_src_for_ssa(src2);
   5744    nir_intrinsic_set_base(intrin, indices.base);
   5745 
   5746    nir_builder_instr_insert(build, &intrin->instr);
   5747    return &intrin->dest.ssa;
   5748 }
   5749 static inline nir_ssa_def *
   5750 _nir_build_global_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_exchange_indices indices)
   5751 {
   5752    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5753       build->shader, nir_intrinsic_global_atomic_exchange);
   5754 
   5755       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5756    intrin->src[0] = nir_src_for_ssa(src0);
   5757    intrin->src[1] = nir_src_for_ssa(src1);
   5758    nir_intrinsic_set_base(intrin, indices.base);
   5759 
   5760    nir_builder_instr_insert(build, &intrin->instr);
   5761    return &intrin->dest.ssa;
   5762 }
   5763 static inline nir_ssa_def *
   5764 _nir_build_global_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_fadd_indices indices)
   5765 {
   5766    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5767       build->shader, nir_intrinsic_global_atomic_fadd);
   5768 
   5769       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5770    intrin->src[0] = nir_src_for_ssa(src0);
   5771    intrin->src[1] = nir_src_for_ssa(src1);
   5772    nir_intrinsic_set_base(intrin, indices.base);
   5773 
   5774    nir_builder_instr_insert(build, &intrin->instr);
   5775    return &intrin->dest.ssa;
   5776 }
   5777 static inline nir_ssa_def *
   5778 _nir_build_global_atomic_fcomp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_global_atomic_fcomp_swap_indices indices)
   5779 {
   5780    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5781       build->shader, nir_intrinsic_global_atomic_fcomp_swap);
   5782 
   5783       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5784    intrin->src[0] = nir_src_for_ssa(src0);
   5785    intrin->src[1] = nir_src_for_ssa(src1);
   5786    intrin->src[2] = nir_src_for_ssa(src2);
   5787    nir_intrinsic_set_base(intrin, indices.base);
   5788 
   5789    nir_builder_instr_insert(build, &intrin->instr);
   5790    return &intrin->dest.ssa;
   5791 }
   5792 static inline nir_ssa_def *
   5793 _nir_build_global_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_fmax_indices indices)
   5794 {
   5795    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5796       build->shader, nir_intrinsic_global_atomic_fmax);
   5797 
   5798       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5799    intrin->src[0] = nir_src_for_ssa(src0);
   5800    intrin->src[1] = nir_src_for_ssa(src1);
   5801    nir_intrinsic_set_base(intrin, indices.base);
   5802 
   5803    nir_builder_instr_insert(build, &intrin->instr);
   5804    return &intrin->dest.ssa;
   5805 }
   5806 static inline nir_ssa_def *
   5807 _nir_build_global_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_fmin_indices indices)
   5808 {
   5809    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5810       build->shader, nir_intrinsic_global_atomic_fmin);
   5811 
   5812       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5813    intrin->src[0] = nir_src_for_ssa(src0);
   5814    intrin->src[1] = nir_src_for_ssa(src1);
   5815    nir_intrinsic_set_base(intrin, indices.base);
   5816 
   5817    nir_builder_instr_insert(build, &intrin->instr);
   5818    return &intrin->dest.ssa;
   5819 }
   5820 static inline nir_ssa_def *
   5821 _nir_build_global_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_imax_indices indices)
   5822 {
   5823    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5824       build->shader, nir_intrinsic_global_atomic_imax);
   5825 
   5826       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5827    intrin->src[0] = nir_src_for_ssa(src0);
   5828    intrin->src[1] = nir_src_for_ssa(src1);
   5829    nir_intrinsic_set_base(intrin, indices.base);
   5830 
   5831    nir_builder_instr_insert(build, &intrin->instr);
   5832    return &intrin->dest.ssa;
   5833 }
   5834 static inline nir_ssa_def *
   5835 _nir_build_global_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_imin_indices indices)
   5836 {
   5837    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5838       build->shader, nir_intrinsic_global_atomic_imin);
   5839 
   5840       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5841    intrin->src[0] = nir_src_for_ssa(src0);
   5842    intrin->src[1] = nir_src_for_ssa(src1);
   5843    nir_intrinsic_set_base(intrin, indices.base);
   5844 
   5845    nir_builder_instr_insert(build, &intrin->instr);
   5846    return &intrin->dest.ssa;
   5847 }
   5848 static inline nir_ssa_def *
   5849 _nir_build_global_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_or_indices indices)
   5850 {
   5851    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5852       build->shader, nir_intrinsic_global_atomic_or);
   5853 
   5854       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5855    intrin->src[0] = nir_src_for_ssa(src0);
   5856    intrin->src[1] = nir_src_for_ssa(src1);
   5857    nir_intrinsic_set_base(intrin, indices.base);
   5858 
   5859    nir_builder_instr_insert(build, &intrin->instr);
   5860    return &intrin->dest.ssa;
   5861 }
   5862 static inline nir_ssa_def *
   5863 _nir_build_global_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_umax_indices indices)
   5864 {
   5865    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5866       build->shader, nir_intrinsic_global_atomic_umax);
   5867 
   5868       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5869    intrin->src[0] = nir_src_for_ssa(src0);
   5870    intrin->src[1] = nir_src_for_ssa(src1);
   5871    nir_intrinsic_set_base(intrin, indices.base);
   5872 
   5873    nir_builder_instr_insert(build, &intrin->instr);
   5874    return &intrin->dest.ssa;
   5875 }
   5876 static inline nir_ssa_def *
   5877 _nir_build_global_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_umin_indices indices)
   5878 {
   5879    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5880       build->shader, nir_intrinsic_global_atomic_umin);
   5881 
   5882       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5883    intrin->src[0] = nir_src_for_ssa(src0);
   5884    intrin->src[1] = nir_src_for_ssa(src1);
   5885    nir_intrinsic_set_base(intrin, indices.base);
   5886 
   5887    nir_builder_instr_insert(build, &intrin->instr);
   5888    return &intrin->dest.ssa;
   5889 }
   5890 static inline nir_ssa_def *
   5891 _nir_build_global_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_global_atomic_xor_indices indices)
   5892 {
   5893    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5894       build->shader, nir_intrinsic_global_atomic_xor);
   5895 
   5896       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5897    intrin->src[0] = nir_src_for_ssa(src0);
   5898    intrin->src[1] = nir_src_for_ssa(src1);
   5899    nir_intrinsic_set_base(intrin, indices.base);
   5900 
   5901    nir_builder_instr_insert(build, &intrin->instr);
   5902    return &intrin->dest.ssa;
   5903 }
   5904 static inline nir_intrinsic_instr *
   5905 _nir_build_group_memory_barrier(nir_builder *build)
   5906 {
   5907    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5908       build->shader, nir_intrinsic_group_memory_barrier);
   5909 
   5910 
   5911    nir_builder_instr_insert(build, &intrin->instr);
   5912    return intrin;
   5913 }
   5914 static inline nir_ssa_def *
   5915 _nir_build_has_input_primitive_amd(nir_builder *build)
   5916 {
   5917    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5918       build->shader, nir_intrinsic_has_input_primitive_amd);
   5919 
   5920       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   5921 
   5922    nir_builder_instr_insert(build, &intrin->instr);
   5923    return &intrin->dest.ssa;
   5924 }
   5925 static inline nir_ssa_def *
   5926 _nir_build_has_input_vertex_amd(nir_builder *build)
   5927 {
   5928    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5929       build->shader, nir_intrinsic_has_input_vertex_amd);
   5930 
   5931       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   5932 
   5933    nir_builder_instr_insert(build, &intrin->instr);
   5934    return &intrin->dest.ssa;
   5935 }
   5936 static inline nir_intrinsic_instr *
   5937 _nir_build_ignore_ray_intersection(nir_builder *build)
   5938 {
   5939    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5940       build->shader, nir_intrinsic_ignore_ray_intersection);
   5941 
   5942 
   5943    nir_builder_instr_insert(build, &intrin->instr);
   5944    return intrin;
   5945 }
   5946 static inline nir_ssa_def *
   5947 _nir_build_image_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_add_indices indices)
   5948 {
   5949    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5950       build->shader, nir_intrinsic_image_atomic_add);
   5951 
   5952       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5953    intrin->src[0] = nir_src_for_ssa(src0);
   5954    intrin->src[1] = nir_src_for_ssa(src1);
   5955    intrin->src[2] = nir_src_for_ssa(src2);
   5956    intrin->src[3] = nir_src_for_ssa(src3);
   5957    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5958    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5959    nir_intrinsic_set_format(intrin, indices.format);
   5960    nir_intrinsic_set_access(intrin, indices.access);
   5961 
   5962    nir_builder_instr_insert(build, &intrin->instr);
   5963    return &intrin->dest.ssa;
   5964 }
   5965 static inline nir_ssa_def *
   5966 _nir_build_image_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_and_indices indices)
   5967 {
   5968    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5969       build->shader, nir_intrinsic_image_atomic_and);
   5970 
   5971       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5972    intrin->src[0] = nir_src_for_ssa(src0);
   5973    intrin->src[1] = nir_src_for_ssa(src1);
   5974    intrin->src[2] = nir_src_for_ssa(src2);
   5975    intrin->src[3] = nir_src_for_ssa(src3);
   5976    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5977    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5978    nir_intrinsic_set_format(intrin, indices.format);
   5979    nir_intrinsic_set_access(intrin, indices.access);
   5980 
   5981    nir_builder_instr_insert(build, &intrin->instr);
   5982    return &intrin->dest.ssa;
   5983 }
   5984 static inline nir_ssa_def *
   5985 _nir_build_image_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_image_atomic_comp_swap_indices indices)
   5986 {
   5987    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   5988       build->shader, nir_intrinsic_image_atomic_comp_swap);
   5989 
   5990       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   5991    intrin->src[0] = nir_src_for_ssa(src0);
   5992    intrin->src[1] = nir_src_for_ssa(src1);
   5993    intrin->src[2] = nir_src_for_ssa(src2);
   5994    intrin->src[3] = nir_src_for_ssa(src3);
   5995    intrin->src[4] = nir_src_for_ssa(src4);
   5996    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   5997    nir_intrinsic_set_image_array(intrin, indices.image_array);
   5998    nir_intrinsic_set_format(intrin, indices.format);
   5999    nir_intrinsic_set_access(intrin, indices.access);
   6000 
   6001    nir_builder_instr_insert(build, &intrin->instr);
   6002    return &intrin->dest.ssa;
   6003 }
   6004 static inline nir_ssa_def *
   6005 _nir_build_image_atomic_dec_wrap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_dec_wrap_indices indices)
   6006 {
   6007    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6008       build->shader, nir_intrinsic_image_atomic_dec_wrap);
   6009 
   6010       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6011    intrin->src[0] = nir_src_for_ssa(src0);
   6012    intrin->src[1] = nir_src_for_ssa(src1);
   6013    intrin->src[2] = nir_src_for_ssa(src2);
   6014    intrin->src[3] = nir_src_for_ssa(src3);
   6015    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6016    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6017    nir_intrinsic_set_format(intrin, indices.format);
   6018    nir_intrinsic_set_access(intrin, indices.access);
   6019 
   6020    nir_builder_instr_insert(build, &intrin->instr);
   6021    return &intrin->dest.ssa;
   6022 }
   6023 static inline nir_ssa_def *
   6024 _nir_build_image_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_exchange_indices indices)
   6025 {
   6026    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6027       build->shader, nir_intrinsic_image_atomic_exchange);
   6028 
   6029       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6030    intrin->src[0] = nir_src_for_ssa(src0);
   6031    intrin->src[1] = nir_src_for_ssa(src1);
   6032    intrin->src[2] = nir_src_for_ssa(src2);
   6033    intrin->src[3] = nir_src_for_ssa(src3);
   6034    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6035    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6036    nir_intrinsic_set_format(intrin, indices.format);
   6037    nir_intrinsic_set_access(intrin, indices.access);
   6038 
   6039    nir_builder_instr_insert(build, &intrin->instr);
   6040    return &intrin->dest.ssa;
   6041 }
   6042 static inline nir_ssa_def *
   6043 _nir_build_image_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_fadd_indices indices)
   6044 {
   6045    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6046       build->shader, nir_intrinsic_image_atomic_fadd);
   6047 
   6048       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6049    intrin->src[0] = nir_src_for_ssa(src0);
   6050    intrin->src[1] = nir_src_for_ssa(src1);
   6051    intrin->src[2] = nir_src_for_ssa(src2);
   6052    intrin->src[3] = nir_src_for_ssa(src3);
   6053    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6054    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6055    nir_intrinsic_set_format(intrin, indices.format);
   6056    nir_intrinsic_set_access(intrin, indices.access);
   6057 
   6058    nir_builder_instr_insert(build, &intrin->instr);
   6059    return &intrin->dest.ssa;
   6060 }
   6061 static inline nir_ssa_def *
   6062 _nir_build_image_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_fmax_indices indices)
   6063 {
   6064    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6065       build->shader, nir_intrinsic_image_atomic_fmax);
   6066 
   6067       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6068    intrin->src[0] = nir_src_for_ssa(src0);
   6069    intrin->src[1] = nir_src_for_ssa(src1);
   6070    intrin->src[2] = nir_src_for_ssa(src2);
   6071    intrin->src[3] = nir_src_for_ssa(src3);
   6072    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6073    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6074    nir_intrinsic_set_format(intrin, indices.format);
   6075    nir_intrinsic_set_access(intrin, indices.access);
   6076 
   6077    nir_builder_instr_insert(build, &intrin->instr);
   6078    return &intrin->dest.ssa;
   6079 }
   6080 static inline nir_ssa_def *
   6081 _nir_build_image_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_fmin_indices indices)
   6082 {
   6083    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6084       build->shader, nir_intrinsic_image_atomic_fmin);
   6085 
   6086       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6087    intrin->src[0] = nir_src_for_ssa(src0);
   6088    intrin->src[1] = nir_src_for_ssa(src1);
   6089    intrin->src[2] = nir_src_for_ssa(src2);
   6090    intrin->src[3] = nir_src_for_ssa(src3);
   6091    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6092    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6093    nir_intrinsic_set_format(intrin, indices.format);
   6094    nir_intrinsic_set_access(intrin, indices.access);
   6095 
   6096    nir_builder_instr_insert(build, &intrin->instr);
   6097    return &intrin->dest.ssa;
   6098 }
   6099 static inline nir_ssa_def *
   6100 _nir_build_image_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_imax_indices indices)
   6101 {
   6102    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6103       build->shader, nir_intrinsic_image_atomic_imax);
   6104 
   6105       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6106    intrin->src[0] = nir_src_for_ssa(src0);
   6107    intrin->src[1] = nir_src_for_ssa(src1);
   6108    intrin->src[2] = nir_src_for_ssa(src2);
   6109    intrin->src[3] = nir_src_for_ssa(src3);
   6110    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6111    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6112    nir_intrinsic_set_format(intrin, indices.format);
   6113    nir_intrinsic_set_access(intrin, indices.access);
   6114 
   6115    nir_builder_instr_insert(build, &intrin->instr);
   6116    return &intrin->dest.ssa;
   6117 }
   6118 static inline nir_ssa_def *
   6119 _nir_build_image_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_imin_indices indices)
   6120 {
   6121    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6122       build->shader, nir_intrinsic_image_atomic_imin);
   6123 
   6124       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6125    intrin->src[0] = nir_src_for_ssa(src0);
   6126    intrin->src[1] = nir_src_for_ssa(src1);
   6127    intrin->src[2] = nir_src_for_ssa(src2);
   6128    intrin->src[3] = nir_src_for_ssa(src3);
   6129    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6130    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6131    nir_intrinsic_set_format(intrin, indices.format);
   6132    nir_intrinsic_set_access(intrin, indices.access);
   6133 
   6134    nir_builder_instr_insert(build, &intrin->instr);
   6135    return &intrin->dest.ssa;
   6136 }
   6137 static inline nir_ssa_def *
   6138 _nir_build_image_atomic_inc_wrap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_inc_wrap_indices indices)
   6139 {
   6140    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6141       build->shader, nir_intrinsic_image_atomic_inc_wrap);
   6142 
   6143       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6144    intrin->src[0] = nir_src_for_ssa(src0);
   6145    intrin->src[1] = nir_src_for_ssa(src1);
   6146    intrin->src[2] = nir_src_for_ssa(src2);
   6147    intrin->src[3] = nir_src_for_ssa(src3);
   6148    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6149    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6150    nir_intrinsic_set_format(intrin, indices.format);
   6151    nir_intrinsic_set_access(intrin, indices.access);
   6152 
   6153    nir_builder_instr_insert(build, &intrin->instr);
   6154    return &intrin->dest.ssa;
   6155 }
   6156 static inline nir_ssa_def *
   6157 _nir_build_image_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_or_indices indices)
   6158 {
   6159    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6160       build->shader, nir_intrinsic_image_atomic_or);
   6161 
   6162       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6163    intrin->src[0] = nir_src_for_ssa(src0);
   6164    intrin->src[1] = nir_src_for_ssa(src1);
   6165    intrin->src[2] = nir_src_for_ssa(src2);
   6166    intrin->src[3] = nir_src_for_ssa(src3);
   6167    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6168    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6169    nir_intrinsic_set_format(intrin, indices.format);
   6170    nir_intrinsic_set_access(intrin, indices.access);
   6171 
   6172    nir_builder_instr_insert(build, &intrin->instr);
   6173    return &intrin->dest.ssa;
   6174 }
   6175 static inline nir_ssa_def *
   6176 _nir_build_image_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_umax_indices indices)
   6177 {
   6178    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6179       build->shader, nir_intrinsic_image_atomic_umax);
   6180 
   6181       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6182    intrin->src[0] = nir_src_for_ssa(src0);
   6183    intrin->src[1] = nir_src_for_ssa(src1);
   6184    intrin->src[2] = nir_src_for_ssa(src2);
   6185    intrin->src[3] = nir_src_for_ssa(src3);
   6186    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6187    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6188    nir_intrinsic_set_format(intrin, indices.format);
   6189    nir_intrinsic_set_access(intrin, indices.access);
   6190 
   6191    nir_builder_instr_insert(build, &intrin->instr);
   6192    return &intrin->dest.ssa;
   6193 }
   6194 static inline nir_ssa_def *
   6195 _nir_build_image_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_umin_indices indices)
   6196 {
   6197    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6198       build->shader, nir_intrinsic_image_atomic_umin);
   6199 
   6200       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6201    intrin->src[0] = nir_src_for_ssa(src0);
   6202    intrin->src[1] = nir_src_for_ssa(src1);
   6203    intrin->src[2] = nir_src_for_ssa(src2);
   6204    intrin->src[3] = nir_src_for_ssa(src3);
   6205    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6206    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6207    nir_intrinsic_set_format(intrin, indices.format);
   6208    nir_intrinsic_set_access(intrin, indices.access);
   6209 
   6210    nir_builder_instr_insert(build, &intrin->instr);
   6211    return &intrin->dest.ssa;
   6212 }
   6213 static inline nir_ssa_def *
   6214 _nir_build_image_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_atomic_xor_indices indices)
   6215 {
   6216    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6217       build->shader, nir_intrinsic_image_atomic_xor);
   6218 
   6219       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6220    intrin->src[0] = nir_src_for_ssa(src0);
   6221    intrin->src[1] = nir_src_for_ssa(src1);
   6222    intrin->src[2] = nir_src_for_ssa(src2);
   6223    intrin->src[3] = nir_src_for_ssa(src3);
   6224    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6225    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6226    nir_intrinsic_set_format(intrin, indices.format);
   6227    nir_intrinsic_set_access(intrin, indices.access);
   6228 
   6229    nir_builder_instr_insert(build, &intrin->instr);
   6230    return &intrin->dest.ssa;
   6231 }
   6232 static inline nir_ssa_def *
   6233 _nir_build_image_deref_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_add_indices indices)
   6234 {
   6235    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6236       build->shader, nir_intrinsic_image_deref_atomic_add);
   6237 
   6238       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6239    intrin->src[0] = nir_src_for_ssa(src0);
   6240    intrin->src[1] = nir_src_for_ssa(src1);
   6241    intrin->src[2] = nir_src_for_ssa(src2);
   6242    intrin->src[3] = nir_src_for_ssa(src3);
   6243    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6244    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6245    nir_intrinsic_set_format(intrin, indices.format);
   6246    nir_intrinsic_set_access(intrin, indices.access);
   6247 
   6248    nir_builder_instr_insert(build, &intrin->instr);
   6249    return &intrin->dest.ssa;
   6250 }
   6251 static inline nir_ssa_def *
   6252 _nir_build_image_deref_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_and_indices indices)
   6253 {
   6254    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6255       build->shader, nir_intrinsic_image_deref_atomic_and);
   6256 
   6257       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6258    intrin->src[0] = nir_src_for_ssa(src0);
   6259    intrin->src[1] = nir_src_for_ssa(src1);
   6260    intrin->src[2] = nir_src_for_ssa(src2);
   6261    intrin->src[3] = nir_src_for_ssa(src3);
   6262    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6263    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6264    nir_intrinsic_set_format(intrin, indices.format);
   6265    nir_intrinsic_set_access(intrin, indices.access);
   6266 
   6267    nir_builder_instr_insert(build, &intrin->instr);
   6268    return &intrin->dest.ssa;
   6269 }
   6270 static inline nir_ssa_def *
   6271 _nir_build_image_deref_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_image_deref_atomic_comp_swap_indices indices)
   6272 {
   6273    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6274       build->shader, nir_intrinsic_image_deref_atomic_comp_swap);
   6275 
   6276       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6277    intrin->src[0] = nir_src_for_ssa(src0);
   6278    intrin->src[1] = nir_src_for_ssa(src1);
   6279    intrin->src[2] = nir_src_for_ssa(src2);
   6280    intrin->src[3] = nir_src_for_ssa(src3);
   6281    intrin->src[4] = nir_src_for_ssa(src4);
   6282    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6283    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6284    nir_intrinsic_set_format(intrin, indices.format);
   6285    nir_intrinsic_set_access(intrin, indices.access);
   6286 
   6287    nir_builder_instr_insert(build, &intrin->instr);
   6288    return &intrin->dest.ssa;
   6289 }
   6290 static inline nir_ssa_def *
   6291 _nir_build_image_deref_atomic_dec_wrap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_dec_wrap_indices indices)
   6292 {
   6293    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6294       build->shader, nir_intrinsic_image_deref_atomic_dec_wrap);
   6295 
   6296       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6297    intrin->src[0] = nir_src_for_ssa(src0);
   6298    intrin->src[1] = nir_src_for_ssa(src1);
   6299    intrin->src[2] = nir_src_for_ssa(src2);
   6300    intrin->src[3] = nir_src_for_ssa(src3);
   6301    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6302    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6303    nir_intrinsic_set_format(intrin, indices.format);
   6304    nir_intrinsic_set_access(intrin, indices.access);
   6305 
   6306    nir_builder_instr_insert(build, &intrin->instr);
   6307    return &intrin->dest.ssa;
   6308 }
   6309 static inline nir_ssa_def *
   6310 _nir_build_image_deref_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_exchange_indices indices)
   6311 {
   6312    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6313       build->shader, nir_intrinsic_image_deref_atomic_exchange);
   6314 
   6315       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6316    intrin->src[0] = nir_src_for_ssa(src0);
   6317    intrin->src[1] = nir_src_for_ssa(src1);
   6318    intrin->src[2] = nir_src_for_ssa(src2);
   6319    intrin->src[3] = nir_src_for_ssa(src3);
   6320    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6321    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6322    nir_intrinsic_set_format(intrin, indices.format);
   6323    nir_intrinsic_set_access(intrin, indices.access);
   6324 
   6325    nir_builder_instr_insert(build, &intrin->instr);
   6326    return &intrin->dest.ssa;
   6327 }
   6328 static inline nir_ssa_def *
   6329 _nir_build_image_deref_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_fadd_indices indices)
   6330 {
   6331    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6332       build->shader, nir_intrinsic_image_deref_atomic_fadd);
   6333 
   6334       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6335    intrin->src[0] = nir_src_for_ssa(src0);
   6336    intrin->src[1] = nir_src_for_ssa(src1);
   6337    intrin->src[2] = nir_src_for_ssa(src2);
   6338    intrin->src[3] = nir_src_for_ssa(src3);
   6339    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6340    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6341    nir_intrinsic_set_format(intrin, indices.format);
   6342    nir_intrinsic_set_access(intrin, indices.access);
   6343 
   6344    nir_builder_instr_insert(build, &intrin->instr);
   6345    return &intrin->dest.ssa;
   6346 }
   6347 static inline nir_ssa_def *
   6348 _nir_build_image_deref_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_fmax_indices indices)
   6349 {
   6350    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6351       build->shader, nir_intrinsic_image_deref_atomic_fmax);
   6352 
   6353       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6354    intrin->src[0] = nir_src_for_ssa(src0);
   6355    intrin->src[1] = nir_src_for_ssa(src1);
   6356    intrin->src[2] = nir_src_for_ssa(src2);
   6357    intrin->src[3] = nir_src_for_ssa(src3);
   6358    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6359    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6360    nir_intrinsic_set_format(intrin, indices.format);
   6361    nir_intrinsic_set_access(intrin, indices.access);
   6362 
   6363    nir_builder_instr_insert(build, &intrin->instr);
   6364    return &intrin->dest.ssa;
   6365 }
   6366 static inline nir_ssa_def *
   6367 _nir_build_image_deref_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_fmin_indices indices)
   6368 {
   6369    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6370       build->shader, nir_intrinsic_image_deref_atomic_fmin);
   6371 
   6372       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6373    intrin->src[0] = nir_src_for_ssa(src0);
   6374    intrin->src[1] = nir_src_for_ssa(src1);
   6375    intrin->src[2] = nir_src_for_ssa(src2);
   6376    intrin->src[3] = nir_src_for_ssa(src3);
   6377    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6378    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6379    nir_intrinsic_set_format(intrin, indices.format);
   6380    nir_intrinsic_set_access(intrin, indices.access);
   6381 
   6382    nir_builder_instr_insert(build, &intrin->instr);
   6383    return &intrin->dest.ssa;
   6384 }
   6385 static inline nir_ssa_def *
   6386 _nir_build_image_deref_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_imax_indices indices)
   6387 {
   6388    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6389       build->shader, nir_intrinsic_image_deref_atomic_imax);
   6390 
   6391       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6392    intrin->src[0] = nir_src_for_ssa(src0);
   6393    intrin->src[1] = nir_src_for_ssa(src1);
   6394    intrin->src[2] = nir_src_for_ssa(src2);
   6395    intrin->src[3] = nir_src_for_ssa(src3);
   6396    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6397    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6398    nir_intrinsic_set_format(intrin, indices.format);
   6399    nir_intrinsic_set_access(intrin, indices.access);
   6400 
   6401    nir_builder_instr_insert(build, &intrin->instr);
   6402    return &intrin->dest.ssa;
   6403 }
   6404 static inline nir_ssa_def *
   6405 _nir_build_image_deref_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_imin_indices indices)
   6406 {
   6407    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6408       build->shader, nir_intrinsic_image_deref_atomic_imin);
   6409 
   6410       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6411    intrin->src[0] = nir_src_for_ssa(src0);
   6412    intrin->src[1] = nir_src_for_ssa(src1);
   6413    intrin->src[2] = nir_src_for_ssa(src2);
   6414    intrin->src[3] = nir_src_for_ssa(src3);
   6415    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6416    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6417    nir_intrinsic_set_format(intrin, indices.format);
   6418    nir_intrinsic_set_access(intrin, indices.access);
   6419 
   6420    nir_builder_instr_insert(build, &intrin->instr);
   6421    return &intrin->dest.ssa;
   6422 }
   6423 static inline nir_ssa_def *
   6424 _nir_build_image_deref_atomic_inc_wrap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_inc_wrap_indices indices)
   6425 {
   6426    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6427       build->shader, nir_intrinsic_image_deref_atomic_inc_wrap);
   6428 
   6429       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6430    intrin->src[0] = nir_src_for_ssa(src0);
   6431    intrin->src[1] = nir_src_for_ssa(src1);
   6432    intrin->src[2] = nir_src_for_ssa(src2);
   6433    intrin->src[3] = nir_src_for_ssa(src3);
   6434    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6435    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6436    nir_intrinsic_set_format(intrin, indices.format);
   6437    nir_intrinsic_set_access(intrin, indices.access);
   6438 
   6439    nir_builder_instr_insert(build, &intrin->instr);
   6440    return &intrin->dest.ssa;
   6441 }
   6442 static inline nir_ssa_def *
   6443 _nir_build_image_deref_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_or_indices indices)
   6444 {
   6445    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6446       build->shader, nir_intrinsic_image_deref_atomic_or);
   6447 
   6448       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6449    intrin->src[0] = nir_src_for_ssa(src0);
   6450    intrin->src[1] = nir_src_for_ssa(src1);
   6451    intrin->src[2] = nir_src_for_ssa(src2);
   6452    intrin->src[3] = nir_src_for_ssa(src3);
   6453    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6454    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6455    nir_intrinsic_set_format(intrin, indices.format);
   6456    nir_intrinsic_set_access(intrin, indices.access);
   6457 
   6458    nir_builder_instr_insert(build, &intrin->instr);
   6459    return &intrin->dest.ssa;
   6460 }
   6461 static inline nir_ssa_def *
   6462 _nir_build_image_deref_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_umax_indices indices)
   6463 {
   6464    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6465       build->shader, nir_intrinsic_image_deref_atomic_umax);
   6466 
   6467       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6468    intrin->src[0] = nir_src_for_ssa(src0);
   6469    intrin->src[1] = nir_src_for_ssa(src1);
   6470    intrin->src[2] = nir_src_for_ssa(src2);
   6471    intrin->src[3] = nir_src_for_ssa(src3);
   6472    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6473    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6474    nir_intrinsic_set_format(intrin, indices.format);
   6475    nir_intrinsic_set_access(intrin, indices.access);
   6476 
   6477    nir_builder_instr_insert(build, &intrin->instr);
   6478    return &intrin->dest.ssa;
   6479 }
   6480 static inline nir_ssa_def *
   6481 _nir_build_image_deref_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_umin_indices indices)
   6482 {
   6483    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6484       build->shader, nir_intrinsic_image_deref_atomic_umin);
   6485 
   6486       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6487    intrin->src[0] = nir_src_for_ssa(src0);
   6488    intrin->src[1] = nir_src_for_ssa(src1);
   6489    intrin->src[2] = nir_src_for_ssa(src2);
   6490    intrin->src[3] = nir_src_for_ssa(src3);
   6491    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6492    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6493    nir_intrinsic_set_format(intrin, indices.format);
   6494    nir_intrinsic_set_access(intrin, indices.access);
   6495 
   6496    nir_builder_instr_insert(build, &intrin->instr);
   6497    return &intrin->dest.ssa;
   6498 }
   6499 static inline nir_ssa_def *
   6500 _nir_build_image_deref_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_atomic_xor_indices indices)
   6501 {
   6502    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6503       build->shader, nir_intrinsic_image_deref_atomic_xor);
   6504 
   6505       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6506    intrin->src[0] = nir_src_for_ssa(src0);
   6507    intrin->src[1] = nir_src_for_ssa(src1);
   6508    intrin->src[2] = nir_src_for_ssa(src2);
   6509    intrin->src[3] = nir_src_for_ssa(src3);
   6510    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6511    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6512    nir_intrinsic_set_format(intrin, indices.format);
   6513    nir_intrinsic_set_access(intrin, indices.access);
   6514 
   6515    nir_builder_instr_insert(build, &intrin->instr);
   6516    return &intrin->dest.ssa;
   6517 }
   6518 static inline nir_ssa_def *
   6519 _nir_build_image_deref_format(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_deref_format_indices indices)
   6520 {
   6521    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6522       build->shader, nir_intrinsic_image_deref_format);
   6523 
   6524       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6525    intrin->src[0] = nir_src_for_ssa(src0);
   6526    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6527    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6528    nir_intrinsic_set_format(intrin, indices.format);
   6529    nir_intrinsic_set_access(intrin, indices.access);
   6530 
   6531    nir_builder_instr_insert(build, &intrin->instr);
   6532    return &intrin->dest.ssa;
   6533 }
   6534 static inline nir_ssa_def *
   6535 _nir_build_image_deref_load(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_load_indices indices)
   6536 {
   6537    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6538       build->shader, nir_intrinsic_image_deref_load);
   6539 
   6540    intrin->num_components = num_components;
   6541       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6542    intrin->src[0] = nir_src_for_ssa(src0);
   6543    intrin->src[1] = nir_src_for_ssa(src1);
   6544    intrin->src[2] = nir_src_for_ssa(src2);
   6545    intrin->src[3] = nir_src_for_ssa(src3);
   6546    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6547    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6548    nir_intrinsic_set_format(intrin, indices.format);
   6549    nir_intrinsic_set_access(intrin, indices.access);
   6550    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   6551 
   6552    nir_builder_instr_insert(build, &intrin->instr);
   6553    return &intrin->dest.ssa;
   6554 }
   6555 static inline nir_ssa_def *
   6556 _nir_build_image_deref_load_param_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_deref_load_param_intel_indices indices)
   6557 {
   6558    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6559       build->shader, nir_intrinsic_image_deref_load_param_intel);
   6560 
   6561    intrin->num_components = num_components;
   6562       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6563    intrin->src[0] = nir_src_for_ssa(src0);
   6564    nir_intrinsic_set_base(intrin, indices.base);
   6565 
   6566    nir_builder_instr_insert(build, &intrin->instr);
   6567    return &intrin->dest.ssa;
   6568 }
   6569 static inline nir_ssa_def *
   6570 _nir_build_image_deref_load_raw_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_image_deref_load_raw_intel_indices indices)
   6571 {
   6572    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6573       build->shader, nir_intrinsic_image_deref_load_raw_intel);
   6574 
   6575    intrin->num_components = num_components;
   6576       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6577    intrin->src[0] = nir_src_for_ssa(src0);
   6578    intrin->src[1] = nir_src_for_ssa(src1);
   6579    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6580    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6581    nir_intrinsic_set_format(intrin, indices.format);
   6582    nir_intrinsic_set_access(intrin, indices.access);
   6583 
   6584    nir_builder_instr_insert(build, &intrin->instr);
   6585    return &intrin->dest.ssa;
   6586 }
   6587 static inline nir_ssa_def *
   6588 _nir_build_image_deref_order(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_deref_order_indices indices)
   6589 {
   6590    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6591       build->shader, nir_intrinsic_image_deref_order);
   6592 
   6593       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6594    intrin->src[0] = nir_src_for_ssa(src0);
   6595    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6596    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6597    nir_intrinsic_set_format(intrin, indices.format);
   6598    nir_intrinsic_set_access(intrin, indices.access);
   6599 
   6600    nir_builder_instr_insert(build, &intrin->instr);
   6601    return &intrin->dest.ssa;
   6602 }
   6603 static inline nir_ssa_def *
   6604 _nir_build_image_deref_samples(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_deref_samples_indices indices)
   6605 {
   6606    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6607       build->shader, nir_intrinsic_image_deref_samples);
   6608 
   6609       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6610    intrin->src[0] = nir_src_for_ssa(src0);
   6611    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6612    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6613    nir_intrinsic_set_format(intrin, indices.format);
   6614    nir_intrinsic_set_access(intrin, indices.access);
   6615 
   6616    nir_builder_instr_insert(build, &intrin->instr);
   6617    return &intrin->dest.ssa;
   6618 }
   6619 static inline nir_ssa_def *
   6620 _nir_build_image_deref_size(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_image_deref_size_indices indices)
   6621 {
   6622    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6623       build->shader, nir_intrinsic_image_deref_size);
   6624 
   6625    intrin->num_components = num_components;
   6626       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6627    intrin->src[0] = nir_src_for_ssa(src0);
   6628    intrin->src[1] = nir_src_for_ssa(src1);
   6629    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6630    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6631    nir_intrinsic_set_format(intrin, indices.format);
   6632    nir_intrinsic_set_access(intrin, indices.access);
   6633 
   6634    nir_builder_instr_insert(build, &intrin->instr);
   6635    return &intrin->dest.ssa;
   6636 }
   6637 static inline nir_ssa_def *
   6638 _nir_build_image_deref_sparse_load(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_deref_sparse_load_indices indices)
   6639 {
   6640    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6641       build->shader, nir_intrinsic_image_deref_sparse_load);
   6642 
   6643    intrin->num_components = num_components;
   6644       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6645    intrin->src[0] = nir_src_for_ssa(src0);
   6646    intrin->src[1] = nir_src_for_ssa(src1);
   6647    intrin->src[2] = nir_src_for_ssa(src2);
   6648    intrin->src[3] = nir_src_for_ssa(src3);
   6649    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6650    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6651    nir_intrinsic_set_format(intrin, indices.format);
   6652    nir_intrinsic_set_access(intrin, indices.access);
   6653    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   6654 
   6655    nir_builder_instr_insert(build, &intrin->instr);
   6656    return &intrin->dest.ssa;
   6657 }
   6658 static inline nir_intrinsic_instr *
   6659 _nir_build_image_deref_store(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_image_deref_store_indices indices)
   6660 {
   6661    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6662       build->shader, nir_intrinsic_image_deref_store);
   6663 
   6664    intrin->num_components = src3->num_components;
   6665    intrin->src[0] = nir_src_for_ssa(src0);
   6666    intrin->src[1] = nir_src_for_ssa(src1);
   6667    intrin->src[2] = nir_src_for_ssa(src2);
   6668    intrin->src[3] = nir_src_for_ssa(src3);
   6669    intrin->src[4] = nir_src_for_ssa(src4);
   6670    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6671    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6672    nir_intrinsic_set_format(intrin, indices.format);
   6673    nir_intrinsic_set_access(intrin, indices.access);
   6674    nir_intrinsic_set_src_type(intrin, indices.src_type);
   6675 
   6676    nir_builder_instr_insert(build, &intrin->instr);
   6677    return intrin;
   6678 }
   6679 static inline nir_intrinsic_instr *
   6680 _nir_build_image_deref_store_raw_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_image_deref_store_raw_intel_indices indices)
   6681 {
   6682    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6683       build->shader, nir_intrinsic_image_deref_store_raw_intel);
   6684 
   6685    intrin->num_components = src2->num_components;
   6686    intrin->src[0] = nir_src_for_ssa(src0);
   6687    intrin->src[1] = nir_src_for_ssa(src1);
   6688    intrin->src[2] = nir_src_for_ssa(src2);
   6689    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6690    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6691    nir_intrinsic_set_format(intrin, indices.format);
   6692    nir_intrinsic_set_access(intrin, indices.access);
   6693 
   6694    nir_builder_instr_insert(build, &intrin->instr);
   6695    return intrin;
   6696 }
   6697 static inline nir_ssa_def *
   6698 _nir_build_image_format(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_format_indices indices)
   6699 {
   6700    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6701       build->shader, nir_intrinsic_image_format);
   6702 
   6703       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6704    intrin->src[0] = nir_src_for_ssa(src0);
   6705    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6706    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6707    nir_intrinsic_set_format(intrin, indices.format);
   6708    nir_intrinsic_set_access(intrin, indices.access);
   6709 
   6710    nir_builder_instr_insert(build, &intrin->instr);
   6711    return &intrin->dest.ssa;
   6712 }
   6713 static inline nir_ssa_def *
   6714 _nir_build_image_load(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_load_indices indices)
   6715 {
   6716    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6717       build->shader, nir_intrinsic_image_load);
   6718 
   6719    intrin->num_components = num_components;
   6720       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6721    intrin->src[0] = nir_src_for_ssa(src0);
   6722    intrin->src[1] = nir_src_for_ssa(src1);
   6723    intrin->src[2] = nir_src_for_ssa(src2);
   6724    intrin->src[3] = nir_src_for_ssa(src3);
   6725    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6726    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6727    nir_intrinsic_set_format(intrin, indices.format);
   6728    nir_intrinsic_set_access(intrin, indices.access);
   6729    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   6730 
   6731    nir_builder_instr_insert(build, &intrin->instr);
   6732    return &intrin->dest.ssa;
   6733 }
   6734 static inline nir_ssa_def *
   6735 _nir_build_image_load_raw_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_image_load_raw_intel_indices indices)
   6736 {
   6737    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6738       build->shader, nir_intrinsic_image_load_raw_intel);
   6739 
   6740    intrin->num_components = num_components;
   6741       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6742    intrin->src[0] = nir_src_for_ssa(src0);
   6743    intrin->src[1] = nir_src_for_ssa(src1);
   6744    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6745    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6746    nir_intrinsic_set_format(intrin, indices.format);
   6747    nir_intrinsic_set_access(intrin, indices.access);
   6748 
   6749    nir_builder_instr_insert(build, &intrin->instr);
   6750    return &intrin->dest.ssa;
   6751 }
   6752 static inline nir_ssa_def *
   6753 _nir_build_image_order(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_order_indices indices)
   6754 {
   6755    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6756       build->shader, nir_intrinsic_image_order);
   6757 
   6758       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6759    intrin->src[0] = nir_src_for_ssa(src0);
   6760    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6761    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6762    nir_intrinsic_set_format(intrin, indices.format);
   6763    nir_intrinsic_set_access(intrin, indices.access);
   6764 
   6765    nir_builder_instr_insert(build, &intrin->instr);
   6766    return &intrin->dest.ssa;
   6767 }
   6768 static inline nir_ssa_def *
   6769 _nir_build_image_samples(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_image_samples_indices indices)
   6770 {
   6771    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6772       build->shader, nir_intrinsic_image_samples);
   6773 
   6774       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6775    intrin->src[0] = nir_src_for_ssa(src0);
   6776    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6777    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6778    nir_intrinsic_set_format(intrin, indices.format);
   6779    nir_intrinsic_set_access(intrin, indices.access);
   6780 
   6781    nir_builder_instr_insert(build, &intrin->instr);
   6782    return &intrin->dest.ssa;
   6783 }
   6784 static inline nir_ssa_def *
   6785 _nir_build_image_size(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_image_size_indices indices)
   6786 {
   6787    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6788       build->shader, nir_intrinsic_image_size);
   6789 
   6790    intrin->num_components = num_components;
   6791       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6792    intrin->src[0] = nir_src_for_ssa(src0);
   6793    intrin->src[1] = nir_src_for_ssa(src1);
   6794    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6795    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6796    nir_intrinsic_set_format(intrin, indices.format);
   6797    nir_intrinsic_set_access(intrin, indices.access);
   6798 
   6799    nir_builder_instr_insert(build, &intrin->instr);
   6800    return &intrin->dest.ssa;
   6801 }
   6802 static inline nir_ssa_def *
   6803 _nir_build_image_sparse_load(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_image_sparse_load_indices indices)
   6804 {
   6805    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6806       build->shader, nir_intrinsic_image_sparse_load);
   6807 
   6808    intrin->num_components = num_components;
   6809       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6810    intrin->src[0] = nir_src_for_ssa(src0);
   6811    intrin->src[1] = nir_src_for_ssa(src1);
   6812    intrin->src[2] = nir_src_for_ssa(src2);
   6813    intrin->src[3] = nir_src_for_ssa(src3);
   6814    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6815    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6816    nir_intrinsic_set_format(intrin, indices.format);
   6817    nir_intrinsic_set_access(intrin, indices.access);
   6818    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   6819 
   6820    nir_builder_instr_insert(build, &intrin->instr);
   6821    return &intrin->dest.ssa;
   6822 }
   6823 static inline nir_intrinsic_instr *
   6824 _nir_build_image_store(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_image_store_indices indices)
   6825 {
   6826    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6827       build->shader, nir_intrinsic_image_store);
   6828 
   6829    intrin->num_components = src3->num_components;
   6830    intrin->src[0] = nir_src_for_ssa(src0);
   6831    intrin->src[1] = nir_src_for_ssa(src1);
   6832    intrin->src[2] = nir_src_for_ssa(src2);
   6833    intrin->src[3] = nir_src_for_ssa(src3);
   6834    intrin->src[4] = nir_src_for_ssa(src4);
   6835    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6836    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6837    nir_intrinsic_set_format(intrin, indices.format);
   6838    nir_intrinsic_set_access(intrin, indices.access);
   6839    nir_intrinsic_set_src_type(intrin, indices.src_type);
   6840 
   6841    nir_builder_instr_insert(build, &intrin->instr);
   6842    return intrin;
   6843 }
   6844 static inline nir_intrinsic_instr *
   6845 _nir_build_image_store_raw_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_image_store_raw_intel_indices indices)
   6846 {
   6847    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6848       build->shader, nir_intrinsic_image_store_raw_intel);
   6849 
   6850    intrin->num_components = src2->num_components;
   6851    intrin->src[0] = nir_src_for_ssa(src0);
   6852    intrin->src[1] = nir_src_for_ssa(src1);
   6853    intrin->src[2] = nir_src_for_ssa(src2);
   6854    nir_intrinsic_set_image_dim(intrin, indices.image_dim);
   6855    nir_intrinsic_set_image_array(intrin, indices.image_array);
   6856    nir_intrinsic_set_format(intrin, indices.format);
   6857    nir_intrinsic_set_access(intrin, indices.access);
   6858 
   6859    nir_builder_instr_insert(build, &intrin->instr);
   6860    return intrin;
   6861 }
   6862 static inline nir_ssa_def *
   6863 _nir_build_inclusive_scan(nir_builder *build, nir_ssa_def *src0, struct _nir_inclusive_scan_indices indices)
   6864 {
   6865    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6866       build->shader, nir_intrinsic_inclusive_scan);
   6867 
   6868    intrin->num_components = src0->num_components;
   6869       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   6870    intrin->src[0] = nir_src_for_ssa(src0);
   6871    nir_intrinsic_set_reduction_op(intrin, indices.reduction_op);
   6872 
   6873    nir_builder_instr_insert(build, &intrin->instr);
   6874    return &intrin->dest.ssa;
   6875 }
   6876 static inline nir_ssa_def *
   6877 _nir_build_interp_deref_at_centroid(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0)
   6878 {
   6879    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6880       build->shader, nir_intrinsic_interp_deref_at_centroid);
   6881 
   6882    intrin->num_components = num_components;
   6883       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6884    intrin->src[0] = nir_src_for_ssa(src0);
   6885 
   6886    nir_builder_instr_insert(build, &intrin->instr);
   6887    return &intrin->dest.ssa;
   6888 }
   6889 static inline nir_ssa_def *
   6890 _nir_build_interp_deref_at_offset(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   6891 {
   6892    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6893       build->shader, nir_intrinsic_interp_deref_at_offset);
   6894 
   6895    intrin->num_components = num_components;
   6896       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6897    intrin->src[0] = nir_src_for_ssa(src0);
   6898    intrin->src[1] = nir_src_for_ssa(src1);
   6899 
   6900    nir_builder_instr_insert(build, &intrin->instr);
   6901    return &intrin->dest.ssa;
   6902 }
   6903 static inline nir_ssa_def *
   6904 _nir_build_interp_deref_at_sample(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   6905 {
   6906    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6907       build->shader, nir_intrinsic_interp_deref_at_sample);
   6908 
   6909    intrin->num_components = num_components;
   6910       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6911    intrin->src[0] = nir_src_for_ssa(src0);
   6912    intrin->src[1] = nir_src_for_ssa(src1);
   6913 
   6914    nir_builder_instr_insert(build, &intrin->instr);
   6915    return &intrin->dest.ssa;
   6916 }
   6917 static inline nir_ssa_def *
   6918 _nir_build_interp_deref_at_vertex(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   6919 {
   6920    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6921       build->shader, nir_intrinsic_interp_deref_at_vertex);
   6922 
   6923    intrin->num_components = num_components;
   6924       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   6925    intrin->src[0] = nir_src_for_ssa(src0);
   6926    intrin->src[1] = nir_src_for_ssa(src1);
   6927 
   6928    nir_builder_instr_insert(build, &intrin->instr);
   6929    return &intrin->dest.ssa;
   6930 }
   6931 static inline nir_ssa_def *
   6932 _nir_build_is_helper_invocation(nir_builder *build, unsigned bit_size)
   6933 {
   6934    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6935       build->shader, nir_intrinsic_is_helper_invocation);
   6936 
   6937       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6938 
   6939    nir_builder_instr_insert(build, &intrin->instr);
   6940    return &intrin->dest.ssa;
   6941 }
   6942 static inline nir_ssa_def *
   6943 _nir_build_is_sparse_texels_resident(nir_builder *build, nir_ssa_def *src0)
   6944 {
   6945    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6946       build->shader, nir_intrinsic_is_sparse_texels_resident);
   6947 
   6948       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   6949    intrin->src[0] = nir_src_for_ssa(src0);
   6950 
   6951    nir_builder_instr_insert(build, &intrin->instr);
   6952    return &intrin->dest.ssa;
   6953 }
   6954 static inline nir_ssa_def *
   6955 _nir_build_lane_permute_16_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   6956 {
   6957    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6958       build->shader, nir_intrinsic_lane_permute_16_amd);
   6959 
   6960       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   6961    intrin->src[0] = nir_src_for_ssa(src0);
   6962    intrin->src[1] = nir_src_for_ssa(src1);
   6963    intrin->src[2] = nir_src_for_ssa(src2);
   6964 
   6965    nir_builder_instr_insert(build, &intrin->instr);
   6966    return &intrin->dest.ssa;
   6967 }
   6968 static inline nir_ssa_def *
   6969 _nir_build_last_invocation(nir_builder *build)
   6970 {
   6971    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6972       build->shader, nir_intrinsic_last_invocation);
   6973 
   6974       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   6975 
   6976    nir_builder_instr_insert(build, &intrin->instr);
   6977    return &intrin->dest.ssa;
   6978 }
   6979 static inline nir_ssa_def *
   6980 _nir_build_load_aa_line_width(nir_builder *build)
   6981 {
   6982    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6983       build->shader, nir_intrinsic_load_aa_line_width);
   6984 
   6985       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   6986 
   6987    nir_builder_instr_insert(build, &intrin->instr);
   6988    return &intrin->dest.ssa;
   6989 }
   6990 static inline nir_ssa_def *
   6991 _nir_build_load_back_face_agx(nir_builder *build, unsigned bit_size)
   6992 {
   6993    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   6994       build->shader, nir_intrinsic_load_back_face_agx);
   6995 
   6996       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   6997 
   6998    nir_builder_instr_insert(build, &intrin->instr);
   6999    return &intrin->dest.ssa;
   7000 }
   7001 static inline nir_ssa_def *
   7002 _nir_build_load_barycentric_at_offset(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_barycentric_at_offset_indices indices)
   7003 {
   7004    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7005       build->shader, nir_intrinsic_load_barycentric_at_offset);
   7006 
   7007       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   7008    intrin->src[0] = nir_src_for_ssa(src0);
   7009    nir_intrinsic_set_interp_mode(intrin, indices.interp_mode);
   7010 
   7011    nir_builder_instr_insert(build, &intrin->instr);
   7012    return &intrin->dest.ssa;
   7013 }
   7014 static inline nir_ssa_def *
   7015 _nir_build_load_barycentric_at_sample(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_barycentric_at_sample_indices indices)
   7016 {
   7017    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7018       build->shader, nir_intrinsic_load_barycentric_at_sample);
   7019 
   7020       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   7021    intrin->src[0] = nir_src_for_ssa(src0);
   7022    nir_intrinsic_set_interp_mode(intrin, indices.interp_mode);
   7023 
   7024    nir_builder_instr_insert(build, &intrin->instr);
   7025    return &intrin->dest.ssa;
   7026 }
   7027 static inline nir_ssa_def *
   7028 _nir_build_load_barycentric_centroid(nir_builder *build, unsigned bit_size, struct _nir_load_barycentric_centroid_indices indices)
   7029 {
   7030    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7031       build->shader, nir_intrinsic_load_barycentric_centroid);
   7032 
   7033       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   7034    nir_intrinsic_set_interp_mode(intrin, indices.interp_mode);
   7035 
   7036    nir_builder_instr_insert(build, &intrin->instr);
   7037    return &intrin->dest.ssa;
   7038 }
   7039 static inline nir_ssa_def *
   7040 _nir_build_load_barycentric_model(nir_builder *build, unsigned bit_size, struct _nir_load_barycentric_model_indices indices)
   7041 {
   7042    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7043       build->shader, nir_intrinsic_load_barycentric_model);
   7044 
   7045       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7046    nir_intrinsic_set_interp_mode(intrin, indices.interp_mode);
   7047 
   7048    nir_builder_instr_insert(build, &intrin->instr);
   7049    return &intrin->dest.ssa;
   7050 }
   7051 static inline nir_ssa_def *
   7052 _nir_build_load_barycentric_pixel(nir_builder *build, unsigned bit_size, struct _nir_load_barycentric_pixel_indices indices)
   7053 {
   7054    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7055       build->shader, nir_intrinsic_load_barycentric_pixel);
   7056 
   7057       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   7058    nir_intrinsic_set_interp_mode(intrin, indices.interp_mode);
   7059 
   7060    nir_builder_instr_insert(build, &intrin->instr);
   7061    return &intrin->dest.ssa;
   7062 }
   7063 static inline nir_ssa_def *
   7064 _nir_build_load_barycentric_sample(nir_builder *build, unsigned bit_size, struct _nir_load_barycentric_sample_indices indices)
   7065 {
   7066    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7067       build->shader, nir_intrinsic_load_barycentric_sample);
   7068 
   7069       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   7070    nir_intrinsic_set_interp_mode(intrin, indices.interp_mode);
   7071 
   7072    nir_builder_instr_insert(build, &intrin->instr);
   7073    return &intrin->dest.ssa;
   7074 }
   7075 static inline nir_ssa_def *
   7076 _nir_build_load_base_global_invocation_id(nir_builder *build, unsigned bit_size)
   7077 {
   7078    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7079       build->shader, nir_intrinsic_load_base_global_invocation_id);
   7080 
   7081       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7082 
   7083    nir_builder_instr_insert(build, &intrin->instr);
   7084    return &intrin->dest.ssa;
   7085 }
   7086 static inline nir_ssa_def *
   7087 _nir_build_load_base_instance(nir_builder *build)
   7088 {
   7089    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7090       build->shader, nir_intrinsic_load_base_instance);
   7091 
   7092       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7093 
   7094    nir_builder_instr_insert(build, &intrin->instr);
   7095    return &intrin->dest.ssa;
   7096 }
   7097 static inline nir_ssa_def *
   7098 _nir_build_load_base_vertex(nir_builder *build)
   7099 {
   7100    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7101       build->shader, nir_intrinsic_load_base_vertex);
   7102 
   7103       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7104 
   7105    nir_builder_instr_insert(build, &intrin->instr);
   7106    return &intrin->dest.ssa;
   7107 }
   7108 static inline nir_ssa_def *
   7109 _nir_build_load_base_workgroup_id(nir_builder *build, unsigned bit_size)
   7110 {
   7111    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7112       build->shader, nir_intrinsic_load_base_workgroup_id);
   7113 
   7114       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7115 
   7116    nir_builder_instr_insert(build, &intrin->instr);
   7117    return &intrin->dest.ssa;
   7118 }
   7119 static inline nir_ssa_def *
   7120 _nir_build_load_blend_const_color_a_float(nir_builder *build)
   7121 {
   7122    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7123       build->shader, nir_intrinsic_load_blend_const_color_a_float);
   7124 
   7125       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7126 
   7127    nir_builder_instr_insert(build, &intrin->instr);
   7128    return &intrin->dest.ssa;
   7129 }
   7130 static inline nir_ssa_def *
   7131 _nir_build_load_blend_const_color_aaaa8888_unorm(nir_builder *build)
   7132 {
   7133    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7134       build->shader, nir_intrinsic_load_blend_const_color_aaaa8888_unorm);
   7135 
   7136       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7137 
   7138    nir_builder_instr_insert(build, &intrin->instr);
   7139    return &intrin->dest.ssa;
   7140 }
   7141 static inline nir_ssa_def *
   7142 _nir_build_load_blend_const_color_b_float(nir_builder *build)
   7143 {
   7144    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7145       build->shader, nir_intrinsic_load_blend_const_color_b_float);
   7146 
   7147       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7148 
   7149    nir_builder_instr_insert(build, &intrin->instr);
   7150    return &intrin->dest.ssa;
   7151 }
   7152 static inline nir_ssa_def *
   7153 _nir_build_load_blend_const_color_g_float(nir_builder *build)
   7154 {
   7155    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7156       build->shader, nir_intrinsic_load_blend_const_color_g_float);
   7157 
   7158       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7159 
   7160    nir_builder_instr_insert(build, &intrin->instr);
   7161    return &intrin->dest.ssa;
   7162 }
   7163 static inline nir_ssa_def *
   7164 _nir_build_load_blend_const_color_r_float(nir_builder *build)
   7165 {
   7166    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7167       build->shader, nir_intrinsic_load_blend_const_color_r_float);
   7168 
   7169       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7170 
   7171    nir_builder_instr_insert(build, &intrin->instr);
   7172    return &intrin->dest.ssa;
   7173 }
   7174 static inline nir_ssa_def *
   7175 _nir_build_load_blend_const_color_rgba(nir_builder *build)
   7176 {
   7177    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7178       build->shader, nir_intrinsic_load_blend_const_color_rgba);
   7179 
   7180       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   7181 
   7182    nir_builder_instr_insert(build, &intrin->instr);
   7183    return &intrin->dest.ssa;
   7184 }
   7185 static inline nir_ssa_def *
   7186 _nir_build_load_blend_const_color_rgba8888_unorm(nir_builder *build)
   7187 {
   7188    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7189       build->shader, nir_intrinsic_load_blend_const_color_rgba8888_unorm);
   7190 
   7191       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7192 
   7193    nir_builder_instr_insert(build, &intrin->instr);
   7194    return &intrin->dest.ssa;
   7195 }
   7196 static inline nir_ssa_def *
   7197 _nir_build_load_btd_dss_id_intel(nir_builder *build)
   7198 {
   7199    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7200       build->shader, nir_intrinsic_load_btd_dss_id_intel);
   7201 
   7202       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7203 
   7204    nir_builder_instr_insert(build, &intrin->instr);
   7205    return &intrin->dest.ssa;
   7206 }
   7207 static inline nir_ssa_def *
   7208 _nir_build_load_btd_global_arg_addr_intel(nir_builder *build)
   7209 {
   7210    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7211       build->shader, nir_intrinsic_load_btd_global_arg_addr_intel);
   7212 
   7213       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   7214 
   7215    nir_builder_instr_insert(build, &intrin->instr);
   7216    return &intrin->dest.ssa;
   7217 }
   7218 static inline nir_ssa_def *
   7219 _nir_build_load_btd_local_arg_addr_intel(nir_builder *build)
   7220 {
   7221    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7222       build->shader, nir_intrinsic_load_btd_local_arg_addr_intel);
   7223 
   7224       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   7225 
   7226    nir_builder_instr_insert(build, &intrin->instr);
   7227    return &intrin->dest.ssa;
   7228 }
   7229 static inline nir_ssa_def *
   7230 _nir_build_load_btd_resume_sbt_addr_intel(nir_builder *build)
   7231 {
   7232    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7233       build->shader, nir_intrinsic_load_btd_resume_sbt_addr_intel);
   7234 
   7235       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   7236 
   7237    nir_builder_instr_insert(build, &intrin->instr);
   7238    return &intrin->dest.ssa;
   7239 }
   7240 static inline nir_ssa_def *
   7241 _nir_build_load_btd_stack_id_intel(nir_builder *build)
   7242 {
   7243    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7244       build->shader, nir_intrinsic_load_btd_stack_id_intel);
   7245 
   7246       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7247 
   7248    nir_builder_instr_insert(build, &intrin->instr);
   7249    return &intrin->dest.ssa;
   7250 }
   7251 static inline nir_ssa_def *
   7252 _nir_build_load_buffer_amd(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_load_buffer_amd_indices indices)
   7253 {
   7254    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7255       build->shader, nir_intrinsic_load_buffer_amd);
   7256 
   7257    intrin->num_components = num_components;
   7258       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7259    intrin->src[0] = nir_src_for_ssa(src0);
   7260    intrin->src[1] = nir_src_for_ssa(src1);
   7261    intrin->src[2] = nir_src_for_ssa(src2);
   7262    nir_intrinsic_set_base(intrin, indices.base);
   7263    nir_intrinsic_set_is_swizzled(intrin, indices.is_swizzled);
   7264    nir_intrinsic_set_slc_amd(intrin, indices.slc_amd);
   7265    nir_intrinsic_set_memory_modes(intrin, indices.memory_modes);
   7266 
   7267    nir_builder_instr_insert(build, &intrin->instr);
   7268    return &intrin->dest.ssa;
   7269 }
   7270 static inline nir_ssa_def *
   7271 _nir_build_load_callable_sbt_addr_intel(nir_builder *build)
   7272 {
   7273    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7274       build->shader, nir_intrinsic_load_callable_sbt_addr_intel);
   7275 
   7276       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   7277 
   7278    nir_builder_instr_insert(build, &intrin->instr);
   7279    return &intrin->dest.ssa;
   7280 }
   7281 static inline nir_ssa_def *
   7282 _nir_build_load_callable_sbt_stride_intel(nir_builder *build)
   7283 {
   7284    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7285       build->shader, nir_intrinsic_load_callable_sbt_stride_intel);
   7286 
   7287       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 16, NULL);
   7288 
   7289    nir_builder_instr_insert(build, &intrin->instr);
   7290    return &intrin->dest.ssa;
   7291 }
   7292 static inline nir_ssa_def *
   7293 _nir_build_load_color0(nir_builder *build)
   7294 {
   7295    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7296       build->shader, nir_intrinsic_load_color0);
   7297 
   7298       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   7299 
   7300    nir_builder_instr_insert(build, &intrin->instr);
   7301    return &intrin->dest.ssa;
   7302 }
   7303 static inline nir_ssa_def *
   7304 _nir_build_load_color1(nir_builder *build)
   7305 {
   7306    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7307       build->shader, nir_intrinsic_load_color1);
   7308 
   7309       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   7310 
   7311    nir_builder_instr_insert(build, &intrin->instr);
   7312    return &intrin->dest.ssa;
   7313 }
   7314 static inline nir_ssa_def *
   7315 _nir_build_load_constant(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_constant_indices indices)
   7316 {
   7317    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7318       build->shader, nir_intrinsic_load_constant);
   7319 
   7320    intrin->num_components = num_components;
   7321       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7322    intrin->src[0] = nir_src_for_ssa(src0);
   7323    nir_intrinsic_set_base(intrin, indices.base);
   7324    nir_intrinsic_set_range(intrin, indices.range);
   7325    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7326    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7327 
   7328    nir_builder_instr_insert(build, &intrin->instr);
   7329    return &intrin->dest.ssa;
   7330 }
   7331 static inline nir_ssa_def *
   7332 _nir_build_load_constant_base_ptr(nir_builder *build, unsigned num_components, unsigned bit_size)
   7333 {
   7334    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7335       build->shader, nir_intrinsic_load_constant_base_ptr);
   7336 
   7337    intrin->num_components = num_components;
   7338       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7339 
   7340    nir_builder_instr_insert(build, &intrin->instr);
   7341    return &intrin->dest.ssa;
   7342 }
   7343 static inline nir_ssa_def *
   7344 _nir_build_load_cull_any_enabled_amd(nir_builder *build)
   7345 {
   7346    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7347       build->shader, nir_intrinsic_load_cull_any_enabled_amd);
   7348 
   7349       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7350 
   7351    nir_builder_instr_insert(build, &intrin->instr);
   7352    return &intrin->dest.ssa;
   7353 }
   7354 static inline nir_ssa_def *
   7355 _nir_build_load_cull_back_face_enabled_amd(nir_builder *build)
   7356 {
   7357    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7358       build->shader, nir_intrinsic_load_cull_back_face_enabled_amd);
   7359 
   7360       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7361 
   7362    nir_builder_instr_insert(build, &intrin->instr);
   7363    return &intrin->dest.ssa;
   7364 }
   7365 static inline nir_ssa_def *
   7366 _nir_build_load_cull_ccw_amd(nir_builder *build)
   7367 {
   7368    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7369       build->shader, nir_intrinsic_load_cull_ccw_amd);
   7370 
   7371       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7372 
   7373    nir_builder_instr_insert(build, &intrin->instr);
   7374    return &intrin->dest.ssa;
   7375 }
   7376 static inline nir_ssa_def *
   7377 _nir_build_load_cull_front_face_enabled_amd(nir_builder *build)
   7378 {
   7379    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7380       build->shader, nir_intrinsic_load_cull_front_face_enabled_amd);
   7381 
   7382       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7383 
   7384    nir_builder_instr_insert(build, &intrin->instr);
   7385    return &intrin->dest.ssa;
   7386 }
   7387 static inline nir_ssa_def *
   7388 _nir_build_load_cull_small_prim_precision_amd(nir_builder *build)
   7389 {
   7390    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7391       build->shader, nir_intrinsic_load_cull_small_prim_precision_amd);
   7392 
   7393       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7394 
   7395    nir_builder_instr_insert(build, &intrin->instr);
   7396    return &intrin->dest.ssa;
   7397 }
   7398 static inline nir_ssa_def *
   7399 _nir_build_load_cull_small_primitives_enabled_amd(nir_builder *build)
   7400 {
   7401    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7402       build->shader, nir_intrinsic_load_cull_small_primitives_enabled_amd);
   7403 
   7404       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7405 
   7406    nir_builder_instr_insert(build, &intrin->instr);
   7407    return &intrin->dest.ssa;
   7408 }
   7409 static inline nir_ssa_def *
   7410 _nir_build_load_deref(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_deref_indices indices)
   7411 {
   7412    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7413       build->shader, nir_intrinsic_load_deref);
   7414 
   7415    intrin->num_components = num_components;
   7416       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7417    intrin->src[0] = nir_src_for_ssa(src0);
   7418    nir_intrinsic_set_access(intrin, indices.access);
   7419 
   7420    nir_builder_instr_insert(build, &intrin->instr);
   7421    return &intrin->dest.ssa;
   7422 }
   7423 static inline nir_ssa_def *
   7424 _nir_build_load_deref_block_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_deref_block_intel_indices indices)
   7425 {
   7426    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7427       build->shader, nir_intrinsic_load_deref_block_intel);
   7428 
   7429    intrin->num_components = num_components;
   7430       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7431    intrin->src[0] = nir_src_for_ssa(src0);
   7432    nir_intrinsic_set_access(intrin, indices.access);
   7433 
   7434    nir_builder_instr_insert(build, &intrin->instr);
   7435    return &intrin->dest.ssa;
   7436 }
   7437 static inline nir_ssa_def *
   7438 _nir_build_load_desc_set_address_intel(nir_builder *build, nir_ssa_def *src0)
   7439 {
   7440    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7441       build->shader, nir_intrinsic_load_desc_set_address_intel);
   7442 
   7443       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   7444    intrin->src[0] = nir_src_for_ssa(src0);
   7445 
   7446    nir_builder_instr_insert(build, &intrin->instr);
   7447    return &intrin->dest.ssa;
   7448 }
   7449 static inline nir_ssa_def *
   7450 _nir_build_load_draw_id(nir_builder *build)
   7451 {
   7452    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7453       build->shader, nir_intrinsic_load_draw_id);
   7454 
   7455       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7456 
   7457    nir_builder_instr_insert(build, &intrin->instr);
   7458    return &intrin->dest.ssa;
   7459 }
   7460 static inline nir_ssa_def *
   7461 _nir_build_load_fb_layers_v3d(nir_builder *build, unsigned bit_size)
   7462 {
   7463    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7464       build->shader, nir_intrinsic_load_fb_layers_v3d);
   7465 
   7466       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   7467 
   7468    nir_builder_instr_insert(build, &intrin->instr);
   7469    return &intrin->dest.ssa;
   7470 }
   7471 static inline nir_ssa_def *
   7472 _nir_build_load_first_vertex(nir_builder *build)
   7473 {
   7474    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7475       build->shader, nir_intrinsic_load_first_vertex);
   7476 
   7477       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7478 
   7479    nir_builder_instr_insert(build, &intrin->instr);
   7480    return &intrin->dest.ssa;
   7481 }
   7482 static inline nir_ssa_def *
   7483 _nir_build_load_frag_coord(nir_builder *build)
   7484 {
   7485    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7486       build->shader, nir_intrinsic_load_frag_coord);
   7487 
   7488       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   7489 
   7490    nir_builder_instr_insert(build, &intrin->instr);
   7491    return &intrin->dest.ssa;
   7492 }
   7493 static inline nir_ssa_def *
   7494 _nir_build_load_frag_shading_rate(nir_builder *build)
   7495 {
   7496    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7497       build->shader, nir_intrinsic_load_frag_shading_rate);
   7498 
   7499       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7500 
   7501    nir_builder_instr_insert(build, &intrin->instr);
   7502    return &intrin->dest.ssa;
   7503 }
   7504 static inline nir_ssa_def *
   7505 _nir_build_load_front_face(nir_builder *build, unsigned bit_size)
   7506 {
   7507    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7508       build->shader, nir_intrinsic_load_front_face);
   7509 
   7510       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   7511 
   7512    nir_builder_instr_insert(build, &intrin->instr);
   7513    return &intrin->dest.ssa;
   7514 }
   7515 static inline nir_ssa_def *
   7516 _nir_build_load_fs_input_interp_deltas(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_fs_input_interp_deltas_indices indices)
   7517 {
   7518    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7519       build->shader, nir_intrinsic_load_fs_input_interp_deltas);
   7520 
   7521       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7522    intrin->src[0] = nir_src_for_ssa(src0);
   7523    nir_intrinsic_set_base(intrin, indices.base);
   7524    nir_intrinsic_set_component(intrin, indices.component);
   7525    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   7526 
   7527    nir_builder_instr_insert(build, &intrin->instr);
   7528    return &intrin->dest.ssa;
   7529 }
   7530 static inline nir_ssa_def *
   7531 _nir_build_load_global(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_global_indices indices)
   7532 {
   7533    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7534       build->shader, nir_intrinsic_load_global);
   7535 
   7536    intrin->num_components = num_components;
   7537       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7538    intrin->src[0] = nir_src_for_ssa(src0);
   7539    nir_intrinsic_set_access(intrin, indices.access);
   7540    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7541    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7542 
   7543    nir_builder_instr_insert(build, &intrin->instr);
   7544    return &intrin->dest.ssa;
   7545 }
   7546 static inline nir_ssa_def *
   7547 _nir_build_load_global_block_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_global_block_intel_indices indices)
   7548 {
   7549    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7550       build->shader, nir_intrinsic_load_global_block_intel);
   7551 
   7552    intrin->num_components = num_components;
   7553       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7554    intrin->src[0] = nir_src_for_ssa(src0);
   7555    nir_intrinsic_set_access(intrin, indices.access);
   7556    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7557    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7558 
   7559    nir_builder_instr_insert(build, &intrin->instr);
   7560    return &intrin->dest.ssa;
   7561 }
   7562 static inline nir_ssa_def *
   7563 _nir_build_load_global_const_block_intel(nir_builder *build, unsigned num_components, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_global_const_block_intel_indices indices)
   7564 {
   7565    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7566       build->shader, nir_intrinsic_load_global_const_block_intel);
   7567 
   7568    intrin->num_components = num_components;
   7569       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, 32, NULL);
   7570    intrin->src[0] = nir_src_for_ssa(src0);
   7571    intrin->src[1] = nir_src_for_ssa(src1);
   7572    nir_intrinsic_set_base(intrin, indices.base);
   7573 
   7574    nir_builder_instr_insert(build, &intrin->instr);
   7575    return &intrin->dest.ssa;
   7576 }
   7577 static inline nir_ssa_def *
   7578 _nir_build_load_global_constant(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_global_constant_indices indices)
   7579 {
   7580    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7581       build->shader, nir_intrinsic_load_global_constant);
   7582 
   7583    intrin->num_components = num_components;
   7584       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7585    intrin->src[0] = nir_src_for_ssa(src0);
   7586    nir_intrinsic_set_access(intrin, indices.access);
   7587    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7588    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7589 
   7590    nir_builder_instr_insert(build, &intrin->instr);
   7591    return &intrin->dest.ssa;
   7592 }
   7593 static inline nir_ssa_def *
   7594 _nir_build_load_global_constant_bounded(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_load_global_constant_bounded_indices indices)
   7595 {
   7596    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7597       build->shader, nir_intrinsic_load_global_constant_bounded);
   7598 
   7599    intrin->num_components = num_components;
   7600       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7601    intrin->src[0] = nir_src_for_ssa(src0);
   7602    intrin->src[1] = nir_src_for_ssa(src1);
   7603    intrin->src[2] = nir_src_for_ssa(src2);
   7604    nir_intrinsic_set_access(intrin, indices.access);
   7605    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7606    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7607 
   7608    nir_builder_instr_insert(build, &intrin->instr);
   7609    return &intrin->dest.ssa;
   7610 }
   7611 static inline nir_ssa_def *
   7612 _nir_build_load_global_constant_offset(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_global_constant_offset_indices indices)
   7613 {
   7614    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7615       build->shader, nir_intrinsic_load_global_constant_offset);
   7616 
   7617    intrin->num_components = num_components;
   7618       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7619    intrin->src[0] = nir_src_for_ssa(src0);
   7620    intrin->src[1] = nir_src_for_ssa(src1);
   7621    nir_intrinsic_set_access(intrin, indices.access);
   7622    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7623    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7624 
   7625    nir_builder_instr_insert(build, &intrin->instr);
   7626    return &intrin->dest.ssa;
   7627 }
   7628 static inline nir_ssa_def *
   7629 _nir_build_load_global_invocation_id(nir_builder *build, unsigned bit_size)
   7630 {
   7631    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7632       build->shader, nir_intrinsic_load_global_invocation_id);
   7633 
   7634       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7635 
   7636    nir_builder_instr_insert(build, &intrin->instr);
   7637    return &intrin->dest.ssa;
   7638 }
   7639 static inline nir_ssa_def *
   7640 _nir_build_load_global_invocation_id_zero_base(nir_builder *build, unsigned bit_size)
   7641 {
   7642    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7643       build->shader, nir_intrinsic_load_global_invocation_id_zero_base);
   7644 
   7645       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7646 
   7647    nir_builder_instr_insert(build, &intrin->instr);
   7648    return &intrin->dest.ssa;
   7649 }
   7650 static inline nir_ssa_def *
   7651 _nir_build_load_global_invocation_index(nir_builder *build, unsigned bit_size)
   7652 {
   7653    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7654       build->shader, nir_intrinsic_load_global_invocation_index);
   7655 
   7656       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   7657 
   7658    nir_builder_instr_insert(build, &intrin->instr);
   7659    return &intrin->dest.ssa;
   7660 }
   7661 static inline nir_ssa_def *
   7662 _nir_build_load_global_ir3(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_global_ir3_indices indices)
   7663 {
   7664    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7665       build->shader, nir_intrinsic_load_global_ir3);
   7666 
   7667    intrin->num_components = num_components;
   7668       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7669    intrin->src[0] = nir_src_for_ssa(src0);
   7670    intrin->src[1] = nir_src_for_ssa(src1);
   7671    nir_intrinsic_set_access(intrin, indices.access);
   7672    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7673    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7674 
   7675    nir_builder_instr_insert(build, &intrin->instr);
   7676    return &intrin->dest.ssa;
   7677 }
   7678 static inline nir_ssa_def *
   7679 _nir_build_load_gs_header_ir3(nir_builder *build)
   7680 {
   7681    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7682       build->shader, nir_intrinsic_load_gs_header_ir3);
   7683 
   7684       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7685 
   7686    nir_builder_instr_insert(build, &intrin->instr);
   7687    return &intrin->dest.ssa;
   7688 }
   7689 static inline nir_ssa_def *
   7690 _nir_build_load_gs_vertex_offset_amd(nir_builder *build, struct _nir_load_gs_vertex_offset_amd_indices indices)
   7691 {
   7692    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7693       build->shader, nir_intrinsic_load_gs_vertex_offset_amd);
   7694 
   7695       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7696    nir_intrinsic_set_base(intrin, indices.base);
   7697 
   7698    nir_builder_instr_insert(build, &intrin->instr);
   7699    return &intrin->dest.ssa;
   7700 }
   7701 static inline nir_ssa_def *
   7702 _nir_build_load_helper_invocation(nir_builder *build, unsigned bit_size)
   7703 {
   7704    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7705       build->shader, nir_intrinsic_load_helper_invocation);
   7706 
   7707       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   7708 
   7709    nir_builder_instr_insert(build, &intrin->instr);
   7710    return &intrin->dest.ssa;
   7711 }
   7712 static inline nir_ssa_def *
   7713 _nir_build_load_hs_patch_stride_ir3(nir_builder *build)
   7714 {
   7715    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7716       build->shader, nir_intrinsic_load_hs_patch_stride_ir3);
   7717 
   7718       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7719 
   7720    nir_builder_instr_insert(build, &intrin->instr);
   7721    return &intrin->dest.ssa;
   7722 }
   7723 static inline nir_ssa_def *
   7724 _nir_build_load_initial_edgeflags_amd(nir_builder *build)
   7725 {
   7726    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7727       build->shader, nir_intrinsic_load_initial_edgeflags_amd);
   7728 
   7729       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7730 
   7731    nir_builder_instr_insert(build, &intrin->instr);
   7732    return &intrin->dest.ssa;
   7733 }
   7734 static inline nir_ssa_def *
   7735 _nir_build_load_input(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_input_indices indices)
   7736 {
   7737    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7738       build->shader, nir_intrinsic_load_input);
   7739 
   7740    intrin->num_components = num_components;
   7741       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7742    intrin->src[0] = nir_src_for_ssa(src0);
   7743    nir_intrinsic_set_base(intrin, indices.base);
   7744    nir_intrinsic_set_component(intrin, indices.component);
   7745    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   7746    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   7747 
   7748    nir_builder_instr_insert(build, &intrin->instr);
   7749    return &intrin->dest.ssa;
   7750 }
   7751 static inline nir_ssa_def *
   7752 _nir_build_load_input_vertex(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_input_vertex_indices indices)
   7753 {
   7754    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7755       build->shader, nir_intrinsic_load_input_vertex);
   7756 
   7757    intrin->num_components = num_components;
   7758       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7759    intrin->src[0] = nir_src_for_ssa(src0);
   7760    intrin->src[1] = nir_src_for_ssa(src1);
   7761    nir_intrinsic_set_base(intrin, indices.base);
   7762    nir_intrinsic_set_component(intrin, indices.component);
   7763    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   7764    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   7765 
   7766    nir_builder_instr_insert(build, &intrin->instr);
   7767    return &intrin->dest.ssa;
   7768 }
   7769 static inline nir_ssa_def *
   7770 _nir_build_load_instance_id(nir_builder *build)
   7771 {
   7772    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7773       build->shader, nir_intrinsic_load_instance_id);
   7774 
   7775       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7776 
   7777    nir_builder_instr_insert(build, &intrin->instr);
   7778    return &intrin->dest.ssa;
   7779 }
   7780 static inline nir_ssa_def *
   7781 _nir_build_load_interpolated_input(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_interpolated_input_indices indices)
   7782 {
   7783    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7784       build->shader, nir_intrinsic_load_interpolated_input);
   7785 
   7786    intrin->num_components = num_components;
   7787       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7788    intrin->src[0] = nir_src_for_ssa(src0);
   7789    intrin->src[1] = nir_src_for_ssa(src1);
   7790    nir_intrinsic_set_base(intrin, indices.base);
   7791    nir_intrinsic_set_component(intrin, indices.component);
   7792    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   7793    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   7794 
   7795    nir_builder_instr_insert(build, &intrin->instr);
   7796    return &intrin->dest.ssa;
   7797 }
   7798 static inline nir_ssa_def *
   7799 _nir_build_load_intersection_opaque_amd(nir_builder *build)
   7800 {
   7801    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7802       build->shader, nir_intrinsic_load_intersection_opaque_amd);
   7803 
   7804       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7805 
   7806    nir_builder_instr_insert(build, &intrin->instr);
   7807    return &intrin->dest.ssa;
   7808 }
   7809 static inline nir_ssa_def *
   7810 _nir_build_load_invocation_id(nir_builder *build)
   7811 {
   7812    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7813       build->shader, nir_intrinsic_load_invocation_id);
   7814 
   7815       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7816 
   7817    nir_builder_instr_insert(build, &intrin->instr);
   7818    return &intrin->dest.ssa;
   7819 }
   7820 static inline nir_ssa_def *
   7821 _nir_build_load_is_indexed_draw(nir_builder *build)
   7822 {
   7823    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7824       build->shader, nir_intrinsic_load_is_indexed_draw);
   7825 
   7826       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7827 
   7828    nir_builder_instr_insert(build, &intrin->instr);
   7829    return &intrin->dest.ssa;
   7830 }
   7831 static inline nir_ssa_def *
   7832 _nir_build_load_kernel_input(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_kernel_input_indices indices)
   7833 {
   7834    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7835       build->shader, nir_intrinsic_load_kernel_input);
   7836 
   7837    intrin->num_components = num_components;
   7838       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7839    intrin->src[0] = nir_src_for_ssa(src0);
   7840    nir_intrinsic_set_base(intrin, indices.base);
   7841    nir_intrinsic_set_range(intrin, indices.range);
   7842    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   7843    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   7844 
   7845    nir_builder_instr_insert(build, &intrin->instr);
   7846    return &intrin->dest.ssa;
   7847 }
   7848 static inline nir_ssa_def *
   7849 _nir_build_load_layer_id(nir_builder *build)
   7850 {
   7851    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7852       build->shader, nir_intrinsic_load_layer_id);
   7853 
   7854       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7855 
   7856    nir_builder_instr_insert(build, &intrin->instr);
   7857    return &intrin->dest.ssa;
   7858 }
   7859 static inline nir_ssa_def *
   7860 _nir_build_load_leaf_opaque_intel(nir_builder *build)
   7861 {
   7862    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7863       build->shader, nir_intrinsic_load_leaf_opaque_intel);
   7864 
   7865       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7866 
   7867    nir_builder_instr_insert(build, &intrin->instr);
   7868    return &intrin->dest.ssa;
   7869 }
   7870 static inline nir_ssa_def *
   7871 _nir_build_load_leaf_procedural_intel(nir_builder *build)
   7872 {
   7873    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7874       build->shader, nir_intrinsic_load_leaf_procedural_intel);
   7875 
   7876       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   7877 
   7878    nir_builder_instr_insert(build, &intrin->instr);
   7879    return &intrin->dest.ssa;
   7880 }
   7881 static inline nir_ssa_def *
   7882 _nir_build_load_line_coord(nir_builder *build)
   7883 {
   7884    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7885       build->shader, nir_intrinsic_load_line_coord);
   7886 
   7887       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7888 
   7889    nir_builder_instr_insert(build, &intrin->instr);
   7890    return &intrin->dest.ssa;
   7891 }
   7892 static inline nir_ssa_def *
   7893 _nir_build_load_line_width(nir_builder *build)
   7894 {
   7895    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7896       build->shader, nir_intrinsic_load_line_width);
   7897 
   7898       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7899 
   7900    nir_builder_instr_insert(build, &intrin->instr);
   7901    return &intrin->dest.ssa;
   7902 }
   7903 static inline nir_ssa_def *
   7904 _nir_build_load_local_invocation_id(nir_builder *build)
   7905 {
   7906    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7907       build->shader, nir_intrinsic_load_local_invocation_id);
   7908 
   7909       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   7910 
   7911    nir_builder_instr_insert(build, &intrin->instr);
   7912    return &intrin->dest.ssa;
   7913 }
   7914 static inline nir_ssa_def *
   7915 _nir_build_load_local_invocation_index(nir_builder *build)
   7916 {
   7917    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7918       build->shader, nir_intrinsic_load_local_invocation_index);
   7919 
   7920       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7921 
   7922    nir_builder_instr_insert(build, &intrin->instr);
   7923    return &intrin->dest.ssa;
   7924 }
   7925 static inline nir_ssa_def *
   7926 _nir_build_load_local_shared_r600(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   7927 {
   7928    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7929       build->shader, nir_intrinsic_load_local_shared_r600);
   7930 
   7931    intrin->num_components = src0->num_components;
   7932       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7933    intrin->src[0] = nir_src_for_ssa(src0);
   7934 
   7935    nir_builder_instr_insert(build, &intrin->instr);
   7936    return &intrin->dest.ssa;
   7937 }
   7938 static inline nir_ssa_def *
   7939 _nir_build_load_num_subgroups(nir_builder *build)
   7940 {
   7941    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7942       build->shader, nir_intrinsic_load_num_subgroups);
   7943 
   7944       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7945 
   7946    nir_builder_instr_insert(build, &intrin->instr);
   7947    return &intrin->dest.ssa;
   7948 }
   7949 static inline nir_ssa_def *
   7950 _nir_build_load_num_workgroups(nir_builder *build, unsigned bit_size)
   7951 {
   7952    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7953       build->shader, nir_intrinsic_load_num_workgroups);
   7954 
   7955       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   7956 
   7957    nir_builder_instr_insert(build, &intrin->instr);
   7958    return &intrin->dest.ssa;
   7959 }
   7960 static inline nir_ssa_def *
   7961 _nir_build_load_output(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_output_indices indices)
   7962 {
   7963    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7964       build->shader, nir_intrinsic_load_output);
   7965 
   7966    intrin->num_components = num_components;
   7967       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7968    intrin->src[0] = nir_src_for_ssa(src0);
   7969    nir_intrinsic_set_base(intrin, indices.base);
   7970    nir_intrinsic_set_component(intrin, indices.component);
   7971    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   7972    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   7973 
   7974    nir_builder_instr_insert(build, &intrin->instr);
   7975    return &intrin->dest.ssa;
   7976 }
   7977 static inline nir_ssa_def *
   7978 _nir_build_load_packed_passthrough_primitive_amd(nir_builder *build)
   7979 {
   7980    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7981       build->shader, nir_intrinsic_load_packed_passthrough_primitive_amd);
   7982 
   7983       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   7984 
   7985    nir_builder_instr_insert(build, &intrin->instr);
   7986    return &intrin->dest.ssa;
   7987 }
   7988 static inline nir_ssa_def *
   7989 _nir_build_load_param(nir_builder *build, unsigned num_components, unsigned bit_size, struct _nir_load_param_indices indices)
   7990 {
   7991    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   7992       build->shader, nir_intrinsic_load_param);
   7993 
   7994    intrin->num_components = num_components;
   7995       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   7996    nir_intrinsic_set_param_idx(intrin, indices.param_idx);
   7997 
   7998    nir_builder_instr_insert(build, &intrin->instr);
   7999    return &intrin->dest.ssa;
   8000 }
   8001 static inline nir_ssa_def *
   8002 _nir_build_load_patch_vertices_in(nir_builder *build)
   8003 {
   8004    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8005       build->shader, nir_intrinsic_load_patch_vertices_in);
   8006 
   8007       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8008 
   8009    nir_builder_instr_insert(build, &intrin->instr);
   8010    return &intrin->dest.ssa;
   8011 }
   8012 static inline nir_ssa_def *
   8013 _nir_build_load_per_primitive_output(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_per_primitive_output_indices indices)
   8014 {
   8015    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8016       build->shader, nir_intrinsic_load_per_primitive_output);
   8017 
   8018    intrin->num_components = num_components;
   8019       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8020    intrin->src[0] = nir_src_for_ssa(src0);
   8021    intrin->src[1] = nir_src_for_ssa(src1);
   8022    nir_intrinsic_set_base(intrin, indices.base);
   8023    nir_intrinsic_set_component(intrin, indices.component);
   8024    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   8025    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   8026 
   8027    nir_builder_instr_insert(build, &intrin->instr);
   8028    return &intrin->dest.ssa;
   8029 }
   8030 static inline nir_ssa_def *
   8031 _nir_build_load_per_vertex_input(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_per_vertex_input_indices indices)
   8032 {
   8033    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8034       build->shader, nir_intrinsic_load_per_vertex_input);
   8035 
   8036    intrin->num_components = num_components;
   8037       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8038    intrin->src[0] = nir_src_for_ssa(src0);
   8039    intrin->src[1] = nir_src_for_ssa(src1);
   8040    nir_intrinsic_set_base(intrin, indices.base);
   8041    nir_intrinsic_set_component(intrin, indices.component);
   8042    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   8043    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   8044 
   8045    nir_builder_instr_insert(build, &intrin->instr);
   8046    return &intrin->dest.ssa;
   8047 }
   8048 static inline nir_ssa_def *
   8049 _nir_build_load_per_vertex_output(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_per_vertex_output_indices indices)
   8050 {
   8051    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8052       build->shader, nir_intrinsic_load_per_vertex_output);
   8053 
   8054    intrin->num_components = num_components;
   8055       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8056    intrin->src[0] = nir_src_for_ssa(src0);
   8057    intrin->src[1] = nir_src_for_ssa(src1);
   8058    nir_intrinsic_set_base(intrin, indices.base);
   8059    nir_intrinsic_set_component(intrin, indices.component);
   8060    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   8061    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   8062 
   8063    nir_builder_instr_insert(build, &intrin->instr);
   8064    return &intrin->dest.ssa;
   8065 }
   8066 static inline nir_ssa_def *
   8067 _nir_build_load_point_coord(nir_builder *build)
   8068 {
   8069    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8070       build->shader, nir_intrinsic_load_point_coord);
   8071 
   8072       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   8073 
   8074    nir_builder_instr_insert(build, &intrin->instr);
   8075    return &intrin->dest.ssa;
   8076 }
   8077 static inline nir_ssa_def *
   8078 _nir_build_load_primitive_id(nir_builder *build)
   8079 {
   8080    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8081       build->shader, nir_intrinsic_load_primitive_id);
   8082 
   8083       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8084 
   8085    nir_builder_instr_insert(build, &intrin->instr);
   8086    return &intrin->dest.ssa;
   8087 }
   8088 static inline nir_ssa_def *
   8089 _nir_build_load_primitive_location_ir3(nir_builder *build, struct _nir_load_primitive_location_ir3_indices indices)
   8090 {
   8091    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8092       build->shader, nir_intrinsic_load_primitive_location_ir3);
   8093 
   8094       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8095    nir_intrinsic_set_driver_location(intrin, indices.driver_location);
   8096 
   8097    nir_builder_instr_insert(build, &intrin->instr);
   8098    return &intrin->dest.ssa;
   8099 }
   8100 static inline nir_ssa_def *
   8101 _nir_build_load_printf_buffer_address(nir_builder *build, unsigned bit_size)
   8102 {
   8103    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8104       build->shader, nir_intrinsic_load_printf_buffer_address);
   8105 
   8106       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   8107 
   8108    nir_builder_instr_insert(build, &intrin->instr);
   8109    return &intrin->dest.ssa;
   8110 }
   8111 static inline nir_ssa_def *
   8112 _nir_build_load_ptr_dxil(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   8113 {
   8114    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8115       build->shader, nir_intrinsic_load_ptr_dxil);
   8116 
   8117    intrin->num_components = num_components;
   8118       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8119    intrin->src[0] = nir_src_for_ssa(src0);
   8120    intrin->src[1] = nir_src_for_ssa(src1);
   8121 
   8122    nir_builder_instr_insert(build, &intrin->instr);
   8123    return &intrin->dest.ssa;
   8124 }
   8125 static inline nir_ssa_def *
   8126 _nir_build_load_push_constant(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_push_constant_indices indices)
   8127 {
   8128    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8129       build->shader, nir_intrinsic_load_push_constant);
   8130 
   8131    intrin->num_components = num_components;
   8132       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8133    intrin->src[0] = nir_src_for_ssa(src0);
   8134    nir_intrinsic_set_base(intrin, indices.base);
   8135    nir_intrinsic_set_range(intrin, indices.range);
   8136 
   8137    nir_builder_instr_insert(build, &intrin->instr);
   8138    return &intrin->dest.ssa;
   8139 }
   8140 static inline nir_ssa_def *
   8141 _nir_build_load_raw_output_pan(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_raw_output_pan_indices indices)
   8142 {
   8143    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8144       build->shader, nir_intrinsic_load_raw_output_pan);
   8145 
   8146    intrin->num_components = num_components;
   8147       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8148    intrin->src[0] = nir_src_for_ssa(src0);
   8149    nir_intrinsic_set_base(intrin, indices.base);
   8150 
   8151    nir_builder_instr_insert(build, &intrin->instr);
   8152    return &intrin->dest.ssa;
   8153 }
   8154 static inline nir_ssa_def *
   8155 _nir_build_load_ray_base_mem_addr_intel(nir_builder *build)
   8156 {
   8157    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8158       build->shader, nir_intrinsic_load_ray_base_mem_addr_intel);
   8159 
   8160       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   8161 
   8162    nir_builder_instr_insert(build, &intrin->instr);
   8163    return &intrin->dest.ssa;
   8164 }
   8165 static inline nir_ssa_def *
   8166 _nir_build_load_ray_flags(nir_builder *build)
   8167 {
   8168    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8169       build->shader, nir_intrinsic_load_ray_flags);
   8170 
   8171       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8172 
   8173    nir_builder_instr_insert(build, &intrin->instr);
   8174    return &intrin->dest.ssa;
   8175 }
   8176 static inline nir_ssa_def *
   8177 _nir_build_load_ray_geometry_index(nir_builder *build)
   8178 {
   8179    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8180       build->shader, nir_intrinsic_load_ray_geometry_index);
   8181 
   8182       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8183 
   8184    nir_builder_instr_insert(build, &intrin->instr);
   8185    return &intrin->dest.ssa;
   8186 }
   8187 static inline nir_ssa_def *
   8188 _nir_build_load_ray_hit_kind(nir_builder *build)
   8189 {
   8190    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8191       build->shader, nir_intrinsic_load_ray_hit_kind);
   8192 
   8193       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8194 
   8195    nir_builder_instr_insert(build, &intrin->instr);
   8196    return &intrin->dest.ssa;
   8197 }
   8198 static inline nir_ssa_def *
   8199 _nir_build_load_ray_hit_sbt_addr_intel(nir_builder *build)
   8200 {
   8201    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8202       build->shader, nir_intrinsic_load_ray_hit_sbt_addr_intel);
   8203 
   8204       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   8205 
   8206    nir_builder_instr_insert(build, &intrin->instr);
   8207    return &intrin->dest.ssa;
   8208 }
   8209 static inline nir_ssa_def *
   8210 _nir_build_load_ray_hit_sbt_stride_intel(nir_builder *build)
   8211 {
   8212    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8213       build->shader, nir_intrinsic_load_ray_hit_sbt_stride_intel);
   8214 
   8215       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 16, NULL);
   8216 
   8217    nir_builder_instr_insert(build, &intrin->instr);
   8218    return &intrin->dest.ssa;
   8219 }
   8220 static inline nir_ssa_def *
   8221 _nir_build_load_ray_hw_stack_size_intel(nir_builder *build)
   8222 {
   8223    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8224       build->shader, nir_intrinsic_load_ray_hw_stack_size_intel);
   8225 
   8226       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8227 
   8228    nir_builder_instr_insert(build, &intrin->instr);
   8229    return &intrin->dest.ssa;
   8230 }
   8231 static inline nir_ssa_def *
   8232 _nir_build_load_ray_instance_custom_index(nir_builder *build)
   8233 {
   8234    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8235       build->shader, nir_intrinsic_load_ray_instance_custom_index);
   8236 
   8237       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8238 
   8239    nir_builder_instr_insert(build, &intrin->instr);
   8240    return &intrin->dest.ssa;
   8241 }
   8242 static inline nir_ssa_def *
   8243 _nir_build_load_ray_launch_id(nir_builder *build)
   8244 {
   8245    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8246       build->shader, nir_intrinsic_load_ray_launch_id);
   8247 
   8248       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8249 
   8250    nir_builder_instr_insert(build, &intrin->instr);
   8251    return &intrin->dest.ssa;
   8252 }
   8253 static inline nir_ssa_def *
   8254 _nir_build_load_ray_launch_size(nir_builder *build)
   8255 {
   8256    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8257       build->shader, nir_intrinsic_load_ray_launch_size);
   8258 
   8259       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8260 
   8261    nir_builder_instr_insert(build, &intrin->instr);
   8262    return &intrin->dest.ssa;
   8263 }
   8264 static inline nir_ssa_def *
   8265 _nir_build_load_ray_miss_sbt_addr_intel(nir_builder *build)
   8266 {
   8267    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8268       build->shader, nir_intrinsic_load_ray_miss_sbt_addr_intel);
   8269 
   8270       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   8271 
   8272    nir_builder_instr_insert(build, &intrin->instr);
   8273    return &intrin->dest.ssa;
   8274 }
   8275 static inline nir_ssa_def *
   8276 _nir_build_load_ray_miss_sbt_stride_intel(nir_builder *build)
   8277 {
   8278    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8279       build->shader, nir_intrinsic_load_ray_miss_sbt_stride_intel);
   8280 
   8281       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 16, NULL);
   8282 
   8283    nir_builder_instr_insert(build, &intrin->instr);
   8284    return &intrin->dest.ssa;
   8285 }
   8286 static inline nir_ssa_def *
   8287 _nir_build_load_ray_num_dss_rt_stacks_intel(nir_builder *build)
   8288 {
   8289    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8290       build->shader, nir_intrinsic_load_ray_num_dss_rt_stacks_intel);
   8291 
   8292       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8293 
   8294    nir_builder_instr_insert(build, &intrin->instr);
   8295    return &intrin->dest.ssa;
   8296 }
   8297 static inline nir_ssa_def *
   8298 _nir_build_load_ray_object_direction(nir_builder *build)
   8299 {
   8300    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8301       build->shader, nir_intrinsic_load_ray_object_direction);
   8302 
   8303       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8304 
   8305    nir_builder_instr_insert(build, &intrin->instr);
   8306    return &intrin->dest.ssa;
   8307 }
   8308 static inline nir_ssa_def *
   8309 _nir_build_load_ray_object_origin(nir_builder *build)
   8310 {
   8311    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8312       build->shader, nir_intrinsic_load_ray_object_origin);
   8313 
   8314       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8315 
   8316    nir_builder_instr_insert(build, &intrin->instr);
   8317    return &intrin->dest.ssa;
   8318 }
   8319 static inline nir_ssa_def *
   8320 _nir_build_load_ray_object_to_world(nir_builder *build, struct _nir_load_ray_object_to_world_indices indices)
   8321 {
   8322    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8323       build->shader, nir_intrinsic_load_ray_object_to_world);
   8324 
   8325       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8326    nir_intrinsic_set_column(intrin, indices.column);
   8327 
   8328    nir_builder_instr_insert(build, &intrin->instr);
   8329    return &intrin->dest.ssa;
   8330 }
   8331 static inline nir_ssa_def *
   8332 _nir_build_load_ray_sw_stack_size_intel(nir_builder *build)
   8333 {
   8334    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8335       build->shader, nir_intrinsic_load_ray_sw_stack_size_intel);
   8336 
   8337       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8338 
   8339    nir_builder_instr_insert(build, &intrin->instr);
   8340    return &intrin->dest.ssa;
   8341 }
   8342 static inline nir_ssa_def *
   8343 _nir_build_load_ray_t_max(nir_builder *build)
   8344 {
   8345    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8346       build->shader, nir_intrinsic_load_ray_t_max);
   8347 
   8348       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8349 
   8350    nir_builder_instr_insert(build, &intrin->instr);
   8351    return &intrin->dest.ssa;
   8352 }
   8353 static inline nir_ssa_def *
   8354 _nir_build_load_ray_t_min(nir_builder *build)
   8355 {
   8356    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8357       build->shader, nir_intrinsic_load_ray_t_min);
   8358 
   8359       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8360 
   8361    nir_builder_instr_insert(build, &intrin->instr);
   8362    return &intrin->dest.ssa;
   8363 }
   8364 static inline nir_ssa_def *
   8365 _nir_build_load_ray_world_direction(nir_builder *build)
   8366 {
   8367    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8368       build->shader, nir_intrinsic_load_ray_world_direction);
   8369 
   8370       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8371 
   8372    nir_builder_instr_insert(build, &intrin->instr);
   8373    return &intrin->dest.ssa;
   8374 }
   8375 static inline nir_ssa_def *
   8376 _nir_build_load_ray_world_origin(nir_builder *build)
   8377 {
   8378    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8379       build->shader, nir_intrinsic_load_ray_world_origin);
   8380 
   8381       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8382 
   8383    nir_builder_instr_insert(build, &intrin->instr);
   8384    return &intrin->dest.ssa;
   8385 }
   8386 static inline nir_ssa_def *
   8387 _nir_build_load_ray_world_to_object(nir_builder *build, struct _nir_load_ray_world_to_object_indices indices)
   8388 {
   8389    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8390       build->shader, nir_intrinsic_load_ray_world_to_object);
   8391 
   8392       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8393    nir_intrinsic_set_column(intrin, indices.column);
   8394 
   8395    nir_builder_instr_insert(build, &intrin->instr);
   8396    return &intrin->dest.ssa;
   8397 }
   8398 static inline nir_ssa_def *
   8399 _nir_build_load_rel_patch_id_ir3(nir_builder *build)
   8400 {
   8401    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8402       build->shader, nir_intrinsic_load_rel_patch_id_ir3);
   8403 
   8404       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8405 
   8406    nir_builder_instr_insert(build, &intrin->instr);
   8407    return &intrin->dest.ssa;
   8408 }
   8409 static inline nir_ssa_def *
   8410 _nir_build_load_reloc_const_intel(nir_builder *build, struct _nir_load_reloc_const_intel_indices indices)
   8411 {
   8412    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8413       build->shader, nir_intrinsic_load_reloc_const_intel);
   8414 
   8415       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8416    nir_intrinsic_set_param_idx(intrin, indices.param_idx);
   8417 
   8418    nir_builder_instr_insert(build, &intrin->instr);
   8419    return &intrin->dest.ssa;
   8420 }
   8421 static inline nir_ssa_def *
   8422 _nir_build_load_ring_es2gs_offset_amd(nir_builder *build)
   8423 {
   8424    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8425       build->shader, nir_intrinsic_load_ring_es2gs_offset_amd);
   8426 
   8427       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8428 
   8429    nir_builder_instr_insert(build, &intrin->instr);
   8430    return &intrin->dest.ssa;
   8431 }
   8432 static inline nir_ssa_def *
   8433 _nir_build_load_ring_esgs_amd(nir_builder *build)
   8434 {
   8435    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8436       build->shader, nir_intrinsic_load_ring_esgs_amd);
   8437 
   8438       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   8439 
   8440    nir_builder_instr_insert(build, &intrin->instr);
   8441    return &intrin->dest.ssa;
   8442 }
   8443 static inline nir_ssa_def *
   8444 _nir_build_load_ring_tess_factors_amd(nir_builder *build)
   8445 {
   8446    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8447       build->shader, nir_intrinsic_load_ring_tess_factors_amd);
   8448 
   8449       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   8450 
   8451    nir_builder_instr_insert(build, &intrin->instr);
   8452    return &intrin->dest.ssa;
   8453 }
   8454 static inline nir_ssa_def *
   8455 _nir_build_load_ring_tess_factors_offset_amd(nir_builder *build)
   8456 {
   8457    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8458       build->shader, nir_intrinsic_load_ring_tess_factors_offset_amd);
   8459 
   8460       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8461 
   8462    nir_builder_instr_insert(build, &intrin->instr);
   8463    return &intrin->dest.ssa;
   8464 }
   8465 static inline nir_ssa_def *
   8466 _nir_build_load_ring_tess_offchip_amd(nir_builder *build)
   8467 {
   8468    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8469       build->shader, nir_intrinsic_load_ring_tess_offchip_amd);
   8470 
   8471       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   8472 
   8473    nir_builder_instr_insert(build, &intrin->instr);
   8474    return &intrin->dest.ssa;
   8475 }
   8476 static inline nir_ssa_def *
   8477 _nir_build_load_ring_tess_offchip_offset_amd(nir_builder *build)
   8478 {
   8479    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8480       build->shader, nir_intrinsic_load_ring_tess_offchip_offset_amd);
   8481 
   8482       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8483 
   8484    nir_builder_instr_insert(build, &intrin->instr);
   8485    return &intrin->dest.ssa;
   8486 }
   8487 static inline nir_ssa_def *
   8488 _nir_build_load_rt_arg_scratch_offset_amd(nir_builder *build)
   8489 {
   8490    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8491       build->shader, nir_intrinsic_load_rt_arg_scratch_offset_amd);
   8492 
   8493       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8494 
   8495    nir_builder_instr_insert(build, &intrin->instr);
   8496    return &intrin->dest.ssa;
   8497 }
   8498 static inline nir_ssa_def *
   8499 _nir_build_load_sample_id(nir_builder *build)
   8500 {
   8501    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8502       build->shader, nir_intrinsic_load_sample_id);
   8503 
   8504       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8505 
   8506    nir_builder_instr_insert(build, &intrin->instr);
   8507    return &intrin->dest.ssa;
   8508 }
   8509 static inline nir_ssa_def *
   8510 _nir_build_load_sample_id_no_per_sample(nir_builder *build)
   8511 {
   8512    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8513       build->shader, nir_intrinsic_load_sample_id_no_per_sample);
   8514 
   8515       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8516 
   8517    nir_builder_instr_insert(build, &intrin->instr);
   8518    return &intrin->dest.ssa;
   8519 }
   8520 static inline nir_ssa_def *
   8521 _nir_build_load_sample_mask_in(nir_builder *build)
   8522 {
   8523    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8524       build->shader, nir_intrinsic_load_sample_mask_in);
   8525 
   8526       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8527 
   8528    nir_builder_instr_insert(build, &intrin->instr);
   8529    return &intrin->dest.ssa;
   8530 }
   8531 static inline nir_ssa_def *
   8532 _nir_build_load_sample_pos(nir_builder *build)
   8533 {
   8534    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8535       build->shader, nir_intrinsic_load_sample_pos);
   8536 
   8537       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   8538 
   8539    nir_builder_instr_insert(build, &intrin->instr);
   8540    return &intrin->dest.ssa;
   8541 }
   8542 static inline nir_ssa_def *
   8543 _nir_build_load_sample_pos_from_id(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   8544 {
   8545    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8546       build->shader, nir_intrinsic_load_sample_pos_from_id);
   8547 
   8548       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   8549    intrin->src[0] = nir_src_for_ssa(src0);
   8550 
   8551    nir_builder_instr_insert(build, &intrin->instr);
   8552    return &intrin->dest.ssa;
   8553 }
   8554 static inline nir_ssa_def *
   8555 _nir_build_load_sample_positions_pan(nir_builder *build)
   8556 {
   8557    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8558       build->shader, nir_intrinsic_load_sample_positions_pan);
   8559 
   8560       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   8561 
   8562    nir_builder_instr_insert(build, &intrin->instr);
   8563    return &intrin->dest.ssa;
   8564 }
   8565 static inline nir_ssa_def *
   8566 _nir_build_load_sampler_lod_parameters_pan(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0)
   8567 {
   8568    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8569       build->shader, nir_intrinsic_load_sampler_lod_parameters_pan);
   8570 
   8571    intrin->num_components = num_components;
   8572       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8573    intrin->src[0] = nir_src_for_ssa(src0);
   8574 
   8575    nir_builder_instr_insert(build, &intrin->instr);
   8576    return &intrin->dest.ssa;
   8577 }
   8578 static inline nir_ssa_def *
   8579 _nir_build_load_sbt_amd(nir_builder *build, struct _nir_load_sbt_amd_indices indices)
   8580 {
   8581    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8582       build->shader, nir_intrinsic_load_sbt_amd);
   8583 
   8584       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   8585    nir_intrinsic_set_binding(intrin, indices.binding);
   8586 
   8587    nir_builder_instr_insert(build, &intrin->instr);
   8588    return &intrin->dest.ssa;
   8589 }
   8590 static inline nir_ssa_def *
   8591 _nir_build_load_scratch(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_scratch_indices indices)
   8592 {
   8593    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8594       build->shader, nir_intrinsic_load_scratch);
   8595 
   8596    intrin->num_components = num_components;
   8597       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8598    intrin->src[0] = nir_src_for_ssa(src0);
   8599    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8600    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8601 
   8602    nir_builder_instr_insert(build, &intrin->instr);
   8603    return &intrin->dest.ssa;
   8604 }
   8605 static inline nir_ssa_def *
   8606 _nir_build_load_scratch_base_ptr(nir_builder *build, unsigned num_components, unsigned bit_size, struct _nir_load_scratch_base_ptr_indices indices)
   8607 {
   8608    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8609       build->shader, nir_intrinsic_load_scratch_base_ptr);
   8610 
   8611    intrin->num_components = num_components;
   8612       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8613    nir_intrinsic_set_base(intrin, indices.base);
   8614 
   8615    nir_builder_instr_insert(build, &intrin->instr);
   8616    return &intrin->dest.ssa;
   8617 }
   8618 static inline nir_ssa_def *
   8619 _nir_build_load_scratch_dxil(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0)
   8620 {
   8621    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8622       build->shader, nir_intrinsic_load_scratch_dxil);
   8623 
   8624    intrin->num_components = num_components;
   8625       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8626    intrin->src[0] = nir_src_for_ssa(src0);
   8627 
   8628    nir_builder_instr_insert(build, &intrin->instr);
   8629    return &intrin->dest.ssa;
   8630 }
   8631 static inline nir_ssa_def *
   8632 _nir_build_load_shader_query_enabled_amd(nir_builder *build)
   8633 {
   8634    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8635       build->shader, nir_intrinsic_load_shader_query_enabled_amd);
   8636 
   8637       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1, NULL);
   8638 
   8639    nir_builder_instr_insert(build, &intrin->instr);
   8640    return &intrin->dest.ssa;
   8641 }
   8642 static inline nir_ssa_def *
   8643 _nir_build_load_shader_record_ptr(nir_builder *build)
   8644 {
   8645    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8646       build->shader, nir_intrinsic_load_shader_record_ptr);
   8647 
   8648       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 64, NULL);
   8649 
   8650    nir_builder_instr_insert(build, &intrin->instr);
   8651    return &intrin->dest.ssa;
   8652 }
   8653 static inline nir_ssa_def *
   8654 _nir_build_load_shared(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_shared_indices indices)
   8655 {
   8656    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8657       build->shader, nir_intrinsic_load_shared);
   8658 
   8659    intrin->num_components = num_components;
   8660       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8661    intrin->src[0] = nir_src_for_ssa(src0);
   8662    nir_intrinsic_set_base(intrin, indices.base);
   8663    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8664    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8665 
   8666    nir_builder_instr_insert(build, &intrin->instr);
   8667    return &intrin->dest.ssa;
   8668 }
   8669 static inline nir_ssa_def *
   8670 _nir_build_load_shared_base_ptr(nir_builder *build, unsigned num_components, unsigned bit_size)
   8671 {
   8672    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8673       build->shader, nir_intrinsic_load_shared_base_ptr);
   8674 
   8675    intrin->num_components = num_components;
   8676       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8677 
   8678    nir_builder_instr_insert(build, &intrin->instr);
   8679    return &intrin->dest.ssa;
   8680 }
   8681 static inline nir_ssa_def *
   8682 _nir_build_load_shared_block_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_shared_block_intel_indices indices)
   8683 {
   8684    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8685       build->shader, nir_intrinsic_load_shared_block_intel);
   8686 
   8687    intrin->num_components = num_components;
   8688       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8689    intrin->src[0] = nir_src_for_ssa(src0);
   8690    nir_intrinsic_set_base(intrin, indices.base);
   8691    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8692    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8693 
   8694    nir_builder_instr_insert(build, &intrin->instr);
   8695    return &intrin->dest.ssa;
   8696 }
   8697 static inline nir_ssa_def *
   8698 _nir_build_load_shared_dxil(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0)
   8699 {
   8700    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8701       build->shader, nir_intrinsic_load_shared_dxil);
   8702 
   8703    intrin->num_components = num_components;
   8704       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8705    intrin->src[0] = nir_src_for_ssa(src0);
   8706 
   8707    nir_builder_instr_insert(build, &intrin->instr);
   8708    return &intrin->dest.ssa;
   8709 }
   8710 static inline nir_ssa_def *
   8711 _nir_build_load_shared_ir3(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_shared_ir3_indices indices)
   8712 {
   8713    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8714       build->shader, nir_intrinsic_load_shared_ir3);
   8715 
   8716    intrin->num_components = num_components;
   8717       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8718    intrin->src[0] = nir_src_for_ssa(src0);
   8719    nir_intrinsic_set_base(intrin, indices.base);
   8720    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8721    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8722 
   8723    nir_builder_instr_insert(build, &intrin->instr);
   8724    return &intrin->dest.ssa;
   8725 }
   8726 static inline nir_ssa_def *
   8727 _nir_build_load_simd_width_intel(nir_builder *build)
   8728 {
   8729    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8730       build->shader, nir_intrinsic_load_simd_width_intel);
   8731 
   8732       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8733 
   8734    nir_builder_instr_insert(build, &intrin->instr);
   8735    return &intrin->dest.ssa;
   8736 }
   8737 static inline nir_ssa_def *
   8738 _nir_build_load_size_ir3(nir_builder *build, unsigned bit_size)
   8739 {
   8740    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8741       build->shader, nir_intrinsic_load_size_ir3);
   8742 
   8743       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   8744 
   8745    nir_builder_instr_insert(build, &intrin->instr);
   8746    return &intrin->dest.ssa;
   8747 }
   8748 static inline nir_ssa_def *
   8749 _nir_build_load_ssbo(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_ssbo_indices indices)
   8750 {
   8751    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8752       build->shader, nir_intrinsic_load_ssbo);
   8753 
   8754    intrin->num_components = num_components;
   8755       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8756    intrin->src[0] = nir_src_for_ssa(src0);
   8757    intrin->src[1] = nir_src_for_ssa(src1);
   8758    nir_intrinsic_set_access(intrin, indices.access);
   8759    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8760    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8761 
   8762    nir_builder_instr_insert(build, &intrin->instr);
   8763    return &intrin->dest.ssa;
   8764 }
   8765 static inline nir_ssa_def *
   8766 _nir_build_load_ssbo_address(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0)
   8767 {
   8768    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8769       build->shader, nir_intrinsic_load_ssbo_address);
   8770 
   8771    intrin->num_components = num_components;
   8772       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8773    intrin->src[0] = nir_src_for_ssa(src0);
   8774 
   8775    nir_builder_instr_insert(build, &intrin->instr);
   8776    return &intrin->dest.ssa;
   8777 }
   8778 static inline nir_ssa_def *
   8779 _nir_build_load_ssbo_block_intel(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_ssbo_block_intel_indices indices)
   8780 {
   8781    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8782       build->shader, nir_intrinsic_load_ssbo_block_intel);
   8783 
   8784    intrin->num_components = num_components;
   8785       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8786    intrin->src[0] = nir_src_for_ssa(src0);
   8787    intrin->src[1] = nir_src_for_ssa(src1);
   8788    nir_intrinsic_set_access(intrin, indices.access);
   8789    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8790    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8791 
   8792    nir_builder_instr_insert(build, &intrin->instr);
   8793    return &intrin->dest.ssa;
   8794 }
   8795 static inline nir_ssa_def *
   8796 _nir_build_load_ssbo_ir3(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_load_ssbo_ir3_indices indices)
   8797 {
   8798    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8799       build->shader, nir_intrinsic_load_ssbo_ir3);
   8800 
   8801    intrin->num_components = num_components;
   8802       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8803    intrin->src[0] = nir_src_for_ssa(src0);
   8804    intrin->src[1] = nir_src_for_ssa(src1);
   8805    intrin->src[2] = nir_src_for_ssa(src2);
   8806    nir_intrinsic_set_access(intrin, indices.access);
   8807    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   8808    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   8809 
   8810    nir_builder_instr_insert(build, &intrin->instr);
   8811    return &intrin->dest.ssa;
   8812 }
   8813 static inline nir_ssa_def *
   8814 _nir_build_load_subgroup_eq_mask(nir_builder *build, unsigned num_components, unsigned bit_size)
   8815 {
   8816    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8817       build->shader, nir_intrinsic_load_subgroup_eq_mask);
   8818 
   8819    intrin->num_components = num_components;
   8820       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8821 
   8822    nir_builder_instr_insert(build, &intrin->instr);
   8823    return &intrin->dest.ssa;
   8824 }
   8825 static inline nir_ssa_def *
   8826 _nir_build_load_subgroup_ge_mask(nir_builder *build, unsigned num_components, unsigned bit_size)
   8827 {
   8828    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8829       build->shader, nir_intrinsic_load_subgroup_ge_mask);
   8830 
   8831    intrin->num_components = num_components;
   8832       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8833 
   8834    nir_builder_instr_insert(build, &intrin->instr);
   8835    return &intrin->dest.ssa;
   8836 }
   8837 static inline nir_ssa_def *
   8838 _nir_build_load_subgroup_gt_mask(nir_builder *build, unsigned num_components, unsigned bit_size)
   8839 {
   8840    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8841       build->shader, nir_intrinsic_load_subgroup_gt_mask);
   8842 
   8843    intrin->num_components = num_components;
   8844       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8845 
   8846    nir_builder_instr_insert(build, &intrin->instr);
   8847    return &intrin->dest.ssa;
   8848 }
   8849 static inline nir_ssa_def *
   8850 _nir_build_load_subgroup_id(nir_builder *build)
   8851 {
   8852    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8853       build->shader, nir_intrinsic_load_subgroup_id);
   8854 
   8855       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8856 
   8857    nir_builder_instr_insert(build, &intrin->instr);
   8858    return &intrin->dest.ssa;
   8859 }
   8860 static inline nir_ssa_def *
   8861 _nir_build_load_subgroup_id_shift_ir3(nir_builder *build)
   8862 {
   8863    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8864       build->shader, nir_intrinsic_load_subgroup_id_shift_ir3);
   8865 
   8866       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8867 
   8868    nir_builder_instr_insert(build, &intrin->instr);
   8869    return &intrin->dest.ssa;
   8870 }
   8871 static inline nir_ssa_def *
   8872 _nir_build_load_subgroup_invocation(nir_builder *build)
   8873 {
   8874    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8875       build->shader, nir_intrinsic_load_subgroup_invocation);
   8876 
   8877       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8878 
   8879    nir_builder_instr_insert(build, &intrin->instr);
   8880    return &intrin->dest.ssa;
   8881 }
   8882 static inline nir_ssa_def *
   8883 _nir_build_load_subgroup_le_mask(nir_builder *build, unsigned num_components, unsigned bit_size)
   8884 {
   8885    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8886       build->shader, nir_intrinsic_load_subgroup_le_mask);
   8887 
   8888    intrin->num_components = num_components;
   8889       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8890 
   8891    nir_builder_instr_insert(build, &intrin->instr);
   8892    return &intrin->dest.ssa;
   8893 }
   8894 static inline nir_ssa_def *
   8895 _nir_build_load_subgroup_lt_mask(nir_builder *build, unsigned num_components, unsigned bit_size)
   8896 {
   8897    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8898       build->shader, nir_intrinsic_load_subgroup_lt_mask);
   8899 
   8900    intrin->num_components = num_components;
   8901       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   8902 
   8903    nir_builder_instr_insert(build, &intrin->instr);
   8904    return &intrin->dest.ssa;
   8905 }
   8906 static inline nir_ssa_def *
   8907 _nir_build_load_subgroup_size(nir_builder *build)
   8908 {
   8909    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8910       build->shader, nir_intrinsic_load_subgroup_size);
   8911 
   8912       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8913 
   8914    nir_builder_instr_insert(build, &intrin->instr);
   8915    return &intrin->dest.ssa;
   8916 }
   8917 static inline nir_ssa_def *
   8918 _nir_build_load_tcs_header_ir3(nir_builder *build)
   8919 {
   8920    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8921       build->shader, nir_intrinsic_load_tcs_header_ir3);
   8922 
   8923       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8924 
   8925    nir_builder_instr_insert(build, &intrin->instr);
   8926    return &intrin->dest.ssa;
   8927 }
   8928 static inline nir_ssa_def *
   8929 _nir_build_load_tcs_in_param_base_r600(nir_builder *build)
   8930 {
   8931    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8932       build->shader, nir_intrinsic_load_tcs_in_param_base_r600);
   8933 
   8934       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   8935 
   8936    nir_builder_instr_insert(build, &intrin->instr);
   8937    return &intrin->dest.ssa;
   8938 }
   8939 static inline nir_ssa_def *
   8940 _nir_build_load_tcs_num_patches_amd(nir_builder *build)
   8941 {
   8942    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8943       build->shader, nir_intrinsic_load_tcs_num_patches_amd);
   8944 
   8945       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8946 
   8947    nir_builder_instr_insert(build, &intrin->instr);
   8948    return &intrin->dest.ssa;
   8949 }
   8950 static inline nir_ssa_def *
   8951 _nir_build_load_tcs_out_param_base_r600(nir_builder *build)
   8952 {
   8953    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8954       build->shader, nir_intrinsic_load_tcs_out_param_base_r600);
   8955 
   8956       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   8957 
   8958    nir_builder_instr_insert(build, &intrin->instr);
   8959    return &intrin->dest.ssa;
   8960 }
   8961 static inline nir_ssa_def *
   8962 _nir_build_load_tcs_rel_patch_id_r600(nir_builder *build)
   8963 {
   8964    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8965       build->shader, nir_intrinsic_load_tcs_rel_patch_id_r600);
   8966 
   8967       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8968 
   8969    nir_builder_instr_insert(build, &intrin->instr);
   8970    return &intrin->dest.ssa;
   8971 }
   8972 static inline nir_ssa_def *
   8973 _nir_build_load_tcs_tess_factor_base_r600(nir_builder *build)
   8974 {
   8975    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8976       build->shader, nir_intrinsic_load_tcs_tess_factor_base_r600);
   8977 
   8978       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   8979 
   8980    nir_builder_instr_insert(build, &intrin->instr);
   8981    return &intrin->dest.ssa;
   8982 }
   8983 static inline nir_ssa_def *
   8984 _nir_build_load_tess_coord(nir_builder *build)
   8985 {
   8986    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8987       build->shader, nir_intrinsic_load_tess_coord);
   8988 
   8989       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   8990 
   8991    nir_builder_instr_insert(build, &intrin->instr);
   8992    return &intrin->dest.ssa;
   8993 }
   8994 static inline nir_ssa_def *
   8995 _nir_build_load_tess_coord_r600(nir_builder *build)
   8996 {
   8997    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   8998       build->shader, nir_intrinsic_load_tess_coord_r600);
   8999 
   9000       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   9001 
   9002    nir_builder_instr_insert(build, &intrin->instr);
   9003    return &intrin->dest.ssa;
   9004 }
   9005 static inline nir_ssa_def *
   9006 _nir_build_load_tess_factor_base_ir3(nir_builder *build)
   9007 {
   9008    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9009       build->shader, nir_intrinsic_load_tess_factor_base_ir3);
   9010 
   9011       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   9012 
   9013    nir_builder_instr_insert(build, &intrin->instr);
   9014    return &intrin->dest.ssa;
   9015 }
   9016 static inline nir_ssa_def *
   9017 _nir_build_load_tess_level_inner(nir_builder *build)
   9018 {
   9019    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9020       build->shader, nir_intrinsic_load_tess_level_inner);
   9021 
   9022       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   9023 
   9024    nir_builder_instr_insert(build, &intrin->instr);
   9025    return &intrin->dest.ssa;
   9026 }
   9027 static inline nir_ssa_def *
   9028 _nir_build_load_tess_level_inner_default(nir_builder *build)
   9029 {
   9030    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9031       build->shader, nir_intrinsic_load_tess_level_inner_default);
   9032 
   9033       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   9034 
   9035    nir_builder_instr_insert(build, &intrin->instr);
   9036    return &intrin->dest.ssa;
   9037 }
   9038 static inline nir_ssa_def *
   9039 _nir_build_load_tess_level_outer(nir_builder *build)
   9040 {
   9041    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9042       build->shader, nir_intrinsic_load_tess_level_outer);
   9043 
   9044       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   9045 
   9046    nir_builder_instr_insert(build, &intrin->instr);
   9047    return &intrin->dest.ssa;
   9048 }
   9049 static inline nir_ssa_def *
   9050 _nir_build_load_tess_level_outer_default(nir_builder *build)
   9051 {
   9052    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9053       build->shader, nir_intrinsic_load_tess_level_outer_default);
   9054 
   9055       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   9056 
   9057    nir_builder_instr_insert(build, &intrin->instr);
   9058    return &intrin->dest.ssa;
   9059 }
   9060 static inline nir_ssa_def *
   9061 _nir_build_load_tess_param_base_ir3(nir_builder *build)
   9062 {
   9063    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9064       build->shader, nir_intrinsic_load_tess_param_base_ir3);
   9065 
   9066       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   9067 
   9068    nir_builder_instr_insert(build, &intrin->instr);
   9069    return &intrin->dest.ssa;
   9070 }
   9071 static inline nir_ssa_def *
   9072 _nir_build_load_tess_rel_patch_id_amd(nir_builder *build)
   9073 {
   9074    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9075       build->shader, nir_intrinsic_load_tess_rel_patch_id_amd);
   9076 
   9077       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9078 
   9079    nir_builder_instr_insert(build, &intrin->instr);
   9080    return &intrin->dest.ssa;
   9081 }
   9082 static inline nir_ssa_def *
   9083 _nir_build_load_texture_rect_scaling(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   9084 {
   9085    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9086       build->shader, nir_intrinsic_load_texture_rect_scaling);
   9087 
   9088       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, bit_size, NULL);
   9089    intrin->src[0] = nir_src_for_ssa(src0);
   9090 
   9091    nir_builder_instr_insert(build, &intrin->instr);
   9092    return &intrin->dest.ssa;
   9093 }
   9094 static inline nir_ssa_def *
   9095 _nir_build_load_tlb_color_v3d(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_tlb_color_v3d_indices indices)
   9096 {
   9097    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9098       build->shader, nir_intrinsic_load_tlb_color_v3d);
   9099 
   9100    intrin->num_components = num_components;
   9101       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9102    intrin->src[0] = nir_src_for_ssa(src0);
   9103    nir_intrinsic_set_base(intrin, indices.base);
   9104    nir_intrinsic_set_component(intrin, indices.component);
   9105 
   9106    nir_builder_instr_insert(build, &intrin->instr);
   9107    return &intrin->dest.ssa;
   9108 }
   9109 static inline nir_ssa_def *
   9110 _nir_build_load_ubo(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_ubo_indices indices)
   9111 {
   9112    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9113       build->shader, nir_intrinsic_load_ubo);
   9114 
   9115    intrin->num_components = num_components;
   9116       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9117    intrin->src[0] = nir_src_for_ssa(src0);
   9118    intrin->src[1] = nir_src_for_ssa(src1);
   9119    nir_intrinsic_set_access(intrin, indices.access);
   9120    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   9121    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   9122    nir_intrinsic_set_range_base(intrin, indices.range_base);
   9123    nir_intrinsic_set_range(intrin, indices.range);
   9124 
   9125    nir_builder_instr_insert(build, &intrin->instr);
   9126    return &intrin->dest.ssa;
   9127 }
   9128 static inline nir_ssa_def *
   9129 _nir_build_load_ubo_dxil(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9130 {
   9131    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9132       build->shader, nir_intrinsic_load_ubo_dxil);
   9133 
   9134    intrin->num_components = num_components;
   9135       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9136    intrin->src[0] = nir_src_for_ssa(src0);
   9137    intrin->src[1] = nir_src_for_ssa(src1);
   9138 
   9139    nir_builder_instr_insert(build, &intrin->instr);
   9140    return &intrin->dest.ssa;
   9141 }
   9142 static inline nir_ssa_def *
   9143 _nir_build_load_ubo_vec4(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_load_ubo_vec4_indices indices)
   9144 {
   9145    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9146       build->shader, nir_intrinsic_load_ubo_vec4);
   9147 
   9148    intrin->num_components = num_components;
   9149       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9150    intrin->src[0] = nir_src_for_ssa(src0);
   9151    intrin->src[1] = nir_src_for_ssa(src1);
   9152    nir_intrinsic_set_access(intrin, indices.access);
   9153    nir_intrinsic_set_component(intrin, indices.component);
   9154 
   9155    nir_builder_instr_insert(build, &intrin->instr);
   9156    return &intrin->dest.ssa;
   9157 }
   9158 static inline nir_ssa_def *
   9159 _nir_build_load_uniform(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_uniform_indices indices)
   9160 {
   9161    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9162       build->shader, nir_intrinsic_load_uniform);
   9163 
   9164    intrin->num_components = num_components;
   9165       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9166    intrin->src[0] = nir_src_for_ssa(src0);
   9167    nir_intrinsic_set_base(intrin, indices.base);
   9168    nir_intrinsic_set_range(intrin, indices.range);
   9169    nir_intrinsic_set_dest_type(intrin, indices.dest_type);
   9170 
   9171    nir_builder_instr_insert(build, &intrin->instr);
   9172    return &intrin->dest.ssa;
   9173 }
   9174 static inline nir_ssa_def *
   9175 _nir_build_load_user_clip_plane(nir_builder *build, struct _nir_load_user_clip_plane_indices indices)
   9176 {
   9177    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9178       build->shader, nir_intrinsic_load_user_clip_plane);
   9179 
   9180       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   9181    nir_intrinsic_set_ucp_id(intrin, indices.ucp_id);
   9182 
   9183    nir_builder_instr_insert(build, &intrin->instr);
   9184    return &intrin->dest.ssa;
   9185 }
   9186 static inline nir_ssa_def *
   9187 _nir_build_load_user_data_amd(nir_builder *build)
   9188 {
   9189    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9190       build->shader, nir_intrinsic_load_user_data_amd);
   9191 
   9192       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 4, 32, NULL);
   9193 
   9194    nir_builder_instr_insert(build, &intrin->instr);
   9195    return &intrin->dest.ssa;
   9196 }
   9197 static inline nir_ssa_def *
   9198 _nir_build_load_vertex_id(nir_builder *build)
   9199 {
   9200    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9201       build->shader, nir_intrinsic_load_vertex_id);
   9202 
   9203       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9204 
   9205    nir_builder_instr_insert(build, &intrin->instr);
   9206    return &intrin->dest.ssa;
   9207 }
   9208 static inline nir_ssa_def *
   9209 _nir_build_load_vertex_id_zero_base(nir_builder *build)
   9210 {
   9211    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9212       build->shader, nir_intrinsic_load_vertex_id_zero_base);
   9213 
   9214       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9215 
   9216    nir_builder_instr_insert(build, &intrin->instr);
   9217    return &intrin->dest.ssa;
   9218 }
   9219 static inline nir_ssa_def *
   9220 _nir_build_load_view_index(nir_builder *build)
   9221 {
   9222    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9223       build->shader, nir_intrinsic_load_view_index);
   9224 
   9225       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9226 
   9227    nir_builder_instr_insert(build, &intrin->instr);
   9228    return &intrin->dest.ssa;
   9229 }
   9230 static inline nir_ssa_def *
   9231 _nir_build_load_viewport_offset(nir_builder *build)
   9232 {
   9233    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9234       build->shader, nir_intrinsic_load_viewport_offset);
   9235 
   9236       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   9237 
   9238    nir_builder_instr_insert(build, &intrin->instr);
   9239    return &intrin->dest.ssa;
   9240 }
   9241 static inline nir_ssa_def *
   9242 _nir_build_load_viewport_scale(nir_builder *build)
   9243 {
   9244    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9245       build->shader, nir_intrinsic_load_viewport_scale);
   9246 
   9247       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   9248 
   9249    nir_builder_instr_insert(build, &intrin->instr);
   9250    return &intrin->dest.ssa;
   9251 }
   9252 static inline nir_ssa_def *
   9253 _nir_build_load_viewport_x_offset(nir_builder *build)
   9254 {
   9255    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9256       build->shader, nir_intrinsic_load_viewport_x_offset);
   9257 
   9258       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9259 
   9260    nir_builder_instr_insert(build, &intrin->instr);
   9261    return &intrin->dest.ssa;
   9262 }
   9263 static inline nir_ssa_def *
   9264 _nir_build_load_viewport_x_scale(nir_builder *build)
   9265 {
   9266    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9267       build->shader, nir_intrinsic_load_viewport_x_scale);
   9268 
   9269       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9270 
   9271    nir_builder_instr_insert(build, &intrin->instr);
   9272    return &intrin->dest.ssa;
   9273 }
   9274 static inline nir_ssa_def *
   9275 _nir_build_load_viewport_y_offset(nir_builder *build)
   9276 {
   9277    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9278       build->shader, nir_intrinsic_load_viewport_y_offset);
   9279 
   9280       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9281 
   9282    nir_builder_instr_insert(build, &intrin->instr);
   9283    return &intrin->dest.ssa;
   9284 }
   9285 static inline nir_ssa_def *
   9286 _nir_build_load_viewport_y_scale(nir_builder *build)
   9287 {
   9288    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9289       build->shader, nir_intrinsic_load_viewport_y_scale);
   9290 
   9291       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9292 
   9293    nir_builder_instr_insert(build, &intrin->instr);
   9294    return &intrin->dest.ssa;
   9295 }
   9296 static inline nir_ssa_def *
   9297 _nir_build_load_viewport_z_offset(nir_builder *build)
   9298 {
   9299    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9300       build->shader, nir_intrinsic_load_viewport_z_offset);
   9301 
   9302       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9303 
   9304    nir_builder_instr_insert(build, &intrin->instr);
   9305    return &intrin->dest.ssa;
   9306 }
   9307 static inline nir_ssa_def *
   9308 _nir_build_load_viewport_z_scale(nir_builder *build)
   9309 {
   9310    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9311       build->shader, nir_intrinsic_load_viewport_z_scale);
   9312 
   9313       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9314 
   9315    nir_builder_instr_insert(build, &intrin->instr);
   9316    return &intrin->dest.ssa;
   9317 }
   9318 static inline nir_ssa_def *
   9319 _nir_build_load_vs_primitive_stride_ir3(nir_builder *build)
   9320 {
   9321    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9322       build->shader, nir_intrinsic_load_vs_primitive_stride_ir3);
   9323 
   9324       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9325 
   9326    nir_builder_instr_insert(build, &intrin->instr);
   9327    return &intrin->dest.ssa;
   9328 }
   9329 static inline nir_ssa_def *
   9330 _nir_build_load_vs_vertex_stride_ir3(nir_builder *build)
   9331 {
   9332    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9333       build->shader, nir_intrinsic_load_vs_vertex_stride_ir3);
   9334 
   9335       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9336 
   9337    nir_builder_instr_insert(build, &intrin->instr);
   9338    return &intrin->dest.ssa;
   9339 }
   9340 static inline nir_ssa_def *
   9341 _nir_build_load_vulkan_descriptor(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_load_vulkan_descriptor_indices indices)
   9342 {
   9343    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9344       build->shader, nir_intrinsic_load_vulkan_descriptor);
   9345 
   9346    intrin->num_components = num_components;
   9347       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9348    intrin->src[0] = nir_src_for_ssa(src0);
   9349    nir_intrinsic_set_desc_type(intrin, indices.desc_type);
   9350 
   9351    nir_builder_instr_insert(build, &intrin->instr);
   9352    return &intrin->dest.ssa;
   9353 }
   9354 static inline nir_ssa_def *
   9355 _nir_build_load_work_dim(nir_builder *build)
   9356 {
   9357    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9358       build->shader, nir_intrinsic_load_work_dim);
   9359 
   9360       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9361 
   9362    nir_builder_instr_insert(build, &intrin->instr);
   9363    return &intrin->dest.ssa;
   9364 }
   9365 static inline nir_ssa_def *
   9366 _nir_build_load_workgroup_id(nir_builder *build, unsigned bit_size)
   9367 {
   9368    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9369       build->shader, nir_intrinsic_load_workgroup_id);
   9370 
   9371       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, bit_size, NULL);
   9372 
   9373    nir_builder_instr_insert(build, &intrin->instr);
   9374    return &intrin->dest.ssa;
   9375 }
   9376 static inline nir_ssa_def *
   9377 _nir_build_load_workgroup_id_zero_base(nir_builder *build)
   9378 {
   9379    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9380       build->shader, nir_intrinsic_load_workgroup_id_zero_base);
   9381 
   9382       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   9383 
   9384    nir_builder_instr_insert(build, &intrin->instr);
   9385    return &intrin->dest.ssa;
   9386 }
   9387 static inline nir_ssa_def *
   9388 _nir_build_load_workgroup_num_input_primitives_amd(nir_builder *build)
   9389 {
   9390    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9391       build->shader, nir_intrinsic_load_workgroup_num_input_primitives_amd);
   9392 
   9393       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9394 
   9395    nir_builder_instr_insert(build, &intrin->instr);
   9396    return &intrin->dest.ssa;
   9397 }
   9398 static inline nir_ssa_def *
   9399 _nir_build_load_workgroup_num_input_vertices_amd(nir_builder *build)
   9400 {
   9401    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9402       build->shader, nir_intrinsic_load_workgroup_num_input_vertices_amd);
   9403 
   9404       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9405 
   9406    nir_builder_instr_insert(build, &intrin->instr);
   9407    return &intrin->dest.ssa;
   9408 }
   9409 static inline nir_ssa_def *
   9410 _nir_build_load_workgroup_size(nir_builder *build)
   9411 {
   9412    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9413       build->shader, nir_intrinsic_load_workgroup_size);
   9414 
   9415       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 3, 32, NULL);
   9416 
   9417    nir_builder_instr_insert(build, &intrin->instr);
   9418    return &intrin->dest.ssa;
   9419 }
   9420 static inline nir_ssa_def *
   9421 _nir_build_masked_swizzle_amd(nir_builder *build, nir_ssa_def *src0, struct _nir_masked_swizzle_amd_indices indices)
   9422 {
   9423    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9424       build->shader, nir_intrinsic_masked_swizzle_amd);
   9425 
   9426    intrin->num_components = src0->num_components;
   9427       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   9428    intrin->src[0] = nir_src_for_ssa(src0);
   9429    nir_intrinsic_set_swizzle_mask(intrin, indices.swizzle_mask);
   9430 
   9431    nir_builder_instr_insert(build, &intrin->instr);
   9432    return &intrin->dest.ssa;
   9433 }
   9434 static inline nir_ssa_def *
   9435 _nir_build_mbcnt_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   9436 {
   9437    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9438       build->shader, nir_intrinsic_mbcnt_amd);
   9439 
   9440       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9441    intrin->src[0] = nir_src_for_ssa(src0);
   9442    intrin->src[1] = nir_src_for_ssa(src1);
   9443 
   9444    nir_builder_instr_insert(build, &intrin->instr);
   9445    return &intrin->dest.ssa;
   9446 }
   9447 static inline nir_intrinsic_instr *
   9448 _nir_build_memcpy_deref(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_memcpy_deref_indices indices)
   9449 {
   9450    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9451       build->shader, nir_intrinsic_memcpy_deref);
   9452 
   9453    intrin->src[0] = nir_src_for_ssa(src0);
   9454    intrin->src[1] = nir_src_for_ssa(src1);
   9455    intrin->src[2] = nir_src_for_ssa(src2);
   9456    nir_intrinsic_set_dst_access(intrin, indices.dst_access);
   9457    nir_intrinsic_set_src_access(intrin, indices.src_access);
   9458 
   9459    nir_builder_instr_insert(build, &intrin->instr);
   9460    return intrin;
   9461 }
   9462 static inline nir_intrinsic_instr *
   9463 _nir_build_memory_barrier(nir_builder *build)
   9464 {
   9465    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9466       build->shader, nir_intrinsic_memory_barrier);
   9467 
   9468 
   9469    nir_builder_instr_insert(build, &intrin->instr);
   9470    return intrin;
   9471 }
   9472 static inline nir_intrinsic_instr *
   9473 _nir_build_memory_barrier_atomic_counter(nir_builder *build)
   9474 {
   9475    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9476       build->shader, nir_intrinsic_memory_barrier_atomic_counter);
   9477 
   9478 
   9479    nir_builder_instr_insert(build, &intrin->instr);
   9480    return intrin;
   9481 }
   9482 static inline nir_intrinsic_instr *
   9483 _nir_build_memory_barrier_buffer(nir_builder *build)
   9484 {
   9485    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9486       build->shader, nir_intrinsic_memory_barrier_buffer);
   9487 
   9488 
   9489    nir_builder_instr_insert(build, &intrin->instr);
   9490    return intrin;
   9491 }
   9492 static inline nir_intrinsic_instr *
   9493 _nir_build_memory_barrier_image(nir_builder *build)
   9494 {
   9495    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9496       build->shader, nir_intrinsic_memory_barrier_image);
   9497 
   9498 
   9499    nir_builder_instr_insert(build, &intrin->instr);
   9500    return intrin;
   9501 }
   9502 static inline nir_intrinsic_instr *
   9503 _nir_build_memory_barrier_shared(nir_builder *build)
   9504 {
   9505    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9506       build->shader, nir_intrinsic_memory_barrier_shared);
   9507 
   9508 
   9509    nir_builder_instr_insert(build, &intrin->instr);
   9510    return intrin;
   9511 }
   9512 static inline nir_intrinsic_instr *
   9513 _nir_build_memory_barrier_tcs_patch(nir_builder *build)
   9514 {
   9515    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9516       build->shader, nir_intrinsic_memory_barrier_tcs_patch);
   9517 
   9518 
   9519    nir_builder_instr_insert(build, &intrin->instr);
   9520    return intrin;
   9521 }
   9522 static inline nir_intrinsic_instr *
   9523 _nir_build_nop(nir_builder *build)
   9524 {
   9525    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9526       build->shader, nir_intrinsic_nop);
   9527 
   9528 
   9529    nir_builder_instr_insert(build, &intrin->instr);
   9530    return intrin;
   9531 }
   9532 static inline nir_intrinsic_instr *
   9533 _nir_build_overwrite_tes_arguments_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
   9534 {
   9535    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9536       build->shader, nir_intrinsic_overwrite_tes_arguments_amd);
   9537 
   9538    intrin->src[0] = nir_src_for_ssa(src0);
   9539    intrin->src[1] = nir_src_for_ssa(src1);
   9540    intrin->src[2] = nir_src_for_ssa(src2);
   9541    intrin->src[3] = nir_src_for_ssa(src3);
   9542 
   9543    nir_builder_instr_insert(build, &intrin->instr);
   9544    return intrin;
   9545 }
   9546 static inline nir_intrinsic_instr *
   9547 _nir_build_overwrite_vs_arguments_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   9548 {
   9549    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9550       build->shader, nir_intrinsic_overwrite_vs_arguments_amd);
   9551 
   9552    intrin->src[0] = nir_src_for_ssa(src0);
   9553    intrin->src[1] = nir_src_for_ssa(src1);
   9554 
   9555    nir_builder_instr_insert(build, &intrin->instr);
   9556    return intrin;
   9557 }
   9558 static inline nir_ssa_def *
   9559 _nir_build_printf(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   9560 {
   9561    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9562       build->shader, nir_intrinsic_printf);
   9563 
   9564       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   9565    intrin->src[0] = nir_src_for_ssa(src0);
   9566    intrin->src[1] = nir_src_for_ssa(src1);
   9567 
   9568    nir_builder_instr_insert(build, &intrin->instr);
   9569    return &intrin->dest.ssa;
   9570 }
   9571 static inline nir_ssa_def *
   9572 _nir_build_quad_broadcast(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9573 {
   9574    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9575       build->shader, nir_intrinsic_quad_broadcast);
   9576 
   9577    intrin->num_components = src0->num_components;
   9578       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9579    intrin->src[0] = nir_src_for_ssa(src0);
   9580    intrin->src[1] = nir_src_for_ssa(src1);
   9581 
   9582    nir_builder_instr_insert(build, &intrin->instr);
   9583    return &intrin->dest.ssa;
   9584 }
   9585 static inline nir_ssa_def *
   9586 _nir_build_quad_swap_diagonal(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   9587 {
   9588    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9589       build->shader, nir_intrinsic_quad_swap_diagonal);
   9590 
   9591    intrin->num_components = src0->num_components;
   9592       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9593    intrin->src[0] = nir_src_for_ssa(src0);
   9594 
   9595    nir_builder_instr_insert(build, &intrin->instr);
   9596    return &intrin->dest.ssa;
   9597 }
   9598 static inline nir_ssa_def *
   9599 _nir_build_quad_swap_horizontal(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   9600 {
   9601    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9602       build->shader, nir_intrinsic_quad_swap_horizontal);
   9603 
   9604    intrin->num_components = src0->num_components;
   9605       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9606    intrin->src[0] = nir_src_for_ssa(src0);
   9607 
   9608    nir_builder_instr_insert(build, &intrin->instr);
   9609    return &intrin->dest.ssa;
   9610 }
   9611 static inline nir_ssa_def *
   9612 _nir_build_quad_swap_vertical(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   9613 {
   9614    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9615       build->shader, nir_intrinsic_quad_swap_vertical);
   9616 
   9617    intrin->num_components = src0->num_components;
   9618       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9619    intrin->src[0] = nir_src_for_ssa(src0);
   9620 
   9621    nir_builder_instr_insert(build, &intrin->instr);
   9622    return &intrin->dest.ssa;
   9623 }
   9624 static inline nir_ssa_def *
   9625 _nir_build_quad_swizzle_amd(nir_builder *build, nir_ssa_def *src0, struct _nir_quad_swizzle_amd_indices indices)
   9626 {
   9627    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9628       build->shader, nir_intrinsic_quad_swizzle_amd);
   9629 
   9630    intrin->num_components = src0->num_components;
   9631       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   9632    intrin->src[0] = nir_src_for_ssa(src0);
   9633    nir_intrinsic_set_swizzle_mask(intrin, indices.swizzle_mask);
   9634 
   9635    nir_builder_instr_insert(build, &intrin->instr);
   9636    return &intrin->dest.ssa;
   9637 }
   9638 static inline nir_ssa_def *
   9639 _nir_build_read_first_invocation(nir_builder *build, nir_ssa_def *src0)
   9640 {
   9641    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9642       build->shader, nir_intrinsic_read_first_invocation);
   9643 
   9644    intrin->num_components = src0->num_components;
   9645       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   9646    intrin->src[0] = nir_src_for_ssa(src0);
   9647 
   9648    nir_builder_instr_insert(build, &intrin->instr);
   9649    return &intrin->dest.ssa;
   9650 }
   9651 static inline nir_ssa_def *
   9652 _nir_build_read_invocation(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   9653 {
   9654    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9655       build->shader, nir_intrinsic_read_invocation);
   9656 
   9657    intrin->num_components = src0->num_components;
   9658       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   9659    intrin->src[0] = nir_src_for_ssa(src0);
   9660    intrin->src[1] = nir_src_for_ssa(src1);
   9661 
   9662    nir_builder_instr_insert(build, &intrin->instr);
   9663    return &intrin->dest.ssa;
   9664 }
   9665 static inline nir_ssa_def *
   9666 _nir_build_read_invocation_cond_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9667 {
   9668    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9669       build->shader, nir_intrinsic_read_invocation_cond_ir3);
   9670 
   9671    intrin->num_components = src0->num_components;
   9672       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   9673    intrin->src[0] = nir_src_for_ssa(src0);
   9674    intrin->src[1] = nir_src_for_ssa(src1);
   9675 
   9676    nir_builder_instr_insert(build, &intrin->instr);
   9677    return &intrin->dest.ssa;
   9678 }
   9679 static inline nir_ssa_def *
   9680 _nir_build_reduce(nir_builder *build, nir_ssa_def *src0, struct _nir_reduce_indices indices)
   9681 {
   9682    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9683       build->shader, nir_intrinsic_reduce);
   9684 
   9685    intrin->num_components = src0->num_components;
   9686       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   9687    intrin->src[0] = nir_src_for_ssa(src0);
   9688    nir_intrinsic_set_reduction_op(intrin, indices.reduction_op);
   9689    nir_intrinsic_set_cluster_size(intrin, indices.cluster_size);
   9690 
   9691    nir_builder_instr_insert(build, &intrin->instr);
   9692    return &intrin->dest.ssa;
   9693 }
   9694 static inline nir_ssa_def *
   9695 _nir_build_report_ray_intersection(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9696 {
   9697    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9698       build->shader, nir_intrinsic_report_ray_intersection);
   9699 
   9700       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9701    intrin->src[0] = nir_src_for_ssa(src0);
   9702    intrin->src[1] = nir_src_for_ssa(src1);
   9703 
   9704    nir_builder_instr_insert(build, &intrin->instr);
   9705    return &intrin->dest.ssa;
   9706 }
   9707 static inline nir_intrinsic_instr *
   9708 _nir_build_rt_execute_callable(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_rt_execute_callable_indices indices)
   9709 {
   9710    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9711       build->shader, nir_intrinsic_rt_execute_callable);
   9712 
   9713    intrin->src[0] = nir_src_for_ssa(src0);
   9714    intrin->src[1] = nir_src_for_ssa(src1);
   9715    nir_intrinsic_set_call_idx(intrin, indices.call_idx);
   9716    nir_intrinsic_set_stack_size(intrin, indices.stack_size);
   9717 
   9718    nir_builder_instr_insert(build, &intrin->instr);
   9719    return intrin;
   9720 }
   9721 static inline nir_intrinsic_instr *
   9722 _nir_build_rt_resume(nir_builder *build, struct _nir_rt_resume_indices indices)
   9723 {
   9724    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9725       build->shader, nir_intrinsic_rt_resume);
   9726 
   9727    nir_intrinsic_set_call_idx(intrin, indices.call_idx);
   9728    nir_intrinsic_set_stack_size(intrin, indices.stack_size);
   9729 
   9730    nir_builder_instr_insert(build, &intrin->instr);
   9731    return intrin;
   9732 }
   9733 static inline nir_intrinsic_instr *
   9734 _nir_build_rt_return_amd(nir_builder *build)
   9735 {
   9736    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9737       build->shader, nir_intrinsic_rt_return_amd);
   9738 
   9739 
   9740    nir_builder_instr_insert(build, &intrin->instr);
   9741    return intrin;
   9742 }
   9743 static inline nir_intrinsic_instr *
   9744 _nir_build_rt_trace_ray(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, nir_ssa_def *src5, nir_ssa_def *src6, nir_ssa_def *src7, nir_ssa_def *src8, nir_ssa_def *src9, nir_ssa_def *src10, struct _nir_rt_trace_ray_indices indices)
   9745 {
   9746    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9747       build->shader, nir_intrinsic_rt_trace_ray);
   9748 
   9749    intrin->src[0] = nir_src_for_ssa(src0);
   9750    intrin->src[1] = nir_src_for_ssa(src1);
   9751    intrin->src[2] = nir_src_for_ssa(src2);
   9752    intrin->src[3] = nir_src_for_ssa(src3);
   9753    intrin->src[4] = nir_src_for_ssa(src4);
   9754    intrin->src[5] = nir_src_for_ssa(src5);
   9755    intrin->src[6] = nir_src_for_ssa(src6);
   9756    intrin->src[7] = nir_src_for_ssa(src7);
   9757    intrin->src[8] = nir_src_for_ssa(src8);
   9758    intrin->src[9] = nir_src_for_ssa(src9);
   9759    intrin->src[10] = nir_src_for_ssa(src10);
   9760    nir_intrinsic_set_call_idx(intrin, indices.call_idx);
   9761    nir_intrinsic_set_stack_size(intrin, indices.stack_size);
   9762 
   9763    nir_builder_instr_insert(build, &intrin->instr);
   9764    return intrin;
   9765 }
   9766 static inline nir_intrinsic_instr *
   9767 _nir_build_scoped_barrier(nir_builder *build, struct _nir_scoped_barrier_indices indices)
   9768 {
   9769    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9770       build->shader, nir_intrinsic_scoped_barrier);
   9771 
   9772    nir_intrinsic_set_execution_scope(intrin, indices.execution_scope);
   9773    nir_intrinsic_set_memory_scope(intrin, indices.memory_scope);
   9774    nir_intrinsic_set_memory_semantics(intrin, indices.memory_semantics);
   9775    nir_intrinsic_set_memory_modes(intrin, indices.memory_modes);
   9776 
   9777    nir_builder_instr_insert(build, &intrin->instr);
   9778    return intrin;
   9779 }
   9780 static inline nir_intrinsic_instr *
   9781 _nir_build_set_vertex_and_primitive_count(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_set_vertex_and_primitive_count_indices indices)
   9782 {
   9783    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9784       build->shader, nir_intrinsic_set_vertex_and_primitive_count);
   9785 
   9786    intrin->src[0] = nir_src_for_ssa(src0);
   9787    intrin->src[1] = nir_src_for_ssa(src1);
   9788    nir_intrinsic_set_stream_id(intrin, indices.stream_id);
   9789 
   9790    nir_builder_instr_insert(build, &intrin->instr);
   9791    return intrin;
   9792 }
   9793 static inline nir_ssa_def *
   9794 _nir_build_shader_clock(nir_builder *build, struct _nir_shader_clock_indices indices)
   9795 {
   9796    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9797       build->shader, nir_intrinsic_shader_clock);
   9798 
   9799       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
   9800    nir_intrinsic_set_memory_scope(intrin, indices.memory_scope);
   9801 
   9802    nir_builder_instr_insert(build, &intrin->instr);
   9803    return &intrin->dest.ssa;
   9804 }
   9805 static inline nir_ssa_def *
   9806 _nir_build_shared_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_add_indices indices)
   9807 {
   9808    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9809       build->shader, nir_intrinsic_shared_atomic_add);
   9810 
   9811       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9812    intrin->src[0] = nir_src_for_ssa(src0);
   9813    intrin->src[1] = nir_src_for_ssa(src1);
   9814    nir_intrinsic_set_base(intrin, indices.base);
   9815 
   9816    nir_builder_instr_insert(build, &intrin->instr);
   9817    return &intrin->dest.ssa;
   9818 }
   9819 static inline nir_ssa_def *
   9820 _nir_build_shared_atomic_add_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9821 {
   9822    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9823       build->shader, nir_intrinsic_shared_atomic_add_dxil);
   9824 
   9825       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9826    intrin->src[0] = nir_src_for_ssa(src0);
   9827    intrin->src[1] = nir_src_for_ssa(src1);
   9828 
   9829    nir_builder_instr_insert(build, &intrin->instr);
   9830    return &intrin->dest.ssa;
   9831 }
   9832 static inline nir_ssa_def *
   9833 _nir_build_shared_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_and_indices indices)
   9834 {
   9835    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9836       build->shader, nir_intrinsic_shared_atomic_and);
   9837 
   9838       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9839    intrin->src[0] = nir_src_for_ssa(src0);
   9840    intrin->src[1] = nir_src_for_ssa(src1);
   9841    nir_intrinsic_set_base(intrin, indices.base);
   9842 
   9843    nir_builder_instr_insert(build, &intrin->instr);
   9844    return &intrin->dest.ssa;
   9845 }
   9846 static inline nir_ssa_def *
   9847 _nir_build_shared_atomic_and_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9848 {
   9849    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9850       build->shader, nir_intrinsic_shared_atomic_and_dxil);
   9851 
   9852       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9853    intrin->src[0] = nir_src_for_ssa(src0);
   9854    intrin->src[1] = nir_src_for_ssa(src1);
   9855 
   9856    nir_builder_instr_insert(build, &intrin->instr);
   9857    return &intrin->dest.ssa;
   9858 }
   9859 static inline nir_ssa_def *
   9860 _nir_build_shared_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_shared_atomic_comp_swap_indices indices)
   9861 {
   9862    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9863       build->shader, nir_intrinsic_shared_atomic_comp_swap);
   9864 
   9865       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9866    intrin->src[0] = nir_src_for_ssa(src0);
   9867    intrin->src[1] = nir_src_for_ssa(src1);
   9868    intrin->src[2] = nir_src_for_ssa(src2);
   9869    nir_intrinsic_set_base(intrin, indices.base);
   9870 
   9871    nir_builder_instr_insert(build, &intrin->instr);
   9872    return &intrin->dest.ssa;
   9873 }
   9874 static inline nir_ssa_def *
   9875 _nir_build_shared_atomic_comp_swap_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   9876 {
   9877    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9878       build->shader, nir_intrinsic_shared_atomic_comp_swap_dxil);
   9879 
   9880       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9881    intrin->src[0] = nir_src_for_ssa(src0);
   9882    intrin->src[1] = nir_src_for_ssa(src1);
   9883    intrin->src[2] = nir_src_for_ssa(src2);
   9884 
   9885    nir_builder_instr_insert(build, &intrin->instr);
   9886    return &intrin->dest.ssa;
   9887 }
   9888 static inline nir_ssa_def *
   9889 _nir_build_shared_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_exchange_indices indices)
   9890 {
   9891    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9892       build->shader, nir_intrinsic_shared_atomic_exchange);
   9893 
   9894       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9895    intrin->src[0] = nir_src_for_ssa(src0);
   9896    intrin->src[1] = nir_src_for_ssa(src1);
   9897    nir_intrinsic_set_base(intrin, indices.base);
   9898 
   9899    nir_builder_instr_insert(build, &intrin->instr);
   9900    return &intrin->dest.ssa;
   9901 }
   9902 static inline nir_ssa_def *
   9903 _nir_build_shared_atomic_exchange_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9904 {
   9905    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9906       build->shader, nir_intrinsic_shared_atomic_exchange_dxil);
   9907 
   9908       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9909    intrin->src[0] = nir_src_for_ssa(src0);
   9910    intrin->src[1] = nir_src_for_ssa(src1);
   9911 
   9912    nir_builder_instr_insert(build, &intrin->instr);
   9913    return &intrin->dest.ssa;
   9914 }
   9915 static inline nir_ssa_def *
   9916 _nir_build_shared_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_fadd_indices indices)
   9917 {
   9918    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9919       build->shader, nir_intrinsic_shared_atomic_fadd);
   9920 
   9921       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9922    intrin->src[0] = nir_src_for_ssa(src0);
   9923    intrin->src[1] = nir_src_for_ssa(src1);
   9924    nir_intrinsic_set_base(intrin, indices.base);
   9925 
   9926    nir_builder_instr_insert(build, &intrin->instr);
   9927    return &intrin->dest.ssa;
   9928 }
   9929 static inline nir_ssa_def *
   9930 _nir_build_shared_atomic_fcomp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_shared_atomic_fcomp_swap_indices indices)
   9931 {
   9932    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9933       build->shader, nir_intrinsic_shared_atomic_fcomp_swap);
   9934 
   9935       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9936    intrin->src[0] = nir_src_for_ssa(src0);
   9937    intrin->src[1] = nir_src_for_ssa(src1);
   9938    intrin->src[2] = nir_src_for_ssa(src2);
   9939    nir_intrinsic_set_base(intrin, indices.base);
   9940 
   9941    nir_builder_instr_insert(build, &intrin->instr);
   9942    return &intrin->dest.ssa;
   9943 }
   9944 static inline nir_ssa_def *
   9945 _nir_build_shared_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_fmax_indices indices)
   9946 {
   9947    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9948       build->shader, nir_intrinsic_shared_atomic_fmax);
   9949 
   9950       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9951    intrin->src[0] = nir_src_for_ssa(src0);
   9952    intrin->src[1] = nir_src_for_ssa(src1);
   9953    nir_intrinsic_set_base(intrin, indices.base);
   9954 
   9955    nir_builder_instr_insert(build, &intrin->instr);
   9956    return &intrin->dest.ssa;
   9957 }
   9958 static inline nir_ssa_def *
   9959 _nir_build_shared_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_fmin_indices indices)
   9960 {
   9961    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9962       build->shader, nir_intrinsic_shared_atomic_fmin);
   9963 
   9964       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9965    intrin->src[0] = nir_src_for_ssa(src0);
   9966    intrin->src[1] = nir_src_for_ssa(src1);
   9967    nir_intrinsic_set_base(intrin, indices.base);
   9968 
   9969    nir_builder_instr_insert(build, &intrin->instr);
   9970    return &intrin->dest.ssa;
   9971 }
   9972 static inline nir_ssa_def *
   9973 _nir_build_shared_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_imax_indices indices)
   9974 {
   9975    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9976       build->shader, nir_intrinsic_shared_atomic_imax);
   9977 
   9978       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9979    intrin->src[0] = nir_src_for_ssa(src0);
   9980    intrin->src[1] = nir_src_for_ssa(src1);
   9981    nir_intrinsic_set_base(intrin, indices.base);
   9982 
   9983    nir_builder_instr_insert(build, &intrin->instr);
   9984    return &intrin->dest.ssa;
   9985 }
   9986 static inline nir_ssa_def *
   9987 _nir_build_shared_atomic_imax_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   9988 {
   9989    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   9990       build->shader, nir_intrinsic_shared_atomic_imax_dxil);
   9991 
   9992       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   9993    intrin->src[0] = nir_src_for_ssa(src0);
   9994    intrin->src[1] = nir_src_for_ssa(src1);
   9995 
   9996    nir_builder_instr_insert(build, &intrin->instr);
   9997    return &intrin->dest.ssa;
   9998 }
   9999 static inline nir_ssa_def *
   10000 _nir_build_shared_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_imin_indices indices)
   10001 {
   10002    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10003       build->shader, nir_intrinsic_shared_atomic_imin);
   10004 
   10005       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10006    intrin->src[0] = nir_src_for_ssa(src0);
   10007    intrin->src[1] = nir_src_for_ssa(src1);
   10008    nir_intrinsic_set_base(intrin, indices.base);
   10009 
   10010    nir_builder_instr_insert(build, &intrin->instr);
   10011    return &intrin->dest.ssa;
   10012 }
   10013 static inline nir_ssa_def *
   10014 _nir_build_shared_atomic_imin_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   10015 {
   10016    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10017       build->shader, nir_intrinsic_shared_atomic_imin_dxil);
   10018 
   10019       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10020    intrin->src[0] = nir_src_for_ssa(src0);
   10021    intrin->src[1] = nir_src_for_ssa(src1);
   10022 
   10023    nir_builder_instr_insert(build, &intrin->instr);
   10024    return &intrin->dest.ssa;
   10025 }
   10026 static inline nir_ssa_def *
   10027 _nir_build_shared_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_or_indices indices)
   10028 {
   10029    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10030       build->shader, nir_intrinsic_shared_atomic_or);
   10031 
   10032       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10033    intrin->src[0] = nir_src_for_ssa(src0);
   10034    intrin->src[1] = nir_src_for_ssa(src1);
   10035    nir_intrinsic_set_base(intrin, indices.base);
   10036 
   10037    nir_builder_instr_insert(build, &intrin->instr);
   10038    return &intrin->dest.ssa;
   10039 }
   10040 static inline nir_ssa_def *
   10041 _nir_build_shared_atomic_or_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   10042 {
   10043    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10044       build->shader, nir_intrinsic_shared_atomic_or_dxil);
   10045 
   10046       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10047    intrin->src[0] = nir_src_for_ssa(src0);
   10048    intrin->src[1] = nir_src_for_ssa(src1);
   10049 
   10050    nir_builder_instr_insert(build, &intrin->instr);
   10051    return &intrin->dest.ssa;
   10052 }
   10053 static inline nir_ssa_def *
   10054 _nir_build_shared_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_umax_indices indices)
   10055 {
   10056    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10057       build->shader, nir_intrinsic_shared_atomic_umax);
   10058 
   10059       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10060    intrin->src[0] = nir_src_for_ssa(src0);
   10061    intrin->src[1] = nir_src_for_ssa(src1);
   10062    nir_intrinsic_set_base(intrin, indices.base);
   10063 
   10064    nir_builder_instr_insert(build, &intrin->instr);
   10065    return &intrin->dest.ssa;
   10066 }
   10067 static inline nir_ssa_def *
   10068 _nir_build_shared_atomic_umax_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   10069 {
   10070    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10071       build->shader, nir_intrinsic_shared_atomic_umax_dxil);
   10072 
   10073       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10074    intrin->src[0] = nir_src_for_ssa(src0);
   10075    intrin->src[1] = nir_src_for_ssa(src1);
   10076 
   10077    nir_builder_instr_insert(build, &intrin->instr);
   10078    return &intrin->dest.ssa;
   10079 }
   10080 static inline nir_ssa_def *
   10081 _nir_build_shared_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_umin_indices indices)
   10082 {
   10083    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10084       build->shader, nir_intrinsic_shared_atomic_umin);
   10085 
   10086       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10087    intrin->src[0] = nir_src_for_ssa(src0);
   10088    intrin->src[1] = nir_src_for_ssa(src1);
   10089    nir_intrinsic_set_base(intrin, indices.base);
   10090 
   10091    nir_builder_instr_insert(build, &intrin->instr);
   10092    return &intrin->dest.ssa;
   10093 }
   10094 static inline nir_ssa_def *
   10095 _nir_build_shared_atomic_umin_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   10096 {
   10097    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10098       build->shader, nir_intrinsic_shared_atomic_umin_dxil);
   10099 
   10100       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10101    intrin->src[0] = nir_src_for_ssa(src0);
   10102    intrin->src[1] = nir_src_for_ssa(src1);
   10103 
   10104    nir_builder_instr_insert(build, &intrin->instr);
   10105    return &intrin->dest.ssa;
   10106 }
   10107 static inline nir_ssa_def *
   10108 _nir_build_shared_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_shared_atomic_xor_indices indices)
   10109 {
   10110    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10111       build->shader, nir_intrinsic_shared_atomic_xor);
   10112 
   10113       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10114    intrin->src[0] = nir_src_for_ssa(src0);
   10115    intrin->src[1] = nir_src_for_ssa(src1);
   10116    nir_intrinsic_set_base(intrin, indices.base);
   10117 
   10118    nir_builder_instr_insert(build, &intrin->instr);
   10119    return &intrin->dest.ssa;
   10120 }
   10121 static inline nir_ssa_def *
   10122 _nir_build_shared_atomic_xor_dxil(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1)
   10123 {
   10124    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10125       build->shader, nir_intrinsic_shared_atomic_xor_dxil);
   10126 
   10127       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10128    intrin->src[0] = nir_src_for_ssa(src0);
   10129    intrin->src[1] = nir_src_for_ssa(src1);
   10130 
   10131    nir_builder_instr_insert(build, &intrin->instr);
   10132    return &intrin->dest.ssa;
   10133 }
   10134 static inline nir_ssa_def *
   10135 _nir_build_shuffle(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10136 {
   10137    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10138       build->shader, nir_intrinsic_shuffle);
   10139 
   10140    intrin->num_components = src0->num_components;
   10141       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   10142    intrin->src[0] = nir_src_for_ssa(src0);
   10143    intrin->src[1] = nir_src_for_ssa(src1);
   10144 
   10145    nir_builder_instr_insert(build, &intrin->instr);
   10146    return &intrin->dest.ssa;
   10147 }
   10148 static inline nir_ssa_def *
   10149 _nir_build_shuffle_down(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10150 {
   10151    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10152       build->shader, nir_intrinsic_shuffle_down);
   10153 
   10154    intrin->num_components = src0->num_components;
   10155       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   10156    intrin->src[0] = nir_src_for_ssa(src0);
   10157    intrin->src[1] = nir_src_for_ssa(src1);
   10158 
   10159    nir_builder_instr_insert(build, &intrin->instr);
   10160    return &intrin->dest.ssa;
   10161 }
   10162 static inline nir_ssa_def *
   10163 _nir_build_shuffle_up(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10164 {
   10165    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10166       build->shader, nir_intrinsic_shuffle_up);
   10167 
   10168    intrin->num_components = src0->num_components;
   10169       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   10170    intrin->src[0] = nir_src_for_ssa(src0);
   10171    intrin->src[1] = nir_src_for_ssa(src1);
   10172 
   10173    nir_builder_instr_insert(build, &intrin->instr);
   10174    return &intrin->dest.ssa;
   10175 }
   10176 static inline nir_ssa_def *
   10177 _nir_build_shuffle_xor(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10178 {
   10179    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10180       build->shader, nir_intrinsic_shuffle_xor);
   10181 
   10182    intrin->num_components = src0->num_components;
   10183       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   10184    intrin->src[0] = nir_src_for_ssa(src0);
   10185    intrin->src[1] = nir_src_for_ssa(src1);
   10186 
   10187    nir_builder_instr_insert(build, &intrin->instr);
   10188    return &intrin->dest.ssa;
   10189 }
   10190 static inline nir_ssa_def *
   10191 _nir_build_sparse_residency_code_and(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10192 {
   10193    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10194       build->shader, nir_intrinsic_sparse_residency_code_and);
   10195 
   10196       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 32, NULL);
   10197    intrin->src[0] = nir_src_for_ssa(src0);
   10198    intrin->src[1] = nir_src_for_ssa(src1);
   10199 
   10200    nir_builder_instr_insert(build, &intrin->instr);
   10201    return &intrin->dest.ssa;
   10202 }
   10203 static inline nir_ssa_def *
   10204 _nir_build_ssbo_atomic_add(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_add_indices indices)
   10205 {
   10206    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10207       build->shader, nir_intrinsic_ssbo_atomic_add);
   10208 
   10209       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10210    intrin->src[0] = nir_src_for_ssa(src0);
   10211    intrin->src[1] = nir_src_for_ssa(src1);
   10212    intrin->src[2] = nir_src_for_ssa(src2);
   10213    nir_intrinsic_set_access(intrin, indices.access);
   10214 
   10215    nir_builder_instr_insert(build, &intrin->instr);
   10216    return &intrin->dest.ssa;
   10217 }
   10218 static inline nir_ssa_def *
   10219 _nir_build_ssbo_atomic_add_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_add_ir3_indices indices)
   10220 {
   10221    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10222       build->shader, nir_intrinsic_ssbo_atomic_add_ir3);
   10223 
   10224       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10225    intrin->src[0] = nir_src_for_ssa(src0);
   10226    intrin->src[1] = nir_src_for_ssa(src1);
   10227    intrin->src[2] = nir_src_for_ssa(src2);
   10228    intrin->src[3] = nir_src_for_ssa(src3);
   10229    nir_intrinsic_set_access(intrin, indices.access);
   10230 
   10231    nir_builder_instr_insert(build, &intrin->instr);
   10232    return &intrin->dest.ssa;
   10233 }
   10234 static inline nir_ssa_def *
   10235 _nir_build_ssbo_atomic_and(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_and_indices indices)
   10236 {
   10237    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10238       build->shader, nir_intrinsic_ssbo_atomic_and);
   10239 
   10240       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10241    intrin->src[0] = nir_src_for_ssa(src0);
   10242    intrin->src[1] = nir_src_for_ssa(src1);
   10243    intrin->src[2] = nir_src_for_ssa(src2);
   10244    nir_intrinsic_set_access(intrin, indices.access);
   10245 
   10246    nir_builder_instr_insert(build, &intrin->instr);
   10247    return &intrin->dest.ssa;
   10248 }
   10249 static inline nir_ssa_def *
   10250 _nir_build_ssbo_atomic_and_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_and_ir3_indices indices)
   10251 {
   10252    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10253       build->shader, nir_intrinsic_ssbo_atomic_and_ir3);
   10254 
   10255       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10256    intrin->src[0] = nir_src_for_ssa(src0);
   10257    intrin->src[1] = nir_src_for_ssa(src1);
   10258    intrin->src[2] = nir_src_for_ssa(src2);
   10259    intrin->src[3] = nir_src_for_ssa(src3);
   10260    nir_intrinsic_set_access(intrin, indices.access);
   10261 
   10262    nir_builder_instr_insert(build, &intrin->instr);
   10263    return &intrin->dest.ssa;
   10264 }
   10265 static inline nir_ssa_def *
   10266 _nir_build_ssbo_atomic_comp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_comp_swap_indices indices)
   10267 {
   10268    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10269       build->shader, nir_intrinsic_ssbo_atomic_comp_swap);
   10270 
   10271       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10272    intrin->src[0] = nir_src_for_ssa(src0);
   10273    intrin->src[1] = nir_src_for_ssa(src1);
   10274    intrin->src[2] = nir_src_for_ssa(src2);
   10275    intrin->src[3] = nir_src_for_ssa(src3);
   10276    nir_intrinsic_set_access(intrin, indices.access);
   10277 
   10278    nir_builder_instr_insert(build, &intrin->instr);
   10279    return &intrin->dest.ssa;
   10280 }
   10281 static inline nir_ssa_def *
   10282 _nir_build_ssbo_atomic_comp_swap_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, struct _nir_ssbo_atomic_comp_swap_ir3_indices indices)
   10283 {
   10284    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10285       build->shader, nir_intrinsic_ssbo_atomic_comp_swap_ir3);
   10286 
   10287       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10288    intrin->src[0] = nir_src_for_ssa(src0);
   10289    intrin->src[1] = nir_src_for_ssa(src1);
   10290    intrin->src[2] = nir_src_for_ssa(src2);
   10291    intrin->src[3] = nir_src_for_ssa(src3);
   10292    intrin->src[4] = nir_src_for_ssa(src4);
   10293    nir_intrinsic_set_access(intrin, indices.access);
   10294 
   10295    nir_builder_instr_insert(build, &intrin->instr);
   10296    return &intrin->dest.ssa;
   10297 }
   10298 static inline nir_ssa_def *
   10299 _nir_build_ssbo_atomic_exchange(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_exchange_indices indices)
   10300 {
   10301    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10302       build->shader, nir_intrinsic_ssbo_atomic_exchange);
   10303 
   10304       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10305    intrin->src[0] = nir_src_for_ssa(src0);
   10306    intrin->src[1] = nir_src_for_ssa(src1);
   10307    intrin->src[2] = nir_src_for_ssa(src2);
   10308    nir_intrinsic_set_access(intrin, indices.access);
   10309 
   10310    nir_builder_instr_insert(build, &intrin->instr);
   10311    return &intrin->dest.ssa;
   10312 }
   10313 static inline nir_ssa_def *
   10314 _nir_build_ssbo_atomic_exchange_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_exchange_ir3_indices indices)
   10315 {
   10316    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10317       build->shader, nir_intrinsic_ssbo_atomic_exchange_ir3);
   10318 
   10319       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10320    intrin->src[0] = nir_src_for_ssa(src0);
   10321    intrin->src[1] = nir_src_for_ssa(src1);
   10322    intrin->src[2] = nir_src_for_ssa(src2);
   10323    intrin->src[3] = nir_src_for_ssa(src3);
   10324    nir_intrinsic_set_access(intrin, indices.access);
   10325 
   10326    nir_builder_instr_insert(build, &intrin->instr);
   10327    return &intrin->dest.ssa;
   10328 }
   10329 static inline nir_ssa_def *
   10330 _nir_build_ssbo_atomic_fadd(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_fadd_indices indices)
   10331 {
   10332    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10333       build->shader, nir_intrinsic_ssbo_atomic_fadd);
   10334 
   10335       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10336    intrin->src[0] = nir_src_for_ssa(src0);
   10337    intrin->src[1] = nir_src_for_ssa(src1);
   10338    intrin->src[2] = nir_src_for_ssa(src2);
   10339    nir_intrinsic_set_access(intrin, indices.access);
   10340 
   10341    nir_builder_instr_insert(build, &intrin->instr);
   10342    return &intrin->dest.ssa;
   10343 }
   10344 static inline nir_ssa_def *
   10345 _nir_build_ssbo_atomic_fcomp_swap(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_fcomp_swap_indices indices)
   10346 {
   10347    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10348       build->shader, nir_intrinsic_ssbo_atomic_fcomp_swap);
   10349 
   10350       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10351    intrin->src[0] = nir_src_for_ssa(src0);
   10352    intrin->src[1] = nir_src_for_ssa(src1);
   10353    intrin->src[2] = nir_src_for_ssa(src2);
   10354    intrin->src[3] = nir_src_for_ssa(src3);
   10355    nir_intrinsic_set_access(intrin, indices.access);
   10356 
   10357    nir_builder_instr_insert(build, &intrin->instr);
   10358    return &intrin->dest.ssa;
   10359 }
   10360 static inline nir_ssa_def *
   10361 _nir_build_ssbo_atomic_fmax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_fmax_indices indices)
   10362 {
   10363    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10364       build->shader, nir_intrinsic_ssbo_atomic_fmax);
   10365 
   10366       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10367    intrin->src[0] = nir_src_for_ssa(src0);
   10368    intrin->src[1] = nir_src_for_ssa(src1);
   10369    intrin->src[2] = nir_src_for_ssa(src2);
   10370    nir_intrinsic_set_access(intrin, indices.access);
   10371 
   10372    nir_builder_instr_insert(build, &intrin->instr);
   10373    return &intrin->dest.ssa;
   10374 }
   10375 static inline nir_ssa_def *
   10376 _nir_build_ssbo_atomic_fmin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_fmin_indices indices)
   10377 {
   10378    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10379       build->shader, nir_intrinsic_ssbo_atomic_fmin);
   10380 
   10381       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10382    intrin->src[0] = nir_src_for_ssa(src0);
   10383    intrin->src[1] = nir_src_for_ssa(src1);
   10384    intrin->src[2] = nir_src_for_ssa(src2);
   10385    nir_intrinsic_set_access(intrin, indices.access);
   10386 
   10387    nir_builder_instr_insert(build, &intrin->instr);
   10388    return &intrin->dest.ssa;
   10389 }
   10390 static inline nir_ssa_def *
   10391 _nir_build_ssbo_atomic_imax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_imax_indices indices)
   10392 {
   10393    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10394       build->shader, nir_intrinsic_ssbo_atomic_imax);
   10395 
   10396       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10397    intrin->src[0] = nir_src_for_ssa(src0);
   10398    intrin->src[1] = nir_src_for_ssa(src1);
   10399    intrin->src[2] = nir_src_for_ssa(src2);
   10400    nir_intrinsic_set_access(intrin, indices.access);
   10401 
   10402    nir_builder_instr_insert(build, &intrin->instr);
   10403    return &intrin->dest.ssa;
   10404 }
   10405 static inline nir_ssa_def *
   10406 _nir_build_ssbo_atomic_imax_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_imax_ir3_indices indices)
   10407 {
   10408    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10409       build->shader, nir_intrinsic_ssbo_atomic_imax_ir3);
   10410 
   10411       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10412    intrin->src[0] = nir_src_for_ssa(src0);
   10413    intrin->src[1] = nir_src_for_ssa(src1);
   10414    intrin->src[2] = nir_src_for_ssa(src2);
   10415    intrin->src[3] = nir_src_for_ssa(src3);
   10416    nir_intrinsic_set_access(intrin, indices.access);
   10417 
   10418    nir_builder_instr_insert(build, &intrin->instr);
   10419    return &intrin->dest.ssa;
   10420 }
   10421 static inline nir_ssa_def *
   10422 _nir_build_ssbo_atomic_imin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_imin_indices indices)
   10423 {
   10424    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10425       build->shader, nir_intrinsic_ssbo_atomic_imin);
   10426 
   10427       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10428    intrin->src[0] = nir_src_for_ssa(src0);
   10429    intrin->src[1] = nir_src_for_ssa(src1);
   10430    intrin->src[2] = nir_src_for_ssa(src2);
   10431    nir_intrinsic_set_access(intrin, indices.access);
   10432 
   10433    nir_builder_instr_insert(build, &intrin->instr);
   10434    return &intrin->dest.ssa;
   10435 }
   10436 static inline nir_ssa_def *
   10437 _nir_build_ssbo_atomic_imin_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_imin_ir3_indices indices)
   10438 {
   10439    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10440       build->shader, nir_intrinsic_ssbo_atomic_imin_ir3);
   10441 
   10442       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10443    intrin->src[0] = nir_src_for_ssa(src0);
   10444    intrin->src[1] = nir_src_for_ssa(src1);
   10445    intrin->src[2] = nir_src_for_ssa(src2);
   10446    intrin->src[3] = nir_src_for_ssa(src3);
   10447    nir_intrinsic_set_access(intrin, indices.access);
   10448 
   10449    nir_builder_instr_insert(build, &intrin->instr);
   10450    return &intrin->dest.ssa;
   10451 }
   10452 static inline nir_ssa_def *
   10453 _nir_build_ssbo_atomic_or(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_or_indices indices)
   10454 {
   10455    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10456       build->shader, nir_intrinsic_ssbo_atomic_or);
   10457 
   10458       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10459    intrin->src[0] = nir_src_for_ssa(src0);
   10460    intrin->src[1] = nir_src_for_ssa(src1);
   10461    intrin->src[2] = nir_src_for_ssa(src2);
   10462    nir_intrinsic_set_access(intrin, indices.access);
   10463 
   10464    nir_builder_instr_insert(build, &intrin->instr);
   10465    return &intrin->dest.ssa;
   10466 }
   10467 static inline nir_ssa_def *
   10468 _nir_build_ssbo_atomic_or_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_or_ir3_indices indices)
   10469 {
   10470    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10471       build->shader, nir_intrinsic_ssbo_atomic_or_ir3);
   10472 
   10473       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10474    intrin->src[0] = nir_src_for_ssa(src0);
   10475    intrin->src[1] = nir_src_for_ssa(src1);
   10476    intrin->src[2] = nir_src_for_ssa(src2);
   10477    intrin->src[3] = nir_src_for_ssa(src3);
   10478    nir_intrinsic_set_access(intrin, indices.access);
   10479 
   10480    nir_builder_instr_insert(build, &intrin->instr);
   10481    return &intrin->dest.ssa;
   10482 }
   10483 static inline nir_ssa_def *
   10484 _nir_build_ssbo_atomic_umax(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_umax_indices indices)
   10485 {
   10486    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10487       build->shader, nir_intrinsic_ssbo_atomic_umax);
   10488 
   10489       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10490    intrin->src[0] = nir_src_for_ssa(src0);
   10491    intrin->src[1] = nir_src_for_ssa(src1);
   10492    intrin->src[2] = nir_src_for_ssa(src2);
   10493    nir_intrinsic_set_access(intrin, indices.access);
   10494 
   10495    nir_builder_instr_insert(build, &intrin->instr);
   10496    return &intrin->dest.ssa;
   10497 }
   10498 static inline nir_ssa_def *
   10499 _nir_build_ssbo_atomic_umax_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_umax_ir3_indices indices)
   10500 {
   10501    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10502       build->shader, nir_intrinsic_ssbo_atomic_umax_ir3);
   10503 
   10504       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10505    intrin->src[0] = nir_src_for_ssa(src0);
   10506    intrin->src[1] = nir_src_for_ssa(src1);
   10507    intrin->src[2] = nir_src_for_ssa(src2);
   10508    intrin->src[3] = nir_src_for_ssa(src3);
   10509    nir_intrinsic_set_access(intrin, indices.access);
   10510 
   10511    nir_builder_instr_insert(build, &intrin->instr);
   10512    return &intrin->dest.ssa;
   10513 }
   10514 static inline nir_ssa_def *
   10515 _nir_build_ssbo_atomic_umin(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_umin_indices indices)
   10516 {
   10517    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10518       build->shader, nir_intrinsic_ssbo_atomic_umin);
   10519 
   10520       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10521    intrin->src[0] = nir_src_for_ssa(src0);
   10522    intrin->src[1] = nir_src_for_ssa(src1);
   10523    intrin->src[2] = nir_src_for_ssa(src2);
   10524    nir_intrinsic_set_access(intrin, indices.access);
   10525 
   10526    nir_builder_instr_insert(build, &intrin->instr);
   10527    return &intrin->dest.ssa;
   10528 }
   10529 static inline nir_ssa_def *
   10530 _nir_build_ssbo_atomic_umin_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_umin_ir3_indices indices)
   10531 {
   10532    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10533       build->shader, nir_intrinsic_ssbo_atomic_umin_ir3);
   10534 
   10535       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10536    intrin->src[0] = nir_src_for_ssa(src0);
   10537    intrin->src[1] = nir_src_for_ssa(src1);
   10538    intrin->src[2] = nir_src_for_ssa(src2);
   10539    intrin->src[3] = nir_src_for_ssa(src3);
   10540    nir_intrinsic_set_access(intrin, indices.access);
   10541 
   10542    nir_builder_instr_insert(build, &intrin->instr);
   10543    return &intrin->dest.ssa;
   10544 }
   10545 static inline nir_ssa_def *
   10546 _nir_build_ssbo_atomic_xor(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_ssbo_atomic_xor_indices indices)
   10547 {
   10548    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10549       build->shader, nir_intrinsic_ssbo_atomic_xor);
   10550 
   10551       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10552    intrin->src[0] = nir_src_for_ssa(src0);
   10553    intrin->src[1] = nir_src_for_ssa(src1);
   10554    intrin->src[2] = nir_src_for_ssa(src2);
   10555    nir_intrinsic_set_access(intrin, indices.access);
   10556 
   10557    nir_builder_instr_insert(build, &intrin->instr);
   10558    return &intrin->dest.ssa;
   10559 }
   10560 static inline nir_ssa_def *
   10561 _nir_build_ssbo_atomic_xor_ir3(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_ssbo_atomic_xor_ir3_indices indices)
   10562 {
   10563    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10564       build->shader, nir_intrinsic_ssbo_atomic_xor_ir3);
   10565 
   10566       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   10567    intrin->src[0] = nir_src_for_ssa(src0);
   10568    intrin->src[1] = nir_src_for_ssa(src1);
   10569    intrin->src[2] = nir_src_for_ssa(src2);
   10570    intrin->src[3] = nir_src_for_ssa(src3);
   10571    nir_intrinsic_set_access(intrin, indices.access);
   10572 
   10573    nir_builder_instr_insert(build, &intrin->instr);
   10574    return &intrin->dest.ssa;
   10575 }
   10576 static inline nir_intrinsic_instr *
   10577 _nir_build_store_buffer_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_store_buffer_amd_indices indices)
   10578 {
   10579    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10580       build->shader, nir_intrinsic_store_buffer_amd);
   10581 
   10582    intrin->num_components = src0->num_components;
   10583    intrin->src[0] = nir_src_for_ssa(src0);
   10584    intrin->src[1] = nir_src_for_ssa(src1);
   10585    intrin->src[2] = nir_src_for_ssa(src2);
   10586    intrin->src[3] = nir_src_for_ssa(src3);
   10587    nir_intrinsic_set_base(intrin, indices.base);
   10588    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10589    nir_intrinsic_set_is_swizzled(intrin, indices.is_swizzled);
   10590    nir_intrinsic_set_slc_amd(intrin, indices.slc_amd);
   10591    nir_intrinsic_set_memory_modes(intrin, indices.memory_modes);
   10592 
   10593    nir_builder_instr_insert(build, &intrin->instr);
   10594    return intrin;
   10595 }
   10596 static inline nir_intrinsic_instr *
   10597 _nir_build_store_combined_output_pan(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_store_combined_output_pan_indices indices)
   10598 {
   10599    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10600       build->shader, nir_intrinsic_store_combined_output_pan);
   10601 
   10602    intrin->num_components = src0->num_components;
   10603    intrin->src[0] = nir_src_for_ssa(src0);
   10604    intrin->src[1] = nir_src_for_ssa(src1);
   10605    intrin->src[2] = nir_src_for_ssa(src2);
   10606    intrin->src[3] = nir_src_for_ssa(src3);
   10607    nir_intrinsic_set_base(intrin, indices.base);
   10608    nir_intrinsic_set_component(intrin, indices.component);
   10609    nir_intrinsic_set_src_type(intrin, indices.src_type);
   10610 
   10611    nir_builder_instr_insert(build, &intrin->instr);
   10612    return intrin;
   10613 }
   10614 static inline nir_intrinsic_instr *
   10615 _nir_build_store_deref(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_deref_indices indices)
   10616 {
   10617    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10618       build->shader, nir_intrinsic_store_deref);
   10619 
   10620    intrin->num_components = src1->num_components;
   10621    intrin->src[0] = nir_src_for_ssa(src0);
   10622    intrin->src[1] = nir_src_for_ssa(src1);
   10623    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10624    nir_intrinsic_set_access(intrin, indices.access);
   10625 
   10626    nir_builder_instr_insert(build, &intrin->instr);
   10627    return intrin;
   10628 }
   10629 static inline nir_intrinsic_instr *
   10630 _nir_build_store_deref_block_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_deref_block_intel_indices indices)
   10631 {
   10632    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10633       build->shader, nir_intrinsic_store_deref_block_intel);
   10634 
   10635    intrin->num_components = src1->num_components;
   10636    intrin->src[0] = nir_src_for_ssa(src0);
   10637    intrin->src[1] = nir_src_for_ssa(src1);
   10638    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10639    nir_intrinsic_set_access(intrin, indices.access);
   10640 
   10641    nir_builder_instr_insert(build, &intrin->instr);
   10642    return intrin;
   10643 }
   10644 static inline nir_intrinsic_instr *
   10645 _nir_build_store_global(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_global_indices indices)
   10646 {
   10647    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10648       build->shader, nir_intrinsic_store_global);
   10649 
   10650    intrin->num_components = src0->num_components;
   10651    intrin->src[0] = nir_src_for_ssa(src0);
   10652    intrin->src[1] = nir_src_for_ssa(src1);
   10653    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10654    nir_intrinsic_set_access(intrin, indices.access);
   10655    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10656    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10657 
   10658    nir_builder_instr_insert(build, &intrin->instr);
   10659    return intrin;
   10660 }
   10661 static inline nir_intrinsic_instr *
   10662 _nir_build_store_global_block_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_global_block_intel_indices indices)
   10663 {
   10664    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10665       build->shader, nir_intrinsic_store_global_block_intel);
   10666 
   10667    intrin->num_components = src0->num_components;
   10668    intrin->src[0] = nir_src_for_ssa(src0);
   10669    intrin->src[1] = nir_src_for_ssa(src1);
   10670    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10671    nir_intrinsic_set_access(intrin, indices.access);
   10672    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10673    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10674 
   10675    nir_builder_instr_insert(build, &intrin->instr);
   10676    return intrin;
   10677 }
   10678 static inline nir_intrinsic_instr *
   10679 _nir_build_store_global_ir3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_store_global_ir3_indices indices)
   10680 {
   10681    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10682       build->shader, nir_intrinsic_store_global_ir3);
   10683 
   10684    intrin->num_components = src0->num_components;
   10685    intrin->src[0] = nir_src_for_ssa(src0);
   10686    intrin->src[1] = nir_src_for_ssa(src1);
   10687    intrin->src[2] = nir_src_for_ssa(src2);
   10688    nir_intrinsic_set_access(intrin, indices.access);
   10689    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10690    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10691 
   10692    nir_builder_instr_insert(build, &intrin->instr);
   10693    return intrin;
   10694 }
   10695 static inline nir_intrinsic_instr *
   10696 _nir_build_store_local_shared_r600(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_local_shared_r600_indices indices)
   10697 {
   10698    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10699       build->shader, nir_intrinsic_store_local_shared_r600);
   10700 
   10701    intrin->num_components = src0->num_components;
   10702    intrin->src[0] = nir_src_for_ssa(src0);
   10703    intrin->src[1] = nir_src_for_ssa(src1);
   10704    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10705 
   10706    nir_builder_instr_insert(build, &intrin->instr);
   10707    return intrin;
   10708 }
   10709 static inline nir_intrinsic_instr *
   10710 _nir_build_store_output(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_output_indices indices)
   10711 {
   10712    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10713       build->shader, nir_intrinsic_store_output);
   10714 
   10715    intrin->num_components = src0->num_components;
   10716    intrin->src[0] = nir_src_for_ssa(src0);
   10717    intrin->src[1] = nir_src_for_ssa(src1);
   10718    nir_intrinsic_set_base(intrin, indices.base);
   10719    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10720    nir_intrinsic_set_component(intrin, indices.component);
   10721    nir_intrinsic_set_src_type(intrin, indices.src_type);
   10722    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   10723 
   10724    nir_builder_instr_insert(build, &intrin->instr);
   10725    return intrin;
   10726 }
   10727 static inline nir_intrinsic_instr *
   10728 _nir_build_store_per_primitive_output(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_store_per_primitive_output_indices indices)
   10729 {
   10730    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10731       build->shader, nir_intrinsic_store_per_primitive_output);
   10732 
   10733    intrin->num_components = src0->num_components;
   10734    intrin->src[0] = nir_src_for_ssa(src0);
   10735    intrin->src[1] = nir_src_for_ssa(src1);
   10736    intrin->src[2] = nir_src_for_ssa(src2);
   10737    nir_intrinsic_set_base(intrin, indices.base);
   10738    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10739    nir_intrinsic_set_component(intrin, indices.component);
   10740    nir_intrinsic_set_src_type(intrin, indices.src_type);
   10741    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   10742 
   10743    nir_builder_instr_insert(build, &intrin->instr);
   10744    return intrin;
   10745 }
   10746 static inline nir_intrinsic_instr *
   10747 _nir_build_store_per_vertex_output(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_store_per_vertex_output_indices indices)
   10748 {
   10749    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10750       build->shader, nir_intrinsic_store_per_vertex_output);
   10751 
   10752    intrin->num_components = src0->num_components;
   10753    intrin->src[0] = nir_src_for_ssa(src0);
   10754    intrin->src[1] = nir_src_for_ssa(src1);
   10755    intrin->src[2] = nir_src_for_ssa(src2);
   10756    nir_intrinsic_set_base(intrin, indices.base);
   10757    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10758    nir_intrinsic_set_component(intrin, indices.component);
   10759    nir_intrinsic_set_src_type(intrin, indices.src_type);
   10760    nir_intrinsic_set_io_semantics(intrin, indices.io_semantics);
   10761 
   10762    nir_builder_instr_insert(build, &intrin->instr);
   10763    return intrin;
   10764 }
   10765 static inline nir_intrinsic_instr *
   10766 _nir_build_store_raw_output_pan(nir_builder *build, nir_ssa_def *src0)
   10767 {
   10768    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10769       build->shader, nir_intrinsic_store_raw_output_pan);
   10770 
   10771    intrin->num_components = src0->num_components;
   10772    intrin->src[0] = nir_src_for_ssa(src0);
   10773 
   10774    nir_builder_instr_insert(build, &intrin->instr);
   10775    return intrin;
   10776 }
   10777 static inline nir_intrinsic_instr *
   10778 _nir_build_store_scratch(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_scratch_indices indices)
   10779 {
   10780    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10781       build->shader, nir_intrinsic_store_scratch);
   10782 
   10783    intrin->num_components = src0->num_components;
   10784    intrin->src[0] = nir_src_for_ssa(src0);
   10785    intrin->src[1] = nir_src_for_ssa(src1);
   10786    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10787    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10788    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10789 
   10790    nir_builder_instr_insert(build, &intrin->instr);
   10791    return intrin;
   10792 }
   10793 static inline nir_intrinsic_instr *
   10794 _nir_build_store_scratch_dxil(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10795 {
   10796    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10797       build->shader, nir_intrinsic_store_scratch_dxil);
   10798 
   10799    intrin->src[0] = nir_src_for_ssa(src0);
   10800    intrin->src[1] = nir_src_for_ssa(src1);
   10801 
   10802    nir_builder_instr_insert(build, &intrin->instr);
   10803    return intrin;
   10804 }
   10805 static inline nir_intrinsic_instr *
   10806 _nir_build_store_shared(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_shared_indices indices)
   10807 {
   10808    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10809       build->shader, nir_intrinsic_store_shared);
   10810 
   10811    intrin->num_components = src0->num_components;
   10812    intrin->src[0] = nir_src_for_ssa(src0);
   10813    intrin->src[1] = nir_src_for_ssa(src1);
   10814    nir_intrinsic_set_base(intrin, indices.base);
   10815    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10816    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10817    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10818 
   10819    nir_builder_instr_insert(build, &intrin->instr);
   10820    return intrin;
   10821 }
   10822 static inline nir_intrinsic_instr *
   10823 _nir_build_store_shared_block_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_shared_block_intel_indices indices)
   10824 {
   10825    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10826       build->shader, nir_intrinsic_store_shared_block_intel);
   10827 
   10828    intrin->num_components = src0->num_components;
   10829    intrin->src[0] = nir_src_for_ssa(src0);
   10830    intrin->src[1] = nir_src_for_ssa(src1);
   10831    nir_intrinsic_set_base(intrin, indices.base);
   10832    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10833    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10834    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10835 
   10836    nir_builder_instr_insert(build, &intrin->instr);
   10837    return intrin;
   10838 }
   10839 static inline nir_intrinsic_instr *
   10840 _nir_build_store_shared_dxil(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
   10841 {
   10842    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10843       build->shader, nir_intrinsic_store_shared_dxil);
   10844 
   10845    intrin->src[0] = nir_src_for_ssa(src0);
   10846    intrin->src[1] = nir_src_for_ssa(src1);
   10847 
   10848    nir_builder_instr_insert(build, &intrin->instr);
   10849    return intrin;
   10850 }
   10851 static inline nir_intrinsic_instr *
   10852 _nir_build_store_shared_ir3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_shared_ir3_indices indices)
   10853 {
   10854    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10855       build->shader, nir_intrinsic_store_shared_ir3);
   10856 
   10857    intrin->num_components = src0->num_components;
   10858    intrin->src[0] = nir_src_for_ssa(src0);
   10859    intrin->src[1] = nir_src_for_ssa(src1);
   10860    nir_intrinsic_set_base(intrin, indices.base);
   10861    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10862    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10863 
   10864    nir_builder_instr_insert(build, &intrin->instr);
   10865    return intrin;
   10866 }
   10867 static inline nir_intrinsic_instr *
   10868 _nir_build_store_shared_masked_dxil(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   10869 {
   10870    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10871       build->shader, nir_intrinsic_store_shared_masked_dxil);
   10872 
   10873    intrin->src[0] = nir_src_for_ssa(src0);
   10874    intrin->src[1] = nir_src_for_ssa(src1);
   10875    intrin->src[2] = nir_src_for_ssa(src2);
   10876 
   10877    nir_builder_instr_insert(build, &intrin->instr);
   10878    return intrin;
   10879 }
   10880 static inline nir_intrinsic_instr *
   10881 _nir_build_store_ssbo(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_store_ssbo_indices indices)
   10882 {
   10883    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10884       build->shader, nir_intrinsic_store_ssbo);
   10885 
   10886    intrin->num_components = src0->num_components;
   10887    intrin->src[0] = nir_src_for_ssa(src0);
   10888    intrin->src[1] = nir_src_for_ssa(src1);
   10889    intrin->src[2] = nir_src_for_ssa(src2);
   10890    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10891    nir_intrinsic_set_access(intrin, indices.access);
   10892    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10893    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10894 
   10895    nir_builder_instr_insert(build, &intrin->instr);
   10896    return intrin;
   10897 }
   10898 static inline nir_intrinsic_instr *
   10899 _nir_build_store_ssbo_block_intel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, struct _nir_store_ssbo_block_intel_indices indices)
   10900 {
   10901    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10902       build->shader, nir_intrinsic_store_ssbo_block_intel);
   10903 
   10904    intrin->num_components = src0->num_components;
   10905    intrin->src[0] = nir_src_for_ssa(src0);
   10906    intrin->src[1] = nir_src_for_ssa(src1);
   10907    intrin->src[2] = nir_src_for_ssa(src2);
   10908    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10909    nir_intrinsic_set_access(intrin, indices.access);
   10910    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10911    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10912 
   10913    nir_builder_instr_insert(build, &intrin->instr);
   10914    return intrin;
   10915 }
   10916 static inline nir_intrinsic_instr *
   10917 _nir_build_store_ssbo_ir3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, struct _nir_store_ssbo_ir3_indices indices)
   10918 {
   10919    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10920       build->shader, nir_intrinsic_store_ssbo_ir3);
   10921 
   10922    intrin->num_components = src0->num_components;
   10923    intrin->src[0] = nir_src_for_ssa(src0);
   10924    intrin->src[1] = nir_src_for_ssa(src1);
   10925    intrin->src[2] = nir_src_for_ssa(src2);
   10926    intrin->src[3] = nir_src_for_ssa(src3);
   10927    nir_intrinsic_set_write_mask(intrin, indices.write_mask);
   10928    nir_intrinsic_set_access(intrin, indices.access);
   10929    nir_intrinsic_set_align_mul(intrin, indices.align_mul);
   10930    nir_intrinsic_set_align_offset(intrin, indices.align_offset);
   10931 
   10932    nir_builder_instr_insert(build, &intrin->instr);
   10933    return intrin;
   10934 }
   10935 static inline nir_intrinsic_instr *
   10936 _nir_build_store_ssbo_masked_dxil(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3)
   10937 {
   10938    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10939       build->shader, nir_intrinsic_store_ssbo_masked_dxil);
   10940 
   10941    intrin->src[0] = nir_src_for_ssa(src0);
   10942    intrin->src[1] = nir_src_for_ssa(src1);
   10943    intrin->src[2] = nir_src_for_ssa(src2);
   10944    intrin->src[3] = nir_src_for_ssa(src3);
   10945 
   10946    nir_builder_instr_insert(build, &intrin->instr);
   10947    return intrin;
   10948 }
   10949 static inline nir_intrinsic_instr *
   10950 _nir_build_store_tf_r600(nir_builder *build, nir_ssa_def *src0)
   10951 {
   10952    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10953       build->shader, nir_intrinsic_store_tf_r600);
   10954 
   10955    intrin->num_components = src0->num_components;
   10956    intrin->src[0] = nir_src_for_ssa(src0);
   10957 
   10958    nir_builder_instr_insert(build, &intrin->instr);
   10959    return intrin;
   10960 }
   10961 static inline nir_intrinsic_instr *
   10962 _nir_build_store_tlb_sample_color_v3d(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_store_tlb_sample_color_v3d_indices indices)
   10963 {
   10964    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10965       build->shader, nir_intrinsic_store_tlb_sample_color_v3d);
   10966 
   10967    intrin->num_components = src0->num_components;
   10968    intrin->src[0] = nir_src_for_ssa(src0);
   10969    intrin->src[1] = nir_src_for_ssa(src1);
   10970    nir_intrinsic_set_base(intrin, indices.base);
   10971    nir_intrinsic_set_component(intrin, indices.component);
   10972    nir_intrinsic_set_src_type(intrin, indices.src_type);
   10973 
   10974    nir_builder_instr_insert(build, &intrin->instr);
   10975    return intrin;
   10976 }
   10977 static inline nir_intrinsic_instr *
   10978 _nir_build_terminate(nir_builder *build)
   10979 {
   10980    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10981       build->shader, nir_intrinsic_terminate);
   10982 
   10983 
   10984    nir_builder_instr_insert(build, &intrin->instr);
   10985    return intrin;
   10986 }
   10987 static inline nir_intrinsic_instr *
   10988 _nir_build_terminate_if(nir_builder *build, nir_ssa_def *src0)
   10989 {
   10990    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   10991       build->shader, nir_intrinsic_terminate_if);
   10992 
   10993    intrin->src[0] = nir_src_for_ssa(src0);
   10994 
   10995    nir_builder_instr_insert(build, &intrin->instr);
   10996    return intrin;
   10997 }
   10998 static inline nir_intrinsic_instr *
   10999 _nir_build_terminate_ray(nir_builder *build)
   11000 {
   11001    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11002       build->shader, nir_intrinsic_terminate_ray);
   11003 
   11004 
   11005    nir_builder_instr_insert(build, &intrin->instr);
   11006    return intrin;
   11007 }
   11008 static inline nir_intrinsic_instr *
   11009 _nir_build_trace_ray(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3, nir_ssa_def *src4, nir_ssa_def *src5, nir_ssa_def *src6, nir_ssa_def *src7, nir_ssa_def *src8, nir_ssa_def *src9, nir_ssa_def *src10)
   11010 {
   11011    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11012       build->shader, nir_intrinsic_trace_ray);
   11013 
   11014    intrin->src[0] = nir_src_for_ssa(src0);
   11015    intrin->src[1] = nir_src_for_ssa(src1);
   11016    intrin->src[2] = nir_src_for_ssa(src2);
   11017    intrin->src[3] = nir_src_for_ssa(src3);
   11018    intrin->src[4] = nir_src_for_ssa(src4);
   11019    intrin->src[5] = nir_src_for_ssa(src5);
   11020    intrin->src[6] = nir_src_for_ssa(src6);
   11021    intrin->src[7] = nir_src_for_ssa(src7);
   11022    intrin->src[8] = nir_src_for_ssa(src8);
   11023    intrin->src[9] = nir_src_for_ssa(src9);
   11024    intrin->src[10] = nir_src_for_ssa(src10);
   11025 
   11026    nir_builder_instr_insert(build, &intrin->instr);
   11027    return intrin;
   11028 }
   11029 static inline nir_intrinsic_instr *
   11030 _nir_build_trace_ray_commit_intel(nir_builder *build)
   11031 {
   11032    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11033       build->shader, nir_intrinsic_trace_ray_commit_intel);
   11034 
   11035 
   11036    nir_builder_instr_insert(build, &intrin->instr);
   11037    return intrin;
   11038 }
   11039 static inline nir_intrinsic_instr *
   11040 _nir_build_trace_ray_continue_intel(nir_builder *build)
   11041 {
   11042    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11043       build->shader, nir_intrinsic_trace_ray_continue_intel);
   11044 
   11045 
   11046    nir_builder_instr_insert(build, &intrin->instr);
   11047    return intrin;
   11048 }
   11049 static inline nir_intrinsic_instr *
   11050 _nir_build_trace_ray_initial_intel(nir_builder *build)
   11051 {
   11052    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11053       build->shader, nir_intrinsic_trace_ray_initial_intel);
   11054 
   11055 
   11056    nir_builder_instr_insert(build, &intrin->instr);
   11057    return intrin;
   11058 }
   11059 static inline nir_ssa_def *
   11060 _nir_build_vote_all(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   11061 {
   11062    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11063       build->shader, nir_intrinsic_vote_all);
   11064 
   11065       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   11066    intrin->src[0] = nir_src_for_ssa(src0);
   11067 
   11068    nir_builder_instr_insert(build, &intrin->instr);
   11069    return &intrin->dest.ssa;
   11070 }
   11071 static inline nir_ssa_def *
   11072 _nir_build_vote_any(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   11073 {
   11074    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11075       build->shader, nir_intrinsic_vote_any);
   11076 
   11077       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   11078    intrin->src[0] = nir_src_for_ssa(src0);
   11079 
   11080    nir_builder_instr_insert(build, &intrin->instr);
   11081    return &intrin->dest.ssa;
   11082 }
   11083 static inline nir_ssa_def *
   11084 _nir_build_vote_feq(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   11085 {
   11086    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11087       build->shader, nir_intrinsic_vote_feq);
   11088 
   11089    intrin->num_components = src0->num_components;
   11090       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   11091    intrin->src[0] = nir_src_for_ssa(src0);
   11092 
   11093    nir_builder_instr_insert(build, &intrin->instr);
   11094    return &intrin->dest.ssa;
   11095 }
   11096 static inline nir_ssa_def *
   11097 _nir_build_vote_ieq(nir_builder *build, unsigned bit_size, nir_ssa_def *src0)
   11098 {
   11099    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11100       build->shader, nir_intrinsic_vote_ieq);
   11101 
   11102    intrin->num_components = src0->num_components;
   11103       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, bit_size, NULL);
   11104    intrin->src[0] = nir_src_for_ssa(src0);
   11105 
   11106    nir_builder_instr_insert(build, &intrin->instr);
   11107    return &intrin->dest.ssa;
   11108 }
   11109 static inline nir_ssa_def *
   11110 _nir_build_vulkan_resource_index(nir_builder *build, unsigned num_components, unsigned bit_size, nir_ssa_def *src0, struct _nir_vulkan_resource_index_indices indices)
   11111 {
   11112    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11113       build->shader, nir_intrinsic_vulkan_resource_index);
   11114 
   11115    intrin->num_components = num_components;
   11116       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   11117    intrin->src[0] = nir_src_for_ssa(src0);
   11118    nir_intrinsic_set_desc_set(intrin, indices.desc_set);
   11119    nir_intrinsic_set_binding(intrin, indices.binding);
   11120    nir_intrinsic_set_desc_type(intrin, indices.desc_type);
   11121 
   11122    nir_builder_instr_insert(build, &intrin->instr);
   11123    return &intrin->dest.ssa;
   11124 }
   11125 static inline nir_ssa_def *
   11126 _nir_build_vulkan_resource_reindex(nir_builder *build, unsigned bit_size, nir_ssa_def *src0, nir_ssa_def *src1, struct _nir_vulkan_resource_reindex_indices indices)
   11127 {
   11128    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11129       build->shader, nir_intrinsic_vulkan_resource_reindex);
   11130 
   11131    intrin->num_components = src0->num_components;
   11132       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, bit_size, NULL);
   11133    intrin->src[0] = nir_src_for_ssa(src0);
   11134    intrin->src[1] = nir_src_for_ssa(src1);
   11135    nir_intrinsic_set_desc_type(intrin, indices.desc_type);
   11136 
   11137    nir_builder_instr_insert(build, &intrin->instr);
   11138    return &intrin->dest.ssa;
   11139 }
   11140 static inline nir_ssa_def *
   11141 _nir_build_write_invocation_amd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2)
   11142 {
   11143    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(
   11144       build->shader, nir_intrinsic_write_invocation_amd);
   11145 
   11146    intrin->num_components = src0->num_components;
   11147       nir_ssa_dest_init(&intrin->instr, &intrin->dest, intrin->num_components, src0->bit_size, NULL);
   11148    intrin->src[0] = nir_src_for_ssa(src0);
   11149    intrin->src[1] = nir_src_for_ssa(src1);
   11150    intrin->src[2] = nir_src_for_ssa(src2);
   11151 
   11152    nir_builder_instr_insert(build, &intrin->instr);
   11153    return &intrin->dest.ssa;
   11154 }
   11155 
   11156 #define nir_build_accept_ray_intersection _nir_build_accept_ray_intersection
   11157 #define nir_accept_ray_intersection nir_build_accept_ray_intersection
   11158 #ifdef __cplusplus
   11159 #define nir_build_addr_mode_is(build, bit_size, src0, ...) \
   11160 _nir_build_addr_mode_is(build, bit_size, src0, _nir_addr_mode_is_indices{0, __VA_ARGS__})
   11161 #else
   11162 #define nir_build_addr_mode_is(build, bit_size, src0, ...) \
   11163 _nir_build_addr_mode_is(build, bit_size, src0, (struct _nir_addr_mode_is_indices){0, __VA_ARGS__})
   11164 #endif
   11165 #define nir_addr_mode_is nir_build_addr_mode_is
   11166 #define nir_build_alloc_vertices_and_primitives_amd _nir_build_alloc_vertices_and_primitives_amd
   11167 #define nir_alloc_vertices_and_primitives_amd nir_build_alloc_vertices_and_primitives_amd
   11168 #ifdef __cplusplus
   11169 #define nir_build_atomic_counter_add(build, bit_size, src0, src1, ...) \
   11170 _nir_build_atomic_counter_add(build, bit_size, src0, src1, _nir_atomic_counter_add_indices{0, __VA_ARGS__})
   11171 #else
   11172 #define nir_build_atomic_counter_add(build, bit_size, src0, src1, ...) \
   11173 _nir_build_atomic_counter_add(build, bit_size, src0, src1, (struct _nir_atomic_counter_add_indices){0, __VA_ARGS__})
   11174 #endif
   11175 #define nir_atomic_counter_add nir_build_atomic_counter_add
   11176 #define nir_build_atomic_counter_add_deref _nir_build_atomic_counter_add_deref
   11177 #define nir_atomic_counter_add_deref nir_build_atomic_counter_add_deref
   11178 #ifdef __cplusplus
   11179 #define nir_build_atomic_counter_and(build, bit_size, src0, src1, ...) \
   11180 _nir_build_atomic_counter_and(build, bit_size, src0, src1, _nir_atomic_counter_and_indices{0, __VA_ARGS__})
   11181 #else
   11182 #define nir_build_atomic_counter_and(build, bit_size, src0, src1, ...) \
   11183 _nir_build_atomic_counter_and(build, bit_size, src0, src1, (struct _nir_atomic_counter_and_indices){0, __VA_ARGS__})
   11184 #endif
   11185 #define nir_atomic_counter_and nir_build_atomic_counter_and
   11186 #define nir_build_atomic_counter_and_deref _nir_build_atomic_counter_and_deref
   11187 #define nir_atomic_counter_and_deref nir_build_atomic_counter_and_deref
   11188 #ifdef __cplusplus
   11189 #define nir_build_atomic_counter_comp_swap(build, bit_size, src0, src1, src2, ...) \
   11190 _nir_build_atomic_counter_comp_swap(build, bit_size, src0, src1, src2, _nir_atomic_counter_comp_swap_indices{0, __VA_ARGS__})
   11191 #else
   11192 #define nir_build_atomic_counter_comp_swap(build, bit_size, src0, src1, src2, ...) \
   11193 _nir_build_atomic_counter_comp_swap(build, bit_size, src0, src1, src2, (struct _nir_atomic_counter_comp_swap_indices){0, __VA_ARGS__})
   11194 #endif
   11195 #define nir_atomic_counter_comp_swap nir_build_atomic_counter_comp_swap
   11196 #define nir_build_atomic_counter_comp_swap_deref _nir_build_atomic_counter_comp_swap_deref
   11197 #define nir_atomic_counter_comp_swap_deref nir_build_atomic_counter_comp_swap_deref
   11198 #ifdef __cplusplus
   11199 #define nir_build_atomic_counter_exchange(build, bit_size, src0, src1, ...) \
   11200 _nir_build_atomic_counter_exchange(build, bit_size, src0, src1, _nir_atomic_counter_exchange_indices{0, __VA_ARGS__})
   11201 #else
   11202 #define nir_build_atomic_counter_exchange(build, bit_size, src0, src1, ...) \
   11203 _nir_build_atomic_counter_exchange(build, bit_size, src0, src1, (struct _nir_atomic_counter_exchange_indices){0, __VA_ARGS__})
   11204 #endif
   11205 #define nir_atomic_counter_exchange nir_build_atomic_counter_exchange
   11206 #define nir_build_atomic_counter_exchange_deref _nir_build_atomic_counter_exchange_deref
   11207 #define nir_atomic_counter_exchange_deref nir_build_atomic_counter_exchange_deref
   11208 #ifdef __cplusplus
   11209 #define nir_build_atomic_counter_inc(build, bit_size, src0, ...) \
   11210 _nir_build_atomic_counter_inc(build, bit_size, src0, _nir_atomic_counter_inc_indices{0, __VA_ARGS__})
   11211 #else
   11212 #define nir_build_atomic_counter_inc(build, bit_size, src0, ...) \
   11213 _nir_build_atomic_counter_inc(build, bit_size, src0, (struct _nir_atomic_counter_inc_indices){0, __VA_ARGS__})
   11214 #endif
   11215 #define nir_atomic_counter_inc nir_build_atomic_counter_inc
   11216 #define nir_build_atomic_counter_inc_deref _nir_build_atomic_counter_inc_deref
   11217 #define nir_atomic_counter_inc_deref nir_build_atomic_counter_inc_deref
   11218 #ifdef __cplusplus
   11219 #define nir_build_atomic_counter_max(build, bit_size, src0, src1, ...) \
   11220 _nir_build_atomic_counter_max(build, bit_size, src0, src1, _nir_atomic_counter_max_indices{0, __VA_ARGS__})
   11221 #else
   11222 #define nir_build_atomic_counter_max(build, bit_size, src0, src1, ...) \
   11223 _nir_build_atomic_counter_max(build, bit_size, src0, src1, (struct _nir_atomic_counter_max_indices){0, __VA_ARGS__})
   11224 #endif
   11225 #define nir_atomic_counter_max nir_build_atomic_counter_max
   11226 #define nir_build_atomic_counter_max_deref _nir_build_atomic_counter_max_deref
   11227 #define nir_atomic_counter_max_deref nir_build_atomic_counter_max_deref
   11228 #ifdef __cplusplus
   11229 #define nir_build_atomic_counter_min(build, bit_size, src0, src1, ...) \
   11230 _nir_build_atomic_counter_min(build, bit_size, src0, src1, _nir_atomic_counter_min_indices{0, __VA_ARGS__})
   11231 #else
   11232 #define nir_build_atomic_counter_min(build, bit_size, src0, src1, ...) \
   11233 _nir_build_atomic_counter_min(build, bit_size, src0, src1, (struct _nir_atomic_counter_min_indices){0, __VA_ARGS__})
   11234 #endif
   11235 #define nir_atomic_counter_min nir_build_atomic_counter_min
   11236 #define nir_build_atomic_counter_min_deref _nir_build_atomic_counter_min_deref
   11237 #define nir_atomic_counter_min_deref nir_build_atomic_counter_min_deref
   11238 #ifdef __cplusplus
   11239 #define nir_build_atomic_counter_or(build, bit_size, src0, src1, ...) \
   11240 _nir_build_atomic_counter_or(build, bit_size, src0, src1, _nir_atomic_counter_or_indices{0, __VA_ARGS__})
   11241 #else
   11242 #define nir_build_atomic_counter_or(build, bit_size, src0, src1, ...) \
   11243 _nir_build_atomic_counter_or(build, bit_size, src0, src1, (struct _nir_atomic_counter_or_indices){0, __VA_ARGS__})
   11244 #endif
   11245 #define nir_atomic_counter_or nir_build_atomic_counter_or
   11246 #define nir_build_atomic_counter_or_deref _nir_build_atomic_counter_or_deref
   11247 #define nir_atomic_counter_or_deref nir_build_atomic_counter_or_deref
   11248 #ifdef __cplusplus
   11249 #define nir_build_atomic_counter_post_dec(build, bit_size, src0, ...) \
   11250 _nir_build_atomic_counter_post_dec(build, bit_size, src0, _nir_atomic_counter_post_dec_indices{0, __VA_ARGS__})
   11251 #else
   11252 #define nir_build_atomic_counter_post_dec(build, bit_size, src0, ...) \
   11253 _nir_build_atomic_counter_post_dec(build, bit_size, src0, (struct _nir_atomic_counter_post_dec_indices){0, __VA_ARGS__})
   11254 #endif
   11255 #define nir_atomic_counter_post_dec nir_build_atomic_counter_post_dec
   11256 #define nir_build_atomic_counter_post_dec_deref _nir_build_atomic_counter_post_dec_deref
   11257 #define nir_atomic_counter_post_dec_deref nir_build_atomic_counter_post_dec_deref
   11258 #ifdef __cplusplus
   11259 #define nir_build_atomic_counter_pre_dec(build, bit_size, src0, ...) \
   11260 _nir_build_atomic_counter_pre_dec(build, bit_size, src0, _nir_atomic_counter_pre_dec_indices{0, __VA_ARGS__})
   11261 #else
   11262 #define nir_build_atomic_counter_pre_dec(build, bit_size, src0, ...) \
   11263 _nir_build_atomic_counter_pre_dec(build, bit_size, src0, (struct _nir_atomic_counter_pre_dec_indices){0, __VA_ARGS__})
   11264 #endif
   11265 #define nir_atomic_counter_pre_dec nir_build_atomic_counter_pre_dec
   11266 #define nir_build_atomic_counter_pre_dec_deref _nir_build_atomic_counter_pre_dec_deref
   11267 #define nir_atomic_counter_pre_dec_deref nir_build_atomic_counter_pre_dec_deref
   11268 #ifdef __cplusplus
   11269 #define nir_build_atomic_counter_read(build, bit_size, src0, ...) \
   11270 _nir_build_atomic_counter_read(build, bit_size, src0, _nir_atomic_counter_read_indices{0, __VA_ARGS__})
   11271 #else
   11272 #define nir_build_atomic_counter_read(build, bit_size, src0, ...) \
   11273 _nir_build_atomic_counter_read(build, bit_size, src0, (struct _nir_atomic_counter_read_indices){0, __VA_ARGS__})
   11274 #endif
   11275 #define nir_atomic_counter_read nir_build_atomic_counter_read
   11276 #define nir_build_atomic_counter_read_deref _nir_build_atomic_counter_read_deref
   11277 #define nir_atomic_counter_read_deref nir_build_atomic_counter_read_deref
   11278 #ifdef __cplusplus
   11279 #define nir_build_atomic_counter_xor(build, bit_size, src0, src1, ...) \
   11280 _nir_build_atomic_counter_xor(build, bit_size, src0, src1, _nir_atomic_counter_xor_indices{0, __VA_ARGS__})
   11281 #else
   11282 #define nir_build_atomic_counter_xor(build, bit_size, src0, src1, ...) \
   11283 _nir_build_atomic_counter_xor(build, bit_size, src0, src1, (struct _nir_atomic_counter_xor_indices){0, __VA_ARGS__})
   11284 #endif
   11285 #define nir_atomic_counter_xor nir_build_atomic_counter_xor
   11286 #define nir_build_atomic_counter_xor_deref _nir_build_atomic_counter_xor_deref
   11287 #define nir_atomic_counter_xor_deref nir_build_atomic_counter_xor_deref
   11288 #define nir_build_ballot _nir_build_ballot
   11289 #define nir_ballot nir_build_ballot
   11290 #define nir_build_ballot_bit_count_exclusive _nir_build_ballot_bit_count_exclusive
   11291 #define nir_ballot_bit_count_exclusive nir_build_ballot_bit_count_exclusive
   11292 #define nir_build_ballot_bit_count_inclusive _nir_build_ballot_bit_count_inclusive
   11293 #define nir_ballot_bit_count_inclusive nir_build_ballot_bit_count_inclusive
   11294 #define nir_build_ballot_bit_count_reduce _nir_build_ballot_bit_count_reduce
   11295 #define nir_ballot_bit_count_reduce nir_build_ballot_bit_count_reduce
   11296 #define nir_build_ballot_bitfield_extract _nir_build_ballot_bitfield_extract
   11297 #define nir_ballot_bitfield_extract nir_build_ballot_bitfield_extract
   11298 #define nir_build_ballot_find_lsb _nir_build_ballot_find_lsb
   11299 #define nir_ballot_find_lsb nir_build_ballot_find_lsb
   11300 #define nir_build_ballot_find_msb _nir_build_ballot_find_msb
   11301 #define nir_ballot_find_msb nir_build_ballot_find_msb
   11302 #define nir_build_begin_invocation_interlock _nir_build_begin_invocation_interlock
   11303 #define nir_begin_invocation_interlock nir_build_begin_invocation_interlock
   11304 #ifdef __cplusplus
   11305 #define nir_build_bindless_image_atomic_add(build, bit_size, src0, src1, src2, src3, ...) \
   11306 _nir_build_bindless_image_atomic_add(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_add_indices{0, __VA_ARGS__})
   11307 #else
   11308 #define nir_build_bindless_image_atomic_add(build, bit_size, src0, src1, src2, src3, ...) \
   11309 _nir_build_bindless_image_atomic_add(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_add_indices){0, __VA_ARGS__})
   11310 #endif
   11311 #define nir_bindless_image_atomic_add nir_build_bindless_image_atomic_add
   11312 #ifdef __cplusplus
   11313 #define nir_build_bindless_image_atomic_and(build, bit_size, src0, src1, src2, src3, ...) \
   11314 _nir_build_bindless_image_atomic_and(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_and_indices{0, __VA_ARGS__})
   11315 #else
   11316 #define nir_build_bindless_image_atomic_and(build, bit_size, src0, src1, src2, src3, ...) \
   11317 _nir_build_bindless_image_atomic_and(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_and_indices){0, __VA_ARGS__})
   11318 #endif
   11319 #define nir_bindless_image_atomic_and nir_build_bindless_image_atomic_and
   11320 #ifdef __cplusplus
   11321 #define nir_build_bindless_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, ...) \
   11322 _nir_build_bindless_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, _nir_bindless_image_atomic_comp_swap_indices{0, __VA_ARGS__})
   11323 #else
   11324 #define nir_build_bindless_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, ...) \
   11325 _nir_build_bindless_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, (struct _nir_bindless_image_atomic_comp_swap_indices){0, __VA_ARGS__})
   11326 #endif
   11327 #define nir_bindless_image_atomic_comp_swap nir_build_bindless_image_atomic_comp_swap
   11328 #ifdef __cplusplus
   11329 #define nir_build_bindless_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11330 _nir_build_bindless_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_dec_wrap_indices{0, __VA_ARGS__})
   11331 #else
   11332 #define nir_build_bindless_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11333 _nir_build_bindless_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_dec_wrap_indices){0, __VA_ARGS__})
   11334 #endif
   11335 #define nir_bindless_image_atomic_dec_wrap nir_build_bindless_image_atomic_dec_wrap
   11336 #ifdef __cplusplus
   11337 #define nir_build_bindless_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, ...) \
   11338 _nir_build_bindless_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_exchange_indices{0, __VA_ARGS__})
   11339 #else
   11340 #define nir_build_bindless_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, ...) \
   11341 _nir_build_bindless_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_exchange_indices){0, __VA_ARGS__})
   11342 #endif
   11343 #define nir_bindless_image_atomic_exchange nir_build_bindless_image_atomic_exchange
   11344 #ifdef __cplusplus
   11345 #define nir_build_bindless_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, ...) \
   11346 _nir_build_bindless_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_fadd_indices{0, __VA_ARGS__})
   11347 #else
   11348 #define nir_build_bindless_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, ...) \
   11349 _nir_build_bindless_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_fadd_indices){0, __VA_ARGS__})
   11350 #endif
   11351 #define nir_bindless_image_atomic_fadd nir_build_bindless_image_atomic_fadd
   11352 #ifdef __cplusplus
   11353 #define nir_build_bindless_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, ...) \
   11354 _nir_build_bindless_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_fmax_indices{0, __VA_ARGS__})
   11355 #else
   11356 #define nir_build_bindless_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, ...) \
   11357 _nir_build_bindless_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_fmax_indices){0, __VA_ARGS__})
   11358 #endif
   11359 #define nir_bindless_image_atomic_fmax nir_build_bindless_image_atomic_fmax
   11360 #ifdef __cplusplus
   11361 #define nir_build_bindless_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, ...) \
   11362 _nir_build_bindless_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_fmin_indices{0, __VA_ARGS__})
   11363 #else
   11364 #define nir_build_bindless_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, ...) \
   11365 _nir_build_bindless_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_fmin_indices){0, __VA_ARGS__})
   11366 #endif
   11367 #define nir_bindless_image_atomic_fmin nir_build_bindless_image_atomic_fmin
   11368 #ifdef __cplusplus
   11369 #define nir_build_bindless_image_atomic_imax(build, bit_size, src0, src1, src2, src3, ...) \
   11370 _nir_build_bindless_image_atomic_imax(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_imax_indices{0, __VA_ARGS__})
   11371 #else
   11372 #define nir_build_bindless_image_atomic_imax(build, bit_size, src0, src1, src2, src3, ...) \
   11373 _nir_build_bindless_image_atomic_imax(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_imax_indices){0, __VA_ARGS__})
   11374 #endif
   11375 #define nir_bindless_image_atomic_imax nir_build_bindless_image_atomic_imax
   11376 #ifdef __cplusplus
   11377 #define nir_build_bindless_image_atomic_imin(build, bit_size, src0, src1, src2, src3, ...) \
   11378 _nir_build_bindless_image_atomic_imin(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_imin_indices{0, __VA_ARGS__})
   11379 #else
   11380 #define nir_build_bindless_image_atomic_imin(build, bit_size, src0, src1, src2, src3, ...) \
   11381 _nir_build_bindless_image_atomic_imin(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_imin_indices){0, __VA_ARGS__})
   11382 #endif
   11383 #define nir_bindless_image_atomic_imin nir_build_bindless_image_atomic_imin
   11384 #ifdef __cplusplus
   11385 #define nir_build_bindless_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11386 _nir_build_bindless_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_inc_wrap_indices{0, __VA_ARGS__})
   11387 #else
   11388 #define nir_build_bindless_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11389 _nir_build_bindless_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_inc_wrap_indices){0, __VA_ARGS__})
   11390 #endif
   11391 #define nir_bindless_image_atomic_inc_wrap nir_build_bindless_image_atomic_inc_wrap
   11392 #ifdef __cplusplus
   11393 #define nir_build_bindless_image_atomic_or(build, bit_size, src0, src1, src2, src3, ...) \
   11394 _nir_build_bindless_image_atomic_or(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_or_indices{0, __VA_ARGS__})
   11395 #else
   11396 #define nir_build_bindless_image_atomic_or(build, bit_size, src0, src1, src2, src3, ...) \
   11397 _nir_build_bindless_image_atomic_or(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_or_indices){0, __VA_ARGS__})
   11398 #endif
   11399 #define nir_bindless_image_atomic_or nir_build_bindless_image_atomic_or
   11400 #ifdef __cplusplus
   11401 #define nir_build_bindless_image_atomic_umax(build, bit_size, src0, src1, src2, src3, ...) \
   11402 _nir_build_bindless_image_atomic_umax(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_umax_indices{0, __VA_ARGS__})
   11403 #else
   11404 #define nir_build_bindless_image_atomic_umax(build, bit_size, src0, src1, src2, src3, ...) \
   11405 _nir_build_bindless_image_atomic_umax(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_umax_indices){0, __VA_ARGS__})
   11406 #endif
   11407 #define nir_bindless_image_atomic_umax nir_build_bindless_image_atomic_umax
   11408 #ifdef __cplusplus
   11409 #define nir_build_bindless_image_atomic_umin(build, bit_size, src0, src1, src2, src3, ...) \
   11410 _nir_build_bindless_image_atomic_umin(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_umin_indices{0, __VA_ARGS__})
   11411 #else
   11412 #define nir_build_bindless_image_atomic_umin(build, bit_size, src0, src1, src2, src3, ...) \
   11413 _nir_build_bindless_image_atomic_umin(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_umin_indices){0, __VA_ARGS__})
   11414 #endif
   11415 #define nir_bindless_image_atomic_umin nir_build_bindless_image_atomic_umin
   11416 #ifdef __cplusplus
   11417 #define nir_build_bindless_image_atomic_xor(build, bit_size, src0, src1, src2, src3, ...) \
   11418 _nir_build_bindless_image_atomic_xor(build, bit_size, src0, src1, src2, src3, _nir_bindless_image_atomic_xor_indices{0, __VA_ARGS__})
   11419 #else
   11420 #define nir_build_bindless_image_atomic_xor(build, bit_size, src0, src1, src2, src3, ...) \
   11421 _nir_build_bindless_image_atomic_xor(build, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_atomic_xor_indices){0, __VA_ARGS__})
   11422 #endif
   11423 #define nir_bindless_image_atomic_xor nir_build_bindless_image_atomic_xor
   11424 #ifdef __cplusplus
   11425 #define nir_build_bindless_image_format(build, bit_size, src0, ...) \
   11426 _nir_build_bindless_image_format(build, bit_size, src0, _nir_bindless_image_format_indices{0, __VA_ARGS__})
   11427 #else
   11428 #define nir_build_bindless_image_format(build, bit_size, src0, ...) \
   11429 _nir_build_bindless_image_format(build, bit_size, src0, (struct _nir_bindless_image_format_indices){0, __VA_ARGS__})
   11430 #endif
   11431 #define nir_bindless_image_format nir_build_bindless_image_format
   11432 #ifdef __cplusplus
   11433 #define nir_build_bindless_image_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   11434 _nir_build_bindless_image_load(build, num_components, bit_size, src0, src1, src2, src3, _nir_bindless_image_load_indices{0, __VA_ARGS__})
   11435 #else
   11436 #define nir_build_bindless_image_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   11437 _nir_build_bindless_image_load(build, num_components, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_load_indices){0, __VA_ARGS__})
   11438 #endif
   11439 #define nir_bindless_image_load nir_build_bindless_image_load
   11440 #ifdef __cplusplus
   11441 #define nir_build_bindless_image_load_raw_intel(build, num_components, bit_size, src0, src1, ...) \
   11442 _nir_build_bindless_image_load_raw_intel(build, num_components, bit_size, src0, src1, _nir_bindless_image_load_raw_intel_indices{0, __VA_ARGS__})
   11443 #else
   11444 #define nir_build_bindless_image_load_raw_intel(build, num_components, bit_size, src0, src1, ...) \
   11445 _nir_build_bindless_image_load_raw_intel(build, num_components, bit_size, src0, src1, (struct _nir_bindless_image_load_raw_intel_indices){0, __VA_ARGS__})
   11446 #endif
   11447 #define nir_bindless_image_load_raw_intel nir_build_bindless_image_load_raw_intel
   11448 #ifdef __cplusplus
   11449 #define nir_build_bindless_image_order(build, bit_size, src0, ...) \
   11450 _nir_build_bindless_image_order(build, bit_size, src0, _nir_bindless_image_order_indices{0, __VA_ARGS__})
   11451 #else
   11452 #define nir_build_bindless_image_order(build, bit_size, src0, ...) \
   11453 _nir_build_bindless_image_order(build, bit_size, src0, (struct _nir_bindless_image_order_indices){0, __VA_ARGS__})
   11454 #endif
   11455 #define nir_bindless_image_order nir_build_bindless_image_order
   11456 #ifdef __cplusplus
   11457 #define nir_build_bindless_image_samples(build, bit_size, src0, ...) \
   11458 _nir_build_bindless_image_samples(build, bit_size, src0, _nir_bindless_image_samples_indices{0, __VA_ARGS__})
   11459 #else
   11460 #define nir_build_bindless_image_samples(build, bit_size, src0, ...) \
   11461 _nir_build_bindless_image_samples(build, bit_size, src0, (struct _nir_bindless_image_samples_indices){0, __VA_ARGS__})
   11462 #endif
   11463 #define nir_bindless_image_samples nir_build_bindless_image_samples
   11464 #ifdef __cplusplus
   11465 #define nir_build_bindless_image_size(build, num_components, bit_size, src0, src1, ...) \
   11466 _nir_build_bindless_image_size(build, num_components, bit_size, src0, src1, _nir_bindless_image_size_indices{0, __VA_ARGS__})
   11467 #else
   11468 #define nir_build_bindless_image_size(build, num_components, bit_size, src0, src1, ...) \
   11469 _nir_build_bindless_image_size(build, num_components, bit_size, src0, src1, (struct _nir_bindless_image_size_indices){0, __VA_ARGS__})
   11470 #endif
   11471 #define nir_bindless_image_size nir_build_bindless_image_size
   11472 #ifdef __cplusplus
   11473 #define nir_build_bindless_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   11474 _nir_build_bindless_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, _nir_bindless_image_sparse_load_indices{0, __VA_ARGS__})
   11475 #else
   11476 #define nir_build_bindless_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   11477 _nir_build_bindless_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, (struct _nir_bindless_image_sparse_load_indices){0, __VA_ARGS__})
   11478 #endif
   11479 #define nir_bindless_image_sparse_load nir_build_bindless_image_sparse_load
   11480 #ifdef __cplusplus
   11481 #define nir_build_bindless_image_store(build, src0, src1, src2, src3, src4, ...) \
   11482 _nir_build_bindless_image_store(build, src0, src1, src2, src3, src4, _nir_bindless_image_store_indices{0, __VA_ARGS__})
   11483 #else
   11484 #define nir_build_bindless_image_store(build, src0, src1, src2, src3, src4, ...) \
   11485 _nir_build_bindless_image_store(build, src0, src1, src2, src3, src4, (struct _nir_bindless_image_store_indices){0, __VA_ARGS__})
   11486 #endif
   11487 #define nir_bindless_image_store nir_build_bindless_image_store
   11488 #ifdef __cplusplus
   11489 #define nir_build_bindless_image_store_raw_intel(build, src0, src1, src2, ...) \
   11490 _nir_build_bindless_image_store_raw_intel(build, src0, src1, src2, _nir_bindless_image_store_raw_intel_indices{0, __VA_ARGS__})
   11491 #else
   11492 #define nir_build_bindless_image_store_raw_intel(build, src0, src1, src2, ...) \
   11493 _nir_build_bindless_image_store_raw_intel(build, src0, src1, src2, (struct _nir_bindless_image_store_raw_intel_indices){0, __VA_ARGS__})
   11494 #endif
   11495 #define nir_bindless_image_store_raw_intel nir_build_bindless_image_store_raw_intel
   11496 #ifdef __cplusplus
   11497 #define nir_build_bindless_resource_ir3(build, bit_size, src0, ...) \
   11498 _nir_build_bindless_resource_ir3(build, bit_size, src0, _nir_bindless_resource_ir3_indices{0, __VA_ARGS__})
   11499 #else
   11500 #define nir_build_bindless_resource_ir3(build, bit_size, src0, ...) \
   11501 _nir_build_bindless_resource_ir3(build, bit_size, src0, (struct _nir_bindless_resource_ir3_indices){0, __VA_ARGS__})
   11502 #endif
   11503 #define nir_bindless_resource_ir3 nir_build_bindless_resource_ir3
   11504 #define nir_build_btd_retire_intel _nir_build_btd_retire_intel
   11505 #define nir_btd_retire_intel nir_build_btd_retire_intel
   11506 #define nir_build_btd_spawn_intel _nir_build_btd_spawn_intel
   11507 #define nir_btd_spawn_intel nir_build_btd_spawn_intel
   11508 #ifdef __cplusplus
   11509 #define nir_build_btd_stack_push_intel(build, ...) \
   11510 _nir_build_btd_stack_push_intel(build, _nir_btd_stack_push_intel_indices{0, __VA_ARGS__})
   11511 #else
   11512 #define nir_build_btd_stack_push_intel(build, ...) \
   11513 _nir_build_btd_stack_push_intel(build, (struct _nir_btd_stack_push_intel_indices){0, __VA_ARGS__})
   11514 #endif
   11515 #define nir_btd_stack_push_intel nir_build_btd_stack_push_intel
   11516 #define nir_build_bvh64_intersect_ray_amd _nir_build_bvh64_intersect_ray_amd
   11517 #define nir_bvh64_intersect_ray_amd nir_build_bvh64_intersect_ray_amd
   11518 #define nir_build_byte_permute_amd _nir_build_byte_permute_amd
   11519 #define nir_byte_permute_amd nir_build_byte_permute_amd
   11520 #define nir_build_cond_end_ir3 _nir_build_cond_end_ir3
   11521 #define nir_cond_end_ir3 nir_build_cond_end_ir3
   11522 #define nir_build_control_barrier _nir_build_control_barrier
   11523 #define nir_control_barrier nir_build_control_barrier
   11524 #ifdef __cplusplus
   11525 #define nir_build_convert_alu_types(build, bit_size, src0, ...) \
   11526 _nir_build_convert_alu_types(build, bit_size, src0, _nir_convert_alu_types_indices{0, __VA_ARGS__})
   11527 #else
   11528 #define nir_build_convert_alu_types(build, bit_size, src0, ...) \
   11529 _nir_build_convert_alu_types(build, bit_size, src0, (struct _nir_convert_alu_types_indices){0, __VA_ARGS__})
   11530 #endif
   11531 #define nir_convert_alu_types nir_build_convert_alu_types
   11532 #ifdef __cplusplus
   11533 #define nir_build_copy_deref(build, src0, src1, ...) \
   11534 _nir_build_copy_deref(build, src0, src1, _nir_copy_deref_indices{0, __VA_ARGS__})
   11535 #else
   11536 #define nir_build_copy_deref(build, src0, src1, ...) \
   11537 _nir_build_copy_deref(build, src0, src1, (struct _nir_copy_deref_indices){0, __VA_ARGS__})
   11538 #endif
   11539 #define nir_copy_deref nir_build_copy_deref
   11540 #define nir_build_demote _nir_build_demote
   11541 #define nir_demote nir_build_demote
   11542 #define nir_build_demote_if _nir_build_demote_if
   11543 #define nir_demote_if nir_build_demote_if
   11544 #ifdef __cplusplus
   11545 #define nir_build_deref_atomic_add(build, bit_size, src0, src1, ...) \
   11546 _nir_build_deref_atomic_add(build, bit_size, src0, src1, _nir_deref_atomic_add_indices{0, __VA_ARGS__})
   11547 #else
   11548 #define nir_build_deref_atomic_add(build, bit_size, src0, src1, ...) \
   11549 _nir_build_deref_atomic_add(build, bit_size, src0, src1, (struct _nir_deref_atomic_add_indices){0, __VA_ARGS__})
   11550 #endif
   11551 #define nir_deref_atomic_add nir_build_deref_atomic_add
   11552 #ifdef __cplusplus
   11553 #define nir_build_deref_atomic_and(build, bit_size, src0, src1, ...) \
   11554 _nir_build_deref_atomic_and(build, bit_size, src0, src1, _nir_deref_atomic_and_indices{0, __VA_ARGS__})
   11555 #else
   11556 #define nir_build_deref_atomic_and(build, bit_size, src0, src1, ...) \
   11557 _nir_build_deref_atomic_and(build, bit_size, src0, src1, (struct _nir_deref_atomic_and_indices){0, __VA_ARGS__})
   11558 #endif
   11559 #define nir_deref_atomic_and nir_build_deref_atomic_and
   11560 #ifdef __cplusplus
   11561 #define nir_build_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, ...) \
   11562 _nir_build_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, _nir_deref_atomic_comp_swap_indices{0, __VA_ARGS__})
   11563 #else
   11564 #define nir_build_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, ...) \
   11565 _nir_build_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, (struct _nir_deref_atomic_comp_swap_indices){0, __VA_ARGS__})
   11566 #endif
   11567 #define nir_deref_atomic_comp_swap nir_build_deref_atomic_comp_swap
   11568 #ifdef __cplusplus
   11569 #define nir_build_deref_atomic_exchange(build, bit_size, src0, src1, ...) \
   11570 _nir_build_deref_atomic_exchange(build, bit_size, src0, src1, _nir_deref_atomic_exchange_indices{0, __VA_ARGS__})
   11571 #else
   11572 #define nir_build_deref_atomic_exchange(build, bit_size, src0, src1, ...) \
   11573 _nir_build_deref_atomic_exchange(build, bit_size, src0, src1, (struct _nir_deref_atomic_exchange_indices){0, __VA_ARGS__})
   11574 #endif
   11575 #define nir_deref_atomic_exchange nir_build_deref_atomic_exchange
   11576 #ifdef __cplusplus
   11577 #define nir_build_deref_atomic_fadd(build, bit_size, src0, src1, ...) \
   11578 _nir_build_deref_atomic_fadd(build, bit_size, src0, src1, _nir_deref_atomic_fadd_indices{0, __VA_ARGS__})
   11579 #else
   11580 #define nir_build_deref_atomic_fadd(build, bit_size, src0, src1, ...) \
   11581 _nir_build_deref_atomic_fadd(build, bit_size, src0, src1, (struct _nir_deref_atomic_fadd_indices){0, __VA_ARGS__})
   11582 #endif
   11583 #define nir_deref_atomic_fadd nir_build_deref_atomic_fadd
   11584 #ifdef __cplusplus
   11585 #define nir_build_deref_atomic_fcomp_swap(build, bit_size, src0, src1, src2, ...) \
   11586 _nir_build_deref_atomic_fcomp_swap(build, bit_size, src0, src1, src2, _nir_deref_atomic_fcomp_swap_indices{0, __VA_ARGS__})
   11587 #else
   11588 #define nir_build_deref_atomic_fcomp_swap(build, bit_size, src0, src1, src2, ...) \
   11589 _nir_build_deref_atomic_fcomp_swap(build, bit_size, src0, src1, src2, (struct _nir_deref_atomic_fcomp_swap_indices){0, __VA_ARGS__})
   11590 #endif
   11591 #define nir_deref_atomic_fcomp_swap nir_build_deref_atomic_fcomp_swap
   11592 #ifdef __cplusplus
   11593 #define nir_build_deref_atomic_fmax(build, bit_size, src0, src1, ...) \
   11594 _nir_build_deref_atomic_fmax(build, bit_size, src0, src1, _nir_deref_atomic_fmax_indices{0, __VA_ARGS__})
   11595 #else
   11596 #define nir_build_deref_atomic_fmax(build, bit_size, src0, src1, ...) \
   11597 _nir_build_deref_atomic_fmax(build, bit_size, src0, src1, (struct _nir_deref_atomic_fmax_indices){0, __VA_ARGS__})
   11598 #endif
   11599 #define nir_deref_atomic_fmax nir_build_deref_atomic_fmax
   11600 #ifdef __cplusplus
   11601 #define nir_build_deref_atomic_fmin(build, bit_size, src0, src1, ...) \
   11602 _nir_build_deref_atomic_fmin(build, bit_size, src0, src1, _nir_deref_atomic_fmin_indices{0, __VA_ARGS__})
   11603 #else
   11604 #define nir_build_deref_atomic_fmin(build, bit_size, src0, src1, ...) \
   11605 _nir_build_deref_atomic_fmin(build, bit_size, src0, src1, (struct _nir_deref_atomic_fmin_indices){0, __VA_ARGS__})
   11606 #endif
   11607 #define nir_deref_atomic_fmin nir_build_deref_atomic_fmin
   11608 #ifdef __cplusplus
   11609 #define nir_build_deref_atomic_imax(build, bit_size, src0, src1, ...) \
   11610 _nir_build_deref_atomic_imax(build, bit_size, src0, src1, _nir_deref_atomic_imax_indices{0, __VA_ARGS__})
   11611 #else
   11612 #define nir_build_deref_atomic_imax(build, bit_size, src0, src1, ...) \
   11613 _nir_build_deref_atomic_imax(build, bit_size, src0, src1, (struct _nir_deref_atomic_imax_indices){0, __VA_ARGS__})
   11614 #endif
   11615 #define nir_deref_atomic_imax nir_build_deref_atomic_imax
   11616 #ifdef __cplusplus
   11617 #define nir_build_deref_atomic_imin(build, bit_size, src0, src1, ...) \
   11618 _nir_build_deref_atomic_imin(build, bit_size, src0, src1, _nir_deref_atomic_imin_indices{0, __VA_ARGS__})
   11619 #else
   11620 #define nir_build_deref_atomic_imin(build, bit_size, src0, src1, ...) \
   11621 _nir_build_deref_atomic_imin(build, bit_size, src0, src1, (struct _nir_deref_atomic_imin_indices){0, __VA_ARGS__})
   11622 #endif
   11623 #define nir_deref_atomic_imin nir_build_deref_atomic_imin
   11624 #ifdef __cplusplus
   11625 #define nir_build_deref_atomic_or(build, bit_size, src0, src1, ...) \
   11626 _nir_build_deref_atomic_or(build, bit_size, src0, src1, _nir_deref_atomic_or_indices{0, __VA_ARGS__})
   11627 #else
   11628 #define nir_build_deref_atomic_or(build, bit_size, src0, src1, ...) \
   11629 _nir_build_deref_atomic_or(build, bit_size, src0, src1, (struct _nir_deref_atomic_or_indices){0, __VA_ARGS__})
   11630 #endif
   11631 #define nir_deref_atomic_or nir_build_deref_atomic_or
   11632 #ifdef __cplusplus
   11633 #define nir_build_deref_atomic_umax(build, bit_size, src0, src1, ...) \
   11634 _nir_build_deref_atomic_umax(build, bit_size, src0, src1, _nir_deref_atomic_umax_indices{0, __VA_ARGS__})
   11635 #else
   11636 #define nir_build_deref_atomic_umax(build, bit_size, src0, src1, ...) \
   11637 _nir_build_deref_atomic_umax(build, bit_size, src0, src1, (struct _nir_deref_atomic_umax_indices){0, __VA_ARGS__})
   11638 #endif
   11639 #define nir_deref_atomic_umax nir_build_deref_atomic_umax
   11640 #ifdef __cplusplus
   11641 #define nir_build_deref_atomic_umin(build, bit_size, src0, src1, ...) \
   11642 _nir_build_deref_atomic_umin(build, bit_size, src0, src1, _nir_deref_atomic_umin_indices{0, __VA_ARGS__})
   11643 #else
   11644 #define nir_build_deref_atomic_umin(build, bit_size, src0, src1, ...) \
   11645 _nir_build_deref_atomic_umin(build, bit_size, src0, src1, (struct _nir_deref_atomic_umin_indices){0, __VA_ARGS__})
   11646 #endif
   11647 #define nir_deref_atomic_umin nir_build_deref_atomic_umin
   11648 #ifdef __cplusplus
   11649 #define nir_build_deref_atomic_xor(build, bit_size, src0, src1, ...) \
   11650 _nir_build_deref_atomic_xor(build, bit_size, src0, src1, _nir_deref_atomic_xor_indices{0, __VA_ARGS__})
   11651 #else
   11652 #define nir_build_deref_atomic_xor(build, bit_size, src0, src1, ...) \
   11653 _nir_build_deref_atomic_xor(build, bit_size, src0, src1, (struct _nir_deref_atomic_xor_indices){0, __VA_ARGS__})
   11654 #endif
   11655 #define nir_deref_atomic_xor nir_build_deref_atomic_xor
   11656 #ifdef __cplusplus
   11657 #define nir_build_deref_buffer_array_length(build, bit_size, src0, ...) \
   11658 _nir_build_deref_buffer_array_length(build, bit_size, src0, _nir_deref_buffer_array_length_indices{0, __VA_ARGS__})
   11659 #else
   11660 #define nir_build_deref_buffer_array_length(build, bit_size, src0, ...) \
   11661 _nir_build_deref_buffer_array_length(build, bit_size, src0, (struct _nir_deref_buffer_array_length_indices){0, __VA_ARGS__})
   11662 #endif
   11663 #define nir_deref_buffer_array_length nir_build_deref_buffer_array_length
   11664 #ifdef __cplusplus
   11665 #define nir_build_deref_mode_is(build, bit_size, src0, ...) \
   11666 _nir_build_deref_mode_is(build, bit_size, src0, _nir_deref_mode_is_indices{0, __VA_ARGS__})
   11667 #else
   11668 #define nir_build_deref_mode_is(build, bit_size, src0, ...) \
   11669 _nir_build_deref_mode_is(build, bit_size, src0, (struct _nir_deref_mode_is_indices){0, __VA_ARGS__})
   11670 #endif
   11671 #define nir_deref_mode_is nir_build_deref_mode_is
   11672 #define nir_build_discard _nir_build_discard
   11673 #define nir_discard nir_build_discard
   11674 #define nir_build_discard_if _nir_build_discard_if
   11675 #define nir_discard_if nir_build_discard_if
   11676 #define nir_build_elect _nir_build_elect
   11677 #define nir_elect nir_build_elect
   11678 #ifdef __cplusplus
   11679 #define nir_build_emit_vertex(build, ...) \
   11680 _nir_build_emit_vertex(build, _nir_emit_vertex_indices{0, __VA_ARGS__})
   11681 #else
   11682 #define nir_build_emit_vertex(build, ...) \
   11683 _nir_build_emit_vertex(build, (struct _nir_emit_vertex_indices){0, __VA_ARGS__})
   11684 #endif
   11685 #define nir_emit_vertex nir_build_emit_vertex
   11686 #ifdef __cplusplus
   11687 #define nir_build_emit_vertex_with_counter(build, src0, src1, ...) \
   11688 _nir_build_emit_vertex_with_counter(build, src0, src1, _nir_emit_vertex_with_counter_indices{0, __VA_ARGS__})
   11689 #else
   11690 #define nir_build_emit_vertex_with_counter(build, src0, src1, ...) \
   11691 _nir_build_emit_vertex_with_counter(build, src0, src1, (struct _nir_emit_vertex_with_counter_indices){0, __VA_ARGS__})
   11692 #endif
   11693 #define nir_emit_vertex_with_counter nir_build_emit_vertex_with_counter
   11694 #define nir_build_end_invocation_interlock _nir_build_end_invocation_interlock
   11695 #define nir_end_invocation_interlock nir_build_end_invocation_interlock
   11696 #define nir_build_end_patch_ir3 _nir_build_end_patch_ir3
   11697 #define nir_end_patch_ir3 nir_build_end_patch_ir3
   11698 #ifdef __cplusplus
   11699 #define nir_build_end_primitive(build, ...) \
   11700 _nir_build_end_primitive(build, _nir_end_primitive_indices{0, __VA_ARGS__})
   11701 #else
   11702 #define nir_build_end_primitive(build, ...) \
   11703 _nir_build_end_primitive(build, (struct _nir_end_primitive_indices){0, __VA_ARGS__})
   11704 #endif
   11705 #define nir_end_primitive nir_build_end_primitive
   11706 #ifdef __cplusplus
   11707 #define nir_build_end_primitive_with_counter(build, src0, src1, ...) \
   11708 _nir_build_end_primitive_with_counter(build, src0, src1, _nir_end_primitive_with_counter_indices{0, __VA_ARGS__})
   11709 #else
   11710 #define nir_build_end_primitive_with_counter(build, src0, src1, ...) \
   11711 _nir_build_end_primitive_with_counter(build, src0, src1, (struct _nir_end_primitive_with_counter_indices){0, __VA_ARGS__})
   11712 #endif
   11713 #define nir_end_primitive_with_counter nir_build_end_primitive_with_counter
   11714 #ifdef __cplusplus
   11715 #define nir_build_exclusive_scan(build, src0, ...) \
   11716 _nir_build_exclusive_scan(build, src0, _nir_exclusive_scan_indices{0, __VA_ARGS__})
   11717 #else
   11718 #define nir_build_exclusive_scan(build, src0, ...) \
   11719 _nir_build_exclusive_scan(build, src0, (struct _nir_exclusive_scan_indices){0, __VA_ARGS__})
   11720 #endif
   11721 #define nir_exclusive_scan nir_build_exclusive_scan
   11722 #define nir_build_execute_callable _nir_build_execute_callable
   11723 #define nir_execute_callable nir_build_execute_callable
   11724 #define nir_build_export_primitive_amd _nir_build_export_primitive_amd
   11725 #define nir_export_primitive_amd nir_build_export_primitive_amd
   11726 #define nir_build_export_vertex_amd _nir_build_export_vertex_amd
   11727 #define nir_export_vertex_amd nir_build_export_vertex_amd
   11728 #define nir_build_first_invocation _nir_build_first_invocation
   11729 #define nir_first_invocation nir_build_first_invocation
   11730 #ifdef __cplusplus
   11731 #define nir_build_gds_atomic_add_amd(build, bit_size, src0, src1, src2, ...) \
   11732 _nir_build_gds_atomic_add_amd(build, bit_size, src0, src1, src2, _nir_gds_atomic_add_amd_indices{0, __VA_ARGS__})
   11733 #else
   11734 #define nir_build_gds_atomic_add_amd(build, bit_size, src0, src1, src2, ...) \
   11735 _nir_build_gds_atomic_add_amd(build, bit_size, src0, src1, src2, (struct _nir_gds_atomic_add_amd_indices){0, __VA_ARGS__})
   11736 #endif
   11737 #define nir_gds_atomic_add_amd nir_build_gds_atomic_add_amd
   11738 #ifdef __cplusplus
   11739 #define nir_build_get_ssbo_size(build, src0, ...) \
   11740 _nir_build_get_ssbo_size(build, src0, _nir_get_ssbo_size_indices{0, __VA_ARGS__})
   11741 #else
   11742 #define nir_build_get_ssbo_size(build, src0, ...) \
   11743 _nir_build_get_ssbo_size(build, src0, (struct _nir_get_ssbo_size_indices){0, __VA_ARGS__})
   11744 #endif
   11745 #define nir_get_ssbo_size nir_build_get_ssbo_size
   11746 #define nir_build_get_ubo_size _nir_build_get_ubo_size
   11747 #define nir_get_ubo_size nir_build_get_ubo_size
   11748 #ifdef __cplusplus
   11749 #define nir_build_global_atomic_add(build, bit_size, src0, src1, ...) \
   11750 _nir_build_global_atomic_add(build, bit_size, src0, src1, _nir_global_atomic_add_indices{0, __VA_ARGS__})
   11751 #else
   11752 #define nir_build_global_atomic_add(build, bit_size, src0, src1, ...) \
   11753 _nir_build_global_atomic_add(build, bit_size, src0, src1, (struct _nir_global_atomic_add_indices){0, __VA_ARGS__})
   11754 #endif
   11755 #define nir_global_atomic_add nir_build_global_atomic_add
   11756 #ifdef __cplusplus
   11757 #define nir_build_global_atomic_and(build, bit_size, src0, src1, ...) \
   11758 _nir_build_global_atomic_and(build, bit_size, src0, src1, _nir_global_atomic_and_indices{0, __VA_ARGS__})
   11759 #else
   11760 #define nir_build_global_atomic_and(build, bit_size, src0, src1, ...) \
   11761 _nir_build_global_atomic_and(build, bit_size, src0, src1, (struct _nir_global_atomic_and_indices){0, __VA_ARGS__})
   11762 #endif
   11763 #define nir_global_atomic_and nir_build_global_atomic_and
   11764 #ifdef __cplusplus
   11765 #define nir_build_global_atomic_comp_swap(build, bit_size, src0, src1, src2, ...) \
   11766 _nir_build_global_atomic_comp_swap(build, bit_size, src0, src1, src2, _nir_global_atomic_comp_swap_indices{0, __VA_ARGS__})
   11767 #else
   11768 #define nir_build_global_atomic_comp_swap(build, bit_size, src0, src1, src2, ...) \
   11769 _nir_build_global_atomic_comp_swap(build, bit_size, src0, src1, src2, (struct _nir_global_atomic_comp_swap_indices){0, __VA_ARGS__})
   11770 #endif
   11771 #define nir_global_atomic_comp_swap nir_build_global_atomic_comp_swap
   11772 #ifdef __cplusplus
   11773 #define nir_build_global_atomic_exchange(build, bit_size, src0, src1, ...) \
   11774 _nir_build_global_atomic_exchange(build, bit_size, src0, src1, _nir_global_atomic_exchange_indices{0, __VA_ARGS__})
   11775 #else
   11776 #define nir_build_global_atomic_exchange(build, bit_size, src0, src1, ...) \
   11777 _nir_build_global_atomic_exchange(build, bit_size, src0, src1, (struct _nir_global_atomic_exchange_indices){0, __VA_ARGS__})
   11778 #endif
   11779 #define nir_global_atomic_exchange nir_build_global_atomic_exchange
   11780 #ifdef __cplusplus
   11781 #define nir_build_global_atomic_fadd(build, bit_size, src0, src1, ...) \
   11782 _nir_build_global_atomic_fadd(build, bit_size, src0, src1, _nir_global_atomic_fadd_indices{0, __VA_ARGS__})
   11783 #else
   11784 #define nir_build_global_atomic_fadd(build, bit_size, src0, src1, ...) \
   11785 _nir_build_global_atomic_fadd(build, bit_size, src0, src1, (struct _nir_global_atomic_fadd_indices){0, __VA_ARGS__})
   11786 #endif
   11787 #define nir_global_atomic_fadd nir_build_global_atomic_fadd
   11788 #ifdef __cplusplus
   11789 #define nir_build_global_atomic_fcomp_swap(build, bit_size, src0, src1, src2, ...) \
   11790 _nir_build_global_atomic_fcomp_swap(build, bit_size, src0, src1, src2, _nir_global_atomic_fcomp_swap_indices{0, __VA_ARGS__})
   11791 #else
   11792 #define nir_build_global_atomic_fcomp_swap(build, bit_size, src0, src1, src2, ...) \
   11793 _nir_build_global_atomic_fcomp_swap(build, bit_size, src0, src1, src2, (struct _nir_global_atomic_fcomp_swap_indices){0, __VA_ARGS__})
   11794 #endif
   11795 #define nir_global_atomic_fcomp_swap nir_build_global_atomic_fcomp_swap
   11796 #ifdef __cplusplus
   11797 #define nir_build_global_atomic_fmax(build, bit_size, src0, src1, ...) \
   11798 _nir_build_global_atomic_fmax(build, bit_size, src0, src1, _nir_global_atomic_fmax_indices{0, __VA_ARGS__})
   11799 #else
   11800 #define nir_build_global_atomic_fmax(build, bit_size, src0, src1, ...) \
   11801 _nir_build_global_atomic_fmax(build, bit_size, src0, src1, (struct _nir_global_atomic_fmax_indices){0, __VA_ARGS__})
   11802 #endif
   11803 #define nir_global_atomic_fmax nir_build_global_atomic_fmax
   11804 #ifdef __cplusplus
   11805 #define nir_build_global_atomic_fmin(build, bit_size, src0, src1, ...) \
   11806 _nir_build_global_atomic_fmin(build, bit_size, src0, src1, _nir_global_atomic_fmin_indices{0, __VA_ARGS__})
   11807 #else
   11808 #define nir_build_global_atomic_fmin(build, bit_size, src0, src1, ...) \
   11809 _nir_build_global_atomic_fmin(build, bit_size, src0, src1, (struct _nir_global_atomic_fmin_indices){0, __VA_ARGS__})
   11810 #endif
   11811 #define nir_global_atomic_fmin nir_build_global_atomic_fmin
   11812 #ifdef __cplusplus
   11813 #define nir_build_global_atomic_imax(build, bit_size, src0, src1, ...) \
   11814 _nir_build_global_atomic_imax(build, bit_size, src0, src1, _nir_global_atomic_imax_indices{0, __VA_ARGS__})
   11815 #else
   11816 #define nir_build_global_atomic_imax(build, bit_size, src0, src1, ...) \
   11817 _nir_build_global_atomic_imax(build, bit_size, src0, src1, (struct _nir_global_atomic_imax_indices){0, __VA_ARGS__})
   11818 #endif
   11819 #define nir_global_atomic_imax nir_build_global_atomic_imax
   11820 #ifdef __cplusplus
   11821 #define nir_build_global_atomic_imin(build, bit_size, src0, src1, ...) \
   11822 _nir_build_global_atomic_imin(build, bit_size, src0, src1, _nir_global_atomic_imin_indices{0, __VA_ARGS__})
   11823 #else
   11824 #define nir_build_global_atomic_imin(build, bit_size, src0, src1, ...) \
   11825 _nir_build_global_atomic_imin(build, bit_size, src0, src1, (struct _nir_global_atomic_imin_indices){0, __VA_ARGS__})
   11826 #endif
   11827 #define nir_global_atomic_imin nir_build_global_atomic_imin
   11828 #ifdef __cplusplus
   11829 #define nir_build_global_atomic_or(build, bit_size, src0, src1, ...) \
   11830 _nir_build_global_atomic_or(build, bit_size, src0, src1, _nir_global_atomic_or_indices{0, __VA_ARGS__})
   11831 #else
   11832 #define nir_build_global_atomic_or(build, bit_size, src0, src1, ...) \
   11833 _nir_build_global_atomic_or(build, bit_size, src0, src1, (struct _nir_global_atomic_or_indices){0, __VA_ARGS__})
   11834 #endif
   11835 #define nir_global_atomic_or nir_build_global_atomic_or
   11836 #ifdef __cplusplus
   11837 #define nir_build_global_atomic_umax(build, bit_size, src0, src1, ...) \
   11838 _nir_build_global_atomic_umax(build, bit_size, src0, src1, _nir_global_atomic_umax_indices{0, __VA_ARGS__})
   11839 #else
   11840 #define nir_build_global_atomic_umax(build, bit_size, src0, src1, ...) \
   11841 _nir_build_global_atomic_umax(build, bit_size, src0, src1, (struct _nir_global_atomic_umax_indices){0, __VA_ARGS__})
   11842 #endif
   11843 #define nir_global_atomic_umax nir_build_global_atomic_umax
   11844 #ifdef __cplusplus
   11845 #define nir_build_global_atomic_umin(build, bit_size, src0, src1, ...) \
   11846 _nir_build_global_atomic_umin(build, bit_size, src0, src1, _nir_global_atomic_umin_indices{0, __VA_ARGS__})
   11847 #else
   11848 #define nir_build_global_atomic_umin(build, bit_size, src0, src1, ...) \
   11849 _nir_build_global_atomic_umin(build, bit_size, src0, src1, (struct _nir_global_atomic_umin_indices){0, __VA_ARGS__})
   11850 #endif
   11851 #define nir_global_atomic_umin nir_build_global_atomic_umin
   11852 #ifdef __cplusplus
   11853 #define nir_build_global_atomic_xor(build, bit_size, src0, src1, ...) \
   11854 _nir_build_global_atomic_xor(build, bit_size, src0, src1, _nir_global_atomic_xor_indices{0, __VA_ARGS__})
   11855 #else
   11856 #define nir_build_global_atomic_xor(build, bit_size, src0, src1, ...) \
   11857 _nir_build_global_atomic_xor(build, bit_size, src0, src1, (struct _nir_global_atomic_xor_indices){0, __VA_ARGS__})
   11858 #endif
   11859 #define nir_global_atomic_xor nir_build_global_atomic_xor
   11860 #define nir_build_group_memory_barrier _nir_build_group_memory_barrier
   11861 #define nir_group_memory_barrier nir_build_group_memory_barrier
   11862 #define nir_build_has_input_primitive_amd _nir_build_has_input_primitive_amd
   11863 #define nir_has_input_primitive_amd nir_build_has_input_primitive_amd
   11864 #define nir_build_has_input_vertex_amd _nir_build_has_input_vertex_amd
   11865 #define nir_has_input_vertex_amd nir_build_has_input_vertex_amd
   11866 #define nir_build_ignore_ray_intersection _nir_build_ignore_ray_intersection
   11867 #define nir_ignore_ray_intersection nir_build_ignore_ray_intersection
   11868 #ifdef __cplusplus
   11869 #define nir_build_image_atomic_add(build, bit_size, src0, src1, src2, src3, ...) \
   11870 _nir_build_image_atomic_add(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_add_indices{0, __VA_ARGS__})
   11871 #else
   11872 #define nir_build_image_atomic_add(build, bit_size, src0, src1, src2, src3, ...) \
   11873 _nir_build_image_atomic_add(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_add_indices){0, __VA_ARGS__})
   11874 #endif
   11875 #define nir_image_atomic_add nir_build_image_atomic_add
   11876 #ifdef __cplusplus
   11877 #define nir_build_image_atomic_and(build, bit_size, src0, src1, src2, src3, ...) \
   11878 _nir_build_image_atomic_and(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_and_indices{0, __VA_ARGS__})
   11879 #else
   11880 #define nir_build_image_atomic_and(build, bit_size, src0, src1, src2, src3, ...) \
   11881 _nir_build_image_atomic_and(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_and_indices){0, __VA_ARGS__})
   11882 #endif
   11883 #define nir_image_atomic_and nir_build_image_atomic_and
   11884 #ifdef __cplusplus
   11885 #define nir_build_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, ...) \
   11886 _nir_build_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, _nir_image_atomic_comp_swap_indices{0, __VA_ARGS__})
   11887 #else
   11888 #define nir_build_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, ...) \
   11889 _nir_build_image_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, (struct _nir_image_atomic_comp_swap_indices){0, __VA_ARGS__})
   11890 #endif
   11891 #define nir_image_atomic_comp_swap nir_build_image_atomic_comp_swap
   11892 #ifdef __cplusplus
   11893 #define nir_build_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11894 _nir_build_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_dec_wrap_indices{0, __VA_ARGS__})
   11895 #else
   11896 #define nir_build_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11897 _nir_build_image_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_dec_wrap_indices){0, __VA_ARGS__})
   11898 #endif
   11899 #define nir_image_atomic_dec_wrap nir_build_image_atomic_dec_wrap
   11900 #ifdef __cplusplus
   11901 #define nir_build_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, ...) \
   11902 _nir_build_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_exchange_indices{0, __VA_ARGS__})
   11903 #else
   11904 #define nir_build_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, ...) \
   11905 _nir_build_image_atomic_exchange(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_exchange_indices){0, __VA_ARGS__})
   11906 #endif
   11907 #define nir_image_atomic_exchange nir_build_image_atomic_exchange
   11908 #ifdef __cplusplus
   11909 #define nir_build_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, ...) \
   11910 _nir_build_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_fadd_indices{0, __VA_ARGS__})
   11911 #else
   11912 #define nir_build_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, ...) \
   11913 _nir_build_image_atomic_fadd(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_fadd_indices){0, __VA_ARGS__})
   11914 #endif
   11915 #define nir_image_atomic_fadd nir_build_image_atomic_fadd
   11916 #ifdef __cplusplus
   11917 #define nir_build_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, ...) \
   11918 _nir_build_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_fmax_indices{0, __VA_ARGS__})
   11919 #else
   11920 #define nir_build_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, ...) \
   11921 _nir_build_image_atomic_fmax(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_fmax_indices){0, __VA_ARGS__})
   11922 #endif
   11923 #define nir_image_atomic_fmax nir_build_image_atomic_fmax
   11924 #ifdef __cplusplus
   11925 #define nir_build_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, ...) \
   11926 _nir_build_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_fmin_indices{0, __VA_ARGS__})
   11927 #else
   11928 #define nir_build_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, ...) \
   11929 _nir_build_image_atomic_fmin(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_fmin_indices){0, __VA_ARGS__})
   11930 #endif
   11931 #define nir_image_atomic_fmin nir_build_image_atomic_fmin
   11932 #ifdef __cplusplus
   11933 #define nir_build_image_atomic_imax(build, bit_size, src0, src1, src2, src3, ...) \
   11934 _nir_build_image_atomic_imax(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_imax_indices{0, __VA_ARGS__})
   11935 #else
   11936 #define nir_build_image_atomic_imax(build, bit_size, src0, src1, src2, src3, ...) \
   11937 _nir_build_image_atomic_imax(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_imax_indices){0, __VA_ARGS__})
   11938 #endif
   11939 #define nir_image_atomic_imax nir_build_image_atomic_imax
   11940 #ifdef __cplusplus
   11941 #define nir_build_image_atomic_imin(build, bit_size, src0, src1, src2, src3, ...) \
   11942 _nir_build_image_atomic_imin(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_imin_indices{0, __VA_ARGS__})
   11943 #else
   11944 #define nir_build_image_atomic_imin(build, bit_size, src0, src1, src2, src3, ...) \
   11945 _nir_build_image_atomic_imin(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_imin_indices){0, __VA_ARGS__})
   11946 #endif
   11947 #define nir_image_atomic_imin nir_build_image_atomic_imin
   11948 #ifdef __cplusplus
   11949 #define nir_build_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11950 _nir_build_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_inc_wrap_indices{0, __VA_ARGS__})
   11951 #else
   11952 #define nir_build_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   11953 _nir_build_image_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_inc_wrap_indices){0, __VA_ARGS__})
   11954 #endif
   11955 #define nir_image_atomic_inc_wrap nir_build_image_atomic_inc_wrap
   11956 #ifdef __cplusplus
   11957 #define nir_build_image_atomic_or(build, bit_size, src0, src1, src2, src3, ...) \
   11958 _nir_build_image_atomic_or(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_or_indices{0, __VA_ARGS__})
   11959 #else
   11960 #define nir_build_image_atomic_or(build, bit_size, src0, src1, src2, src3, ...) \
   11961 _nir_build_image_atomic_or(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_or_indices){0, __VA_ARGS__})
   11962 #endif
   11963 #define nir_image_atomic_or nir_build_image_atomic_or
   11964 #ifdef __cplusplus
   11965 #define nir_build_image_atomic_umax(build, bit_size, src0, src1, src2, src3, ...) \
   11966 _nir_build_image_atomic_umax(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_umax_indices{0, __VA_ARGS__})
   11967 #else
   11968 #define nir_build_image_atomic_umax(build, bit_size, src0, src1, src2, src3, ...) \
   11969 _nir_build_image_atomic_umax(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_umax_indices){0, __VA_ARGS__})
   11970 #endif
   11971 #define nir_image_atomic_umax nir_build_image_atomic_umax
   11972 #ifdef __cplusplus
   11973 #define nir_build_image_atomic_umin(build, bit_size, src0, src1, src2, src3, ...) \
   11974 _nir_build_image_atomic_umin(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_umin_indices{0, __VA_ARGS__})
   11975 #else
   11976 #define nir_build_image_atomic_umin(build, bit_size, src0, src1, src2, src3, ...) \
   11977 _nir_build_image_atomic_umin(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_umin_indices){0, __VA_ARGS__})
   11978 #endif
   11979 #define nir_image_atomic_umin nir_build_image_atomic_umin
   11980 #ifdef __cplusplus
   11981 #define nir_build_image_atomic_xor(build, bit_size, src0, src1, src2, src3, ...) \
   11982 _nir_build_image_atomic_xor(build, bit_size, src0, src1, src2, src3, _nir_image_atomic_xor_indices{0, __VA_ARGS__})
   11983 #else
   11984 #define nir_build_image_atomic_xor(build, bit_size, src0, src1, src2, src3, ...) \
   11985 _nir_build_image_atomic_xor(build, bit_size, src0, src1, src2, src3, (struct _nir_image_atomic_xor_indices){0, __VA_ARGS__})
   11986 #endif
   11987 #define nir_image_atomic_xor nir_build_image_atomic_xor
   11988 #ifdef __cplusplus
   11989 #define nir_build_image_deref_atomic_add(build, bit_size, src0, src1, src2, src3, ...) \
   11990 _nir_build_image_deref_atomic_add(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_add_indices{0, __VA_ARGS__})
   11991 #else
   11992 #define nir_build_image_deref_atomic_add(build, bit_size, src0, src1, src2, src3, ...) \
   11993 _nir_build_image_deref_atomic_add(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_add_indices){0, __VA_ARGS__})
   11994 #endif
   11995 #define nir_image_deref_atomic_add nir_build_image_deref_atomic_add
   11996 #ifdef __cplusplus
   11997 #define nir_build_image_deref_atomic_and(build, bit_size, src0, src1, src2, src3, ...) \
   11998 _nir_build_image_deref_atomic_and(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_and_indices{0, __VA_ARGS__})
   11999 #else
   12000 #define nir_build_image_deref_atomic_and(build, bit_size, src0, src1, src2, src3, ...) \
   12001 _nir_build_image_deref_atomic_and(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_and_indices){0, __VA_ARGS__})
   12002 #endif
   12003 #define nir_image_deref_atomic_and nir_build_image_deref_atomic_and
   12004 #ifdef __cplusplus
   12005 #define nir_build_image_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, ...) \
   12006 _nir_build_image_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, _nir_image_deref_atomic_comp_swap_indices{0, __VA_ARGS__})
   12007 #else
   12008 #define nir_build_image_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, ...) \
   12009 _nir_build_image_deref_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, src4, (struct _nir_image_deref_atomic_comp_swap_indices){0, __VA_ARGS__})
   12010 #endif
   12011 #define nir_image_deref_atomic_comp_swap nir_build_image_deref_atomic_comp_swap
   12012 #ifdef __cplusplus
   12013 #define nir_build_image_deref_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   12014 _nir_build_image_deref_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_dec_wrap_indices{0, __VA_ARGS__})
   12015 #else
   12016 #define nir_build_image_deref_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   12017 _nir_build_image_deref_atomic_dec_wrap(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_dec_wrap_indices){0, __VA_ARGS__})
   12018 #endif
   12019 #define nir_image_deref_atomic_dec_wrap nir_build_image_deref_atomic_dec_wrap
   12020 #ifdef __cplusplus
   12021 #define nir_build_image_deref_atomic_exchange(build, bit_size, src0, src1, src2, src3, ...) \
   12022 _nir_build_image_deref_atomic_exchange(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_exchange_indices{0, __VA_ARGS__})
   12023 #else
   12024 #define nir_build_image_deref_atomic_exchange(build, bit_size, src0, src1, src2, src3, ...) \
   12025 _nir_build_image_deref_atomic_exchange(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_exchange_indices){0, __VA_ARGS__})
   12026 #endif
   12027 #define nir_image_deref_atomic_exchange nir_build_image_deref_atomic_exchange
   12028 #ifdef __cplusplus
   12029 #define nir_build_image_deref_atomic_fadd(build, bit_size, src0, src1, src2, src3, ...) \
   12030 _nir_build_image_deref_atomic_fadd(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_fadd_indices{0, __VA_ARGS__})
   12031 #else
   12032 #define nir_build_image_deref_atomic_fadd(build, bit_size, src0, src1, src2, src3, ...) \
   12033 _nir_build_image_deref_atomic_fadd(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_fadd_indices){0, __VA_ARGS__})
   12034 #endif
   12035 #define nir_image_deref_atomic_fadd nir_build_image_deref_atomic_fadd
   12036 #ifdef __cplusplus
   12037 #define nir_build_image_deref_atomic_fmax(build, bit_size, src0, src1, src2, src3, ...) \
   12038 _nir_build_image_deref_atomic_fmax(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_fmax_indices{0, __VA_ARGS__})
   12039 #else
   12040 #define nir_build_image_deref_atomic_fmax(build, bit_size, src0, src1, src2, src3, ...) \
   12041 _nir_build_image_deref_atomic_fmax(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_fmax_indices){0, __VA_ARGS__})
   12042 #endif
   12043 #define nir_image_deref_atomic_fmax nir_build_image_deref_atomic_fmax
   12044 #ifdef __cplusplus
   12045 #define nir_build_image_deref_atomic_fmin(build, bit_size, src0, src1, src2, src3, ...) \
   12046 _nir_build_image_deref_atomic_fmin(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_fmin_indices{0, __VA_ARGS__})
   12047 #else
   12048 #define nir_build_image_deref_atomic_fmin(build, bit_size, src0, src1, src2, src3, ...) \
   12049 _nir_build_image_deref_atomic_fmin(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_fmin_indices){0, __VA_ARGS__})
   12050 #endif
   12051 #define nir_image_deref_atomic_fmin nir_build_image_deref_atomic_fmin
   12052 #ifdef __cplusplus
   12053 #define nir_build_image_deref_atomic_imax(build, bit_size, src0, src1, src2, src3, ...) \
   12054 _nir_build_image_deref_atomic_imax(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_imax_indices{0, __VA_ARGS__})
   12055 #else
   12056 #define nir_build_image_deref_atomic_imax(build, bit_size, src0, src1, src2, src3, ...) \
   12057 _nir_build_image_deref_atomic_imax(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_imax_indices){0, __VA_ARGS__})
   12058 #endif
   12059 #define nir_image_deref_atomic_imax nir_build_image_deref_atomic_imax
   12060 #ifdef __cplusplus
   12061 #define nir_build_image_deref_atomic_imin(build, bit_size, src0, src1, src2, src3, ...) \
   12062 _nir_build_image_deref_atomic_imin(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_imin_indices{0, __VA_ARGS__})
   12063 #else
   12064 #define nir_build_image_deref_atomic_imin(build, bit_size, src0, src1, src2, src3, ...) \
   12065 _nir_build_image_deref_atomic_imin(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_imin_indices){0, __VA_ARGS__})
   12066 #endif
   12067 #define nir_image_deref_atomic_imin nir_build_image_deref_atomic_imin
   12068 #ifdef __cplusplus
   12069 #define nir_build_image_deref_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   12070 _nir_build_image_deref_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_inc_wrap_indices{0, __VA_ARGS__})
   12071 #else
   12072 #define nir_build_image_deref_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, ...) \
   12073 _nir_build_image_deref_atomic_inc_wrap(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_inc_wrap_indices){0, __VA_ARGS__})
   12074 #endif
   12075 #define nir_image_deref_atomic_inc_wrap nir_build_image_deref_atomic_inc_wrap
   12076 #ifdef __cplusplus
   12077 #define nir_build_image_deref_atomic_or(build, bit_size, src0, src1, src2, src3, ...) \
   12078 _nir_build_image_deref_atomic_or(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_or_indices{0, __VA_ARGS__})
   12079 #else
   12080 #define nir_build_image_deref_atomic_or(build, bit_size, src0, src1, src2, src3, ...) \
   12081 _nir_build_image_deref_atomic_or(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_or_indices){0, __VA_ARGS__})
   12082 #endif
   12083 #define nir_image_deref_atomic_or nir_build_image_deref_atomic_or
   12084 #ifdef __cplusplus
   12085 #define nir_build_image_deref_atomic_umax(build, bit_size, src0, src1, src2, src3, ...) \
   12086 _nir_build_image_deref_atomic_umax(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_umax_indices{0, __VA_ARGS__})
   12087 #else
   12088 #define nir_build_image_deref_atomic_umax(build, bit_size, src0, src1, src2, src3, ...) \
   12089 _nir_build_image_deref_atomic_umax(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_umax_indices){0, __VA_ARGS__})
   12090 #endif
   12091 #define nir_image_deref_atomic_umax nir_build_image_deref_atomic_umax
   12092 #ifdef __cplusplus
   12093 #define nir_build_image_deref_atomic_umin(build, bit_size, src0, src1, src2, src3, ...) \
   12094 _nir_build_image_deref_atomic_umin(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_umin_indices{0, __VA_ARGS__})
   12095 #else
   12096 #define nir_build_image_deref_atomic_umin(build, bit_size, src0, src1, src2, src3, ...) \
   12097 _nir_build_image_deref_atomic_umin(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_umin_indices){0, __VA_ARGS__})
   12098 #endif
   12099 #define nir_image_deref_atomic_umin nir_build_image_deref_atomic_umin
   12100 #ifdef __cplusplus
   12101 #define nir_build_image_deref_atomic_xor(build, bit_size, src0, src1, src2, src3, ...) \
   12102 _nir_build_image_deref_atomic_xor(build, bit_size, src0, src1, src2, src3, _nir_image_deref_atomic_xor_indices{0, __VA_ARGS__})
   12103 #else
   12104 #define nir_build_image_deref_atomic_xor(build, bit_size, src0, src1, src2, src3, ...) \
   12105 _nir_build_image_deref_atomic_xor(build, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_atomic_xor_indices){0, __VA_ARGS__})
   12106 #endif
   12107 #define nir_image_deref_atomic_xor nir_build_image_deref_atomic_xor
   12108 #ifdef __cplusplus
   12109 #define nir_build_image_deref_format(build, bit_size, src0, ...) \
   12110 _nir_build_image_deref_format(build, bit_size, src0, _nir_image_deref_format_indices{0, __VA_ARGS__})
   12111 #else
   12112 #define nir_build_image_deref_format(build, bit_size, src0, ...) \
   12113 _nir_build_image_deref_format(build, bit_size, src0, (struct _nir_image_deref_format_indices){0, __VA_ARGS__})
   12114 #endif
   12115 #define nir_image_deref_format nir_build_image_deref_format
   12116 #ifdef __cplusplus
   12117 #define nir_build_image_deref_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12118 _nir_build_image_deref_load(build, num_components, bit_size, src0, src1, src2, src3, _nir_image_deref_load_indices{0, __VA_ARGS__})
   12119 #else
   12120 #define nir_build_image_deref_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12121 _nir_build_image_deref_load(build, num_components, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_load_indices){0, __VA_ARGS__})
   12122 #endif
   12123 #define nir_image_deref_load nir_build_image_deref_load
   12124 #ifdef __cplusplus
   12125 #define nir_build_image_deref_load_param_intel(build, num_components, bit_size, src0, ...) \
   12126 _nir_build_image_deref_load_param_intel(build, num_components, bit_size, src0, _nir_image_deref_load_param_intel_indices{0, __VA_ARGS__})
   12127 #else
   12128 #define nir_build_image_deref_load_param_intel(build, num_components, bit_size, src0, ...) \
   12129 _nir_build_image_deref_load_param_intel(build, num_components, bit_size, src0, (struct _nir_image_deref_load_param_intel_indices){0, __VA_ARGS__})
   12130 #endif
   12131 #define nir_image_deref_load_param_intel nir_build_image_deref_load_param_intel
   12132 #ifdef __cplusplus
   12133 #define nir_build_image_deref_load_raw_intel(build, num_components, bit_size, src0, src1, ...) \
   12134 _nir_build_image_deref_load_raw_intel(build, num_components, bit_size, src0, src1, _nir_image_deref_load_raw_intel_indices{0, __VA_ARGS__})
   12135 #else
   12136 #define nir_build_image_deref_load_raw_intel(build, num_components, bit_size, src0, src1, ...) \
   12137 _nir_build_image_deref_load_raw_intel(build, num_components, bit_size, src0, src1, (struct _nir_image_deref_load_raw_intel_indices){0, __VA_ARGS__})
   12138 #endif
   12139 #define nir_image_deref_load_raw_intel nir_build_image_deref_load_raw_intel
   12140 #ifdef __cplusplus
   12141 #define nir_build_image_deref_order(build, bit_size, src0, ...) \
   12142 _nir_build_image_deref_order(build, bit_size, src0, _nir_image_deref_order_indices{0, __VA_ARGS__})
   12143 #else
   12144 #define nir_build_image_deref_order(build, bit_size, src0, ...) \
   12145 _nir_build_image_deref_order(build, bit_size, src0, (struct _nir_image_deref_order_indices){0, __VA_ARGS__})
   12146 #endif
   12147 #define nir_image_deref_order nir_build_image_deref_order
   12148 #ifdef __cplusplus
   12149 #define nir_build_image_deref_samples(build, bit_size, src0, ...) \
   12150 _nir_build_image_deref_samples(build, bit_size, src0, _nir_image_deref_samples_indices{0, __VA_ARGS__})
   12151 #else
   12152 #define nir_build_image_deref_samples(build, bit_size, src0, ...) \
   12153 _nir_build_image_deref_samples(build, bit_size, src0, (struct _nir_image_deref_samples_indices){0, __VA_ARGS__})
   12154 #endif
   12155 #define nir_image_deref_samples nir_build_image_deref_samples
   12156 #ifdef __cplusplus
   12157 #define nir_build_image_deref_size(build, num_components, bit_size, src0, src1, ...) \
   12158 _nir_build_image_deref_size(build, num_components, bit_size, src0, src1, _nir_image_deref_size_indices{0, __VA_ARGS__})
   12159 #else
   12160 #define nir_build_image_deref_size(build, num_components, bit_size, src0, src1, ...) \
   12161 _nir_build_image_deref_size(build, num_components, bit_size, src0, src1, (struct _nir_image_deref_size_indices){0, __VA_ARGS__})
   12162 #endif
   12163 #define nir_image_deref_size nir_build_image_deref_size
   12164 #ifdef __cplusplus
   12165 #define nir_build_image_deref_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12166 _nir_build_image_deref_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, _nir_image_deref_sparse_load_indices{0, __VA_ARGS__})
   12167 #else
   12168 #define nir_build_image_deref_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12169 _nir_build_image_deref_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, (struct _nir_image_deref_sparse_load_indices){0, __VA_ARGS__})
   12170 #endif
   12171 #define nir_image_deref_sparse_load nir_build_image_deref_sparse_load
   12172 #ifdef __cplusplus
   12173 #define nir_build_image_deref_store(build, src0, src1, src2, src3, src4, ...) \
   12174 _nir_build_image_deref_store(build, src0, src1, src2, src3, src4, _nir_image_deref_store_indices{0, __VA_ARGS__})
   12175 #else
   12176 #define nir_build_image_deref_store(build, src0, src1, src2, src3, src4, ...) \
   12177 _nir_build_image_deref_store(build, src0, src1, src2, src3, src4, (struct _nir_image_deref_store_indices){0, __VA_ARGS__})
   12178 #endif
   12179 #define nir_image_deref_store nir_build_image_deref_store
   12180 #ifdef __cplusplus
   12181 #define nir_build_image_deref_store_raw_intel(build, src0, src1, src2, ...) \
   12182 _nir_build_image_deref_store_raw_intel(build, src0, src1, src2, _nir_image_deref_store_raw_intel_indices{0, __VA_ARGS__})
   12183 #else
   12184 #define nir_build_image_deref_store_raw_intel(build, src0, src1, src2, ...) \
   12185 _nir_build_image_deref_store_raw_intel(build, src0, src1, src2, (struct _nir_image_deref_store_raw_intel_indices){0, __VA_ARGS__})
   12186 #endif
   12187 #define nir_image_deref_store_raw_intel nir_build_image_deref_store_raw_intel
   12188 #ifdef __cplusplus
   12189 #define nir_build_image_format(build, bit_size, src0, ...) \
   12190 _nir_build_image_format(build, bit_size, src0, _nir_image_format_indices{0, __VA_ARGS__})
   12191 #else
   12192 #define nir_build_image_format(build, bit_size, src0, ...) \
   12193 _nir_build_image_format(build, bit_size, src0, (struct _nir_image_format_indices){0, __VA_ARGS__})
   12194 #endif
   12195 #define nir_image_format nir_build_image_format
   12196 #ifdef __cplusplus
   12197 #define nir_build_image_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12198 _nir_build_image_load(build, num_components, bit_size, src0, src1, src2, src3, _nir_image_load_indices{0, __VA_ARGS__})
   12199 #else
   12200 #define nir_build_image_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12201 _nir_build_image_load(build, num_components, bit_size, src0, src1, src2, src3, (struct _nir_image_load_indices){0, __VA_ARGS__})
   12202 #endif
   12203 #define nir_image_load nir_build_image_load
   12204 #ifdef __cplusplus
   12205 #define nir_build_image_load_raw_intel(build, num_components, bit_size, src0, src1, ...) \
   12206 _nir_build_image_load_raw_intel(build, num_components, bit_size, src0, src1, _nir_image_load_raw_intel_indices{0, __VA_ARGS__})
   12207 #else
   12208 #define nir_build_image_load_raw_intel(build, num_components, bit_size, src0, src1, ...) \
   12209 _nir_build_image_load_raw_intel(build, num_components, bit_size, src0, src1, (struct _nir_image_load_raw_intel_indices){0, __VA_ARGS__})
   12210 #endif
   12211 #define nir_image_load_raw_intel nir_build_image_load_raw_intel
   12212 #ifdef __cplusplus
   12213 #define nir_build_image_order(build, bit_size, src0, ...) \
   12214 _nir_build_image_order(build, bit_size, src0, _nir_image_order_indices{0, __VA_ARGS__})
   12215 #else
   12216 #define nir_build_image_order(build, bit_size, src0, ...) \
   12217 _nir_build_image_order(build, bit_size, src0, (struct _nir_image_order_indices){0, __VA_ARGS__})
   12218 #endif
   12219 #define nir_image_order nir_build_image_order
   12220 #ifdef __cplusplus
   12221 #define nir_build_image_samples(build, bit_size, src0, ...) \
   12222 _nir_build_image_samples(build, bit_size, src0, _nir_image_samples_indices{0, __VA_ARGS__})
   12223 #else
   12224 #define nir_build_image_samples(build, bit_size, src0, ...) \
   12225 _nir_build_image_samples(build, bit_size, src0, (struct _nir_image_samples_indices){0, __VA_ARGS__})
   12226 #endif
   12227 #define nir_image_samples nir_build_image_samples
   12228 #ifdef __cplusplus
   12229 #define nir_build_image_size(build, num_components, bit_size, src0, src1, ...) \
   12230 _nir_build_image_size(build, num_components, bit_size, src0, src1, _nir_image_size_indices{0, __VA_ARGS__})
   12231 #else
   12232 #define nir_build_image_size(build, num_components, bit_size, src0, src1, ...) \
   12233 _nir_build_image_size(build, num_components, bit_size, src0, src1, (struct _nir_image_size_indices){0, __VA_ARGS__})
   12234 #endif
   12235 #define nir_image_size nir_build_image_size
   12236 #ifdef __cplusplus
   12237 #define nir_build_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12238 _nir_build_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, _nir_image_sparse_load_indices{0, __VA_ARGS__})
   12239 #else
   12240 #define nir_build_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, ...) \
   12241 _nir_build_image_sparse_load(build, num_components, bit_size, src0, src1, src2, src3, (struct _nir_image_sparse_load_indices){0, __VA_ARGS__})
   12242 #endif
   12243 #define nir_image_sparse_load nir_build_image_sparse_load
   12244 #ifdef __cplusplus
   12245 #define nir_build_image_store(build, src0, src1, src2, src3, src4, ...) \
   12246 _nir_build_image_store(build, src0, src1, src2, src3, src4, _nir_image_store_indices{0, __VA_ARGS__})
   12247 #else
   12248 #define nir_build_image_store(build, src0, src1, src2, src3, src4, ...) \
   12249 _nir_build_image_store(build, src0, src1, src2, src3, src4, (struct _nir_image_store_indices){0, __VA_ARGS__})
   12250 #endif
   12251 #define nir_image_store nir_build_image_store
   12252 #ifdef __cplusplus
   12253 #define nir_build_image_store_raw_intel(build, src0, src1, src2, ...) \
   12254 _nir_build_image_store_raw_intel(build, src0, src1, src2, _nir_image_store_raw_intel_indices{0, __VA_ARGS__})
   12255 #else
   12256 #define nir_build_image_store_raw_intel(build, src0, src1, src2, ...) \
   12257 _nir_build_image_store_raw_intel(build, src0, src1, src2, (struct _nir_image_store_raw_intel_indices){0, __VA_ARGS__})
   12258 #endif
   12259 #define nir_image_store_raw_intel nir_build_image_store_raw_intel
   12260 #ifdef __cplusplus
   12261 #define nir_build_inclusive_scan(build, src0, ...) \
   12262 _nir_build_inclusive_scan(build, src0, _nir_inclusive_scan_indices{0, __VA_ARGS__})
   12263 #else
   12264 #define nir_build_inclusive_scan(build, src0, ...) \
   12265 _nir_build_inclusive_scan(build, src0, (struct _nir_inclusive_scan_indices){0, __VA_ARGS__})
   12266 #endif
   12267 #define nir_inclusive_scan nir_build_inclusive_scan
   12268 #define nir_build_interp_deref_at_centroid _nir_build_interp_deref_at_centroid
   12269 #define nir_interp_deref_at_centroid nir_build_interp_deref_at_centroid
   12270 #define nir_build_interp_deref_at_offset _nir_build_interp_deref_at_offset
   12271 #define nir_interp_deref_at_offset nir_build_interp_deref_at_offset
   12272 #define nir_build_interp_deref_at_sample _nir_build_interp_deref_at_sample
   12273 #define nir_interp_deref_at_sample nir_build_interp_deref_at_sample
   12274 #define nir_build_interp_deref_at_vertex _nir_build_interp_deref_at_vertex
   12275 #define nir_interp_deref_at_vertex nir_build_interp_deref_at_vertex
   12276 #define nir_build_is_helper_invocation _nir_build_is_helper_invocation
   12277 #define nir_is_helper_invocation nir_build_is_helper_invocation
   12278 #define nir_build_is_sparse_texels_resident _nir_build_is_sparse_texels_resident
   12279 #define nir_is_sparse_texels_resident nir_build_is_sparse_texels_resident
   12280 #define nir_build_lane_permute_16_amd _nir_build_lane_permute_16_amd
   12281 #define nir_lane_permute_16_amd nir_build_lane_permute_16_amd
   12282 #define nir_build_last_invocation _nir_build_last_invocation
   12283 #define nir_last_invocation nir_build_last_invocation
   12284 #define nir_build_load_aa_line_width _nir_build_load_aa_line_width
   12285 #define nir_load_aa_line_width nir_build_load_aa_line_width
   12286 #define nir_build_load_back_face_agx _nir_build_load_back_face_agx
   12287 #define nir_load_back_face_agx nir_build_load_back_face_agx
   12288 #ifdef __cplusplus
   12289 #define nir_build_load_barycentric_at_offset(build, bit_size, src0, ...) \
   12290 _nir_build_load_barycentric_at_offset(build, bit_size, src0, _nir_load_barycentric_at_offset_indices{0, __VA_ARGS__})
   12291 #else
   12292 #define nir_build_load_barycentric_at_offset(build, bit_size, src0, ...) \
   12293 _nir_build_load_barycentric_at_offset(build, bit_size, src0, (struct _nir_load_barycentric_at_offset_indices){0, __VA_ARGS__})
   12294 #endif
   12295 #define nir_load_barycentric_at_offset nir_build_load_barycentric_at_offset
   12296 #ifdef __cplusplus
   12297 #define nir_build_load_barycentric_at_sample(build, bit_size, src0, ...) \
   12298 _nir_build_load_barycentric_at_sample(build, bit_size, src0, _nir_load_barycentric_at_sample_indices{0, __VA_ARGS__})
   12299 #else
   12300 #define nir_build_load_barycentric_at_sample(build, bit_size, src0, ...) \
   12301 _nir_build_load_barycentric_at_sample(build, bit_size, src0, (struct _nir_load_barycentric_at_sample_indices){0, __VA_ARGS__})
   12302 #endif
   12303 #define nir_load_barycentric_at_sample nir_build_load_barycentric_at_sample
   12304 #ifdef __cplusplus
   12305 #define nir_build_load_barycentric_centroid(build, bit_size, ...) \
   12306 _nir_build_load_barycentric_centroid(build, bit_size, _nir_load_barycentric_centroid_indices{0, __VA_ARGS__})
   12307 #else
   12308 #define nir_build_load_barycentric_centroid(build, bit_size, ...) \
   12309 _nir_build_load_barycentric_centroid(build, bit_size, (struct _nir_load_barycentric_centroid_indices){0, __VA_ARGS__})
   12310 #endif
   12311 #define nir_load_barycentric_centroid nir_build_load_barycentric_centroid
   12312 #ifdef __cplusplus
   12313 #define nir_build_load_barycentric_model(build, bit_size, ...) \
   12314 _nir_build_load_barycentric_model(build, bit_size, _nir_load_barycentric_model_indices{0, __VA_ARGS__})
   12315 #else
   12316 #define nir_build_load_barycentric_model(build, bit_size, ...) \
   12317 _nir_build_load_barycentric_model(build, bit_size, (struct _nir_load_barycentric_model_indices){0, __VA_ARGS__})
   12318 #endif
   12319 #define nir_load_barycentric_model nir_build_load_barycentric_model
   12320 #ifdef __cplusplus
   12321 #define nir_build_load_barycentric_pixel(build, bit_size, ...) \
   12322 _nir_build_load_barycentric_pixel(build, bit_size, _nir_load_barycentric_pixel_indices{0, __VA_ARGS__})
   12323 #else
   12324 #define nir_build_load_barycentric_pixel(build, bit_size, ...) \
   12325 _nir_build_load_barycentric_pixel(build, bit_size, (struct _nir_load_barycentric_pixel_indices){0, __VA_ARGS__})
   12326 #endif
   12327 #define nir_load_barycentric_pixel nir_build_load_barycentric_pixel
   12328 #ifdef __cplusplus
   12329 #define nir_build_load_barycentric_sample(build, bit_size, ...) \
   12330 _nir_build_load_barycentric_sample(build, bit_size, _nir_load_barycentric_sample_indices{0, __VA_ARGS__})
   12331 #else
   12332 #define nir_build_load_barycentric_sample(build, bit_size, ...) \
   12333 _nir_build_load_barycentric_sample(build, bit_size, (struct _nir_load_barycentric_sample_indices){0, __VA_ARGS__})
   12334 #endif
   12335 #define nir_load_barycentric_sample nir_build_load_barycentric_sample
   12336 #define nir_build_load_base_global_invocation_id _nir_build_load_base_global_invocation_id
   12337 #define nir_load_base_global_invocation_id nir_build_load_base_global_invocation_id
   12338 #define nir_build_load_base_instance _nir_build_load_base_instance
   12339 #define nir_load_base_instance nir_build_load_base_instance
   12340 #define nir_build_load_base_vertex _nir_build_load_base_vertex
   12341 #define nir_load_base_vertex nir_build_load_base_vertex
   12342 #define nir_build_load_base_workgroup_id _nir_build_load_base_workgroup_id
   12343 #define nir_load_base_workgroup_id nir_build_load_base_workgroup_id
   12344 #define nir_build_load_blend_const_color_a_float _nir_build_load_blend_const_color_a_float
   12345 #define nir_load_blend_const_color_a_float nir_build_load_blend_const_color_a_float
   12346 #define nir_build_load_blend_const_color_aaaa8888_unorm _nir_build_load_blend_const_color_aaaa8888_unorm
   12347 #define nir_load_blend_const_color_aaaa8888_unorm nir_build_load_blend_const_color_aaaa8888_unorm
   12348 #define nir_build_load_blend_const_color_b_float _nir_build_load_blend_const_color_b_float
   12349 #define nir_load_blend_const_color_b_float nir_build_load_blend_const_color_b_float
   12350 #define nir_build_load_blend_const_color_g_float _nir_build_load_blend_const_color_g_float
   12351 #define nir_load_blend_const_color_g_float nir_build_load_blend_const_color_g_float
   12352 #define nir_build_load_blend_const_color_r_float _nir_build_load_blend_const_color_r_float
   12353 #define nir_load_blend_const_color_r_float nir_build_load_blend_const_color_r_float
   12354 #define nir_build_load_blend_const_color_rgba _nir_build_load_blend_const_color_rgba
   12355 #define nir_load_blend_const_color_rgba nir_build_load_blend_const_color_rgba
   12356 #define nir_build_load_blend_const_color_rgba8888_unorm _nir_build_load_blend_const_color_rgba8888_unorm
   12357 #define nir_load_blend_const_color_rgba8888_unorm nir_build_load_blend_const_color_rgba8888_unorm
   12358 #define nir_build_load_btd_dss_id_intel _nir_build_load_btd_dss_id_intel
   12359 #define nir_load_btd_dss_id_intel nir_build_load_btd_dss_id_intel
   12360 #define nir_build_load_btd_global_arg_addr_intel _nir_build_load_btd_global_arg_addr_intel
   12361 #define nir_load_btd_global_arg_addr_intel nir_build_load_btd_global_arg_addr_intel
   12362 #define nir_build_load_btd_local_arg_addr_intel _nir_build_load_btd_local_arg_addr_intel
   12363 #define nir_load_btd_local_arg_addr_intel nir_build_load_btd_local_arg_addr_intel
   12364 #define nir_build_load_btd_resume_sbt_addr_intel _nir_build_load_btd_resume_sbt_addr_intel
   12365 #define nir_load_btd_resume_sbt_addr_intel nir_build_load_btd_resume_sbt_addr_intel
   12366 #define nir_build_load_btd_stack_id_intel _nir_build_load_btd_stack_id_intel
   12367 #define nir_load_btd_stack_id_intel nir_build_load_btd_stack_id_intel
   12368 #ifdef __cplusplus
   12369 #define nir_build_load_buffer_amd(build, num_components, bit_size, src0, src1, src2, ...) \
   12370 _nir_build_load_buffer_amd(build, num_components, bit_size, src0, src1, src2, _nir_load_buffer_amd_indices{0, __VA_ARGS__})
   12371 #else
   12372 #define nir_build_load_buffer_amd(build, num_components, bit_size, src0, src1, src2, ...) \
   12373 _nir_build_load_buffer_amd(build, num_components, bit_size, src0, src1, src2, (struct _nir_load_buffer_amd_indices){0, __VA_ARGS__})
   12374 #endif
   12375 #define nir_load_buffer_amd nir_build_load_buffer_amd
   12376 #define nir_build_load_callable_sbt_addr_intel _nir_build_load_callable_sbt_addr_intel
   12377 #define nir_load_callable_sbt_addr_intel nir_build_load_callable_sbt_addr_intel
   12378 #define nir_build_load_callable_sbt_stride_intel _nir_build_load_callable_sbt_stride_intel
   12379 #define nir_load_callable_sbt_stride_intel nir_build_load_callable_sbt_stride_intel
   12380 #define nir_build_load_color0 _nir_build_load_color0
   12381 #define nir_load_color0 nir_build_load_color0
   12382 #define nir_build_load_color1 _nir_build_load_color1
   12383 #define nir_load_color1 nir_build_load_color1
   12384 #ifdef __cplusplus
   12385 #define nir_build_load_constant(build, num_components, bit_size, src0, ...) \
   12386 _nir_build_load_constant(build, num_components, bit_size, src0, _nir_load_constant_indices{0, __VA_ARGS__})
   12387 #else
   12388 #define nir_build_load_constant(build, num_components, bit_size, src0, ...) \
   12389 _nir_build_load_constant(build, num_components, bit_size, src0, (struct _nir_load_constant_indices){0, __VA_ARGS__})
   12390 #endif
   12391 #define nir_load_constant nir_build_load_constant
   12392 #define nir_build_load_constant_base_ptr _nir_build_load_constant_base_ptr
   12393 #define nir_load_constant_base_ptr nir_build_load_constant_base_ptr
   12394 #define nir_build_load_cull_any_enabled_amd _nir_build_load_cull_any_enabled_amd
   12395 #define nir_load_cull_any_enabled_amd nir_build_load_cull_any_enabled_amd
   12396 #define nir_build_load_cull_back_face_enabled_amd _nir_build_load_cull_back_face_enabled_amd
   12397 #define nir_load_cull_back_face_enabled_amd nir_build_load_cull_back_face_enabled_amd
   12398 #define nir_build_load_cull_ccw_amd _nir_build_load_cull_ccw_amd
   12399 #define nir_load_cull_ccw_amd nir_build_load_cull_ccw_amd
   12400 #define nir_build_load_cull_front_face_enabled_amd _nir_build_load_cull_front_face_enabled_amd
   12401 #define nir_load_cull_front_face_enabled_amd nir_build_load_cull_front_face_enabled_amd
   12402 #define nir_build_load_cull_small_prim_precision_amd _nir_build_load_cull_small_prim_precision_amd
   12403 #define nir_load_cull_small_prim_precision_amd nir_build_load_cull_small_prim_precision_amd
   12404 #define nir_build_load_cull_small_primitives_enabled_amd _nir_build_load_cull_small_primitives_enabled_amd
   12405 #define nir_load_cull_small_primitives_enabled_amd nir_build_load_cull_small_primitives_enabled_amd
   12406 #ifdef __cplusplus
   12407 #define nir_build_load_deref(build, num_components, bit_size, src0, ...) \
   12408 _nir_build_load_deref(build, num_components, bit_size, src0, _nir_load_deref_indices{0, __VA_ARGS__})
   12409 #else
   12410 #define nir_build_load_deref(build, num_components, bit_size, src0, ...) \
   12411 _nir_build_load_deref(build, num_components, bit_size, src0, (struct _nir_load_deref_indices){0, __VA_ARGS__})
   12412 #endif
   12413 #define nir_load_deref nir_build_load_deref
   12414 #ifdef __cplusplus
   12415 #define nir_build_load_deref_block_intel(build, num_components, bit_size, src0, ...) \
   12416 _nir_build_load_deref_block_intel(build, num_components, bit_size, src0, _nir_load_deref_block_intel_indices{0, __VA_ARGS__})
   12417 #else
   12418 #define nir_build_load_deref_block_intel(build, num_components, bit_size, src0, ...) \
   12419 _nir_build_load_deref_block_intel(build, num_components, bit_size, src0, (struct _nir_load_deref_block_intel_indices){0, __VA_ARGS__})
   12420 #endif
   12421 #define nir_load_deref_block_intel nir_build_load_deref_block_intel
   12422 #define nir_build_load_desc_set_address_intel _nir_build_load_desc_set_address_intel
   12423 #define nir_load_desc_set_address_intel nir_build_load_desc_set_address_intel
   12424 #define nir_build_load_draw_id _nir_build_load_draw_id
   12425 #define nir_load_draw_id nir_build_load_draw_id
   12426 #define nir_build_load_fb_layers_v3d _nir_build_load_fb_layers_v3d
   12427 #define nir_load_fb_layers_v3d nir_build_load_fb_layers_v3d
   12428 #define nir_build_load_first_vertex _nir_build_load_first_vertex
   12429 #define nir_load_first_vertex nir_build_load_first_vertex
   12430 #define nir_build_load_frag_coord _nir_build_load_frag_coord
   12431 #define nir_load_frag_coord nir_build_load_frag_coord
   12432 #define nir_build_load_frag_shading_rate _nir_build_load_frag_shading_rate
   12433 #define nir_load_frag_shading_rate nir_build_load_frag_shading_rate
   12434 #define nir_build_load_front_face _nir_build_load_front_face
   12435 #define nir_load_front_face nir_build_load_front_face
   12436 #ifdef __cplusplus
   12437 #define nir_build_load_fs_input_interp_deltas(build, bit_size, src0, ...) \
   12438 _nir_build_load_fs_input_interp_deltas(build, bit_size, src0, _nir_load_fs_input_interp_deltas_indices{0, __VA_ARGS__})
   12439 #else
   12440 #define nir_build_load_fs_input_interp_deltas(build, bit_size, src0, ...) \
   12441 _nir_build_load_fs_input_interp_deltas(build, bit_size, src0, (struct _nir_load_fs_input_interp_deltas_indices){0, __VA_ARGS__})
   12442 #endif
   12443 #define nir_load_fs_input_interp_deltas nir_build_load_fs_input_interp_deltas
   12444 #ifdef __cplusplus
   12445 #define nir_build_load_global(build, num_components, bit_size, src0, ...) \
   12446 _nir_build_load_global(build, num_components, bit_size, src0, _nir_load_global_indices{0, __VA_ARGS__})
   12447 #else
   12448 #define nir_build_load_global(build, num_components, bit_size, src0, ...) \
   12449 _nir_build_load_global(build, num_components, bit_size, src0, (struct _nir_load_global_indices){0, __VA_ARGS__})
   12450 #endif
   12451 #define nir_load_global nir_build_load_global
   12452 #ifdef __cplusplus
   12453 #define nir_build_load_global_block_intel(build, num_components, bit_size, src0, ...) \
   12454 _nir_build_load_global_block_intel(build, num_components, bit_size, src0, _nir_load_global_block_intel_indices{0, __VA_ARGS__})
   12455 #else
   12456 #define nir_build_load_global_block_intel(build, num_components, bit_size, src0, ...) \
   12457 _nir_build_load_global_block_intel(build, num_components, bit_size, src0, (struct _nir_load_global_block_intel_indices){0, __VA_ARGS__})
   12458 #endif
   12459 #define nir_load_global_block_intel nir_build_load_global_block_intel
   12460 #ifdef __cplusplus
   12461 #define nir_build_load_global_const_block_intel(build, num_components, src0, src1, ...) \
   12462 _nir_build_load_global_const_block_intel(build, num_components, src0, src1, _nir_load_global_const_block_intel_indices{0, __VA_ARGS__})
   12463 #else
   12464 #define nir_build_load_global_const_block_intel(build, num_components, src0, src1, ...) \
   12465 _nir_build_load_global_const_block_intel(build, num_components, src0, src1, (struct _nir_load_global_const_block_intel_indices){0, __VA_ARGS__})
   12466 #endif
   12467 #define nir_load_global_const_block_intel nir_build_load_global_const_block_intel
   12468 #ifdef __cplusplus
   12469 #define nir_build_load_global_constant(build, num_components, bit_size, src0, ...) \
   12470 _nir_build_load_global_constant(build, num_components, bit_size, src0, _nir_load_global_constant_indices{0, __VA_ARGS__})
   12471 #else
   12472 #define nir_build_load_global_constant(build, num_components, bit_size, src0, ...) \
   12473 _nir_build_load_global_constant(build, num_components, bit_size, src0, (struct _nir_load_global_constant_indices){0, __VA_ARGS__})
   12474 #endif
   12475 #define nir_load_global_constant nir_build_load_global_constant
   12476 #ifdef __cplusplus
   12477 #define nir_build_load_global_constant_bounded(build, num_components, bit_size, src0, src1, src2, ...) \
   12478 _nir_build_load_global_constant_bounded(build, num_components, bit_size, src0, src1, src2, _nir_load_global_constant_bounded_indices{0, __VA_ARGS__})
   12479 #else
   12480 #define nir_build_load_global_constant_bounded(build, num_components, bit_size, src0, src1, src2, ...) \
   12481 _nir_build_load_global_constant_bounded(build, num_components, bit_size, src0, src1, src2, (struct _nir_load_global_constant_bounded_indices){0, __VA_ARGS__})
   12482 #endif
   12483 #define nir_load_global_constant_bounded nir_build_load_global_constant_bounded
   12484 #ifdef __cplusplus
   12485 #define nir_build_load_global_constant_offset(build, num_components, bit_size, src0, src1, ...) \
   12486 _nir_build_load_global_constant_offset(build, num_components, bit_size, src0, src1, _nir_load_global_constant_offset_indices{0, __VA_ARGS__})
   12487 #else
   12488 #define nir_build_load_global_constant_offset(build, num_components, bit_size, src0, src1, ...) \
   12489 _nir_build_load_global_constant_offset(build, num_components, bit_size, src0, src1, (struct _nir_load_global_constant_offset_indices){0, __VA_ARGS__})
   12490 #endif
   12491 #define nir_load_global_constant_offset nir_build_load_global_constant_offset
   12492 #define nir_build_load_global_invocation_id _nir_build_load_global_invocation_id
   12493 #define nir_load_global_invocation_id nir_build_load_global_invocation_id
   12494 #define nir_build_load_global_invocation_id_zero_base _nir_build_load_global_invocation_id_zero_base
   12495 #define nir_load_global_invocation_id_zero_base nir_build_load_global_invocation_id_zero_base
   12496 #define nir_build_load_global_invocation_index _nir_build_load_global_invocation_index
   12497 #define nir_load_global_invocation_index nir_build_load_global_invocation_index
   12498 #ifdef __cplusplus
   12499 #define nir_build_load_global_ir3(build, num_components, bit_size, src0, src1, ...) \
   12500 _nir_build_load_global_ir3(build, num_components, bit_size, src0, src1, _nir_load_global_ir3_indices{0, __VA_ARGS__})
   12501 #else
   12502 #define nir_build_load_global_ir3(build, num_components, bit_size, src0, src1, ...) \
   12503 _nir_build_load_global_ir3(build, num_components, bit_size, src0, src1, (struct _nir_load_global_ir3_indices){0, __VA_ARGS__})
   12504 #endif
   12505 #define nir_load_global_ir3 nir_build_load_global_ir3
   12506 #define nir_build_load_gs_header_ir3 _nir_build_load_gs_header_ir3
   12507 #define nir_load_gs_header_ir3 nir_build_load_gs_header_ir3
   12508 #ifdef __cplusplus
   12509 #define nir_build_load_gs_vertex_offset_amd(build, ...) \
   12510 _nir_build_load_gs_vertex_offset_amd(build, _nir_load_gs_vertex_offset_amd_indices{0, __VA_ARGS__})
   12511 #else
   12512 #define nir_build_load_gs_vertex_offset_amd(build, ...) \
   12513 _nir_build_load_gs_vertex_offset_amd(build, (struct _nir_load_gs_vertex_offset_amd_indices){0, __VA_ARGS__})
   12514 #endif
   12515 #define nir_load_gs_vertex_offset_amd nir_build_load_gs_vertex_offset_amd
   12516 #define nir_build_load_helper_invocation _nir_build_load_helper_invocation
   12517 #define nir_load_helper_invocation nir_build_load_helper_invocation
   12518 #define nir_build_load_hs_patch_stride_ir3 _nir_build_load_hs_patch_stride_ir3
   12519 #define nir_load_hs_patch_stride_ir3 nir_build_load_hs_patch_stride_ir3
   12520 #define nir_build_load_initial_edgeflags_amd _nir_build_load_initial_edgeflags_amd
   12521 #define nir_load_initial_edgeflags_amd nir_build_load_initial_edgeflags_amd
   12522 #ifdef __cplusplus
   12523 #define nir_build_load_input(build, num_components, bit_size, src0, ...) \
   12524 _nir_build_load_input(build, num_components, bit_size, src0, _nir_load_input_indices{0, __VA_ARGS__})
   12525 #else
   12526 #define nir_build_load_input(build, num_components, bit_size, src0, ...) \
   12527 _nir_build_load_input(build, num_components, bit_size, src0, (struct _nir_load_input_indices){0, __VA_ARGS__})
   12528 #endif
   12529 #define nir_load_input nir_build_load_input
   12530 #ifdef __cplusplus
   12531 #define nir_build_load_input_vertex(build, num_components, bit_size, src0, src1, ...) \
   12532 _nir_build_load_input_vertex(build, num_components, bit_size, src0, src1, _nir_load_input_vertex_indices{0, __VA_ARGS__})
   12533 #else
   12534 #define nir_build_load_input_vertex(build, num_components, bit_size, src0, src1, ...) \
   12535 _nir_build_load_input_vertex(build, num_components, bit_size, src0, src1, (struct _nir_load_input_vertex_indices){0, __VA_ARGS__})
   12536 #endif
   12537 #define nir_load_input_vertex nir_build_load_input_vertex
   12538 #define nir_build_load_instance_id _nir_build_load_instance_id
   12539 #define nir_load_instance_id nir_build_load_instance_id
   12540 #ifdef __cplusplus
   12541 #define nir_build_load_interpolated_input(build, num_components, bit_size, src0, src1, ...) \
   12542 _nir_build_load_interpolated_input(build, num_components, bit_size, src0, src1, _nir_load_interpolated_input_indices{0, __VA_ARGS__})
   12543 #else
   12544 #define nir_build_load_interpolated_input(build, num_components, bit_size, src0, src1, ...) \
   12545 _nir_build_load_interpolated_input(build, num_components, bit_size, src0, src1, (struct _nir_load_interpolated_input_indices){0, __VA_ARGS__})
   12546 #endif
   12547 #define nir_load_interpolated_input nir_build_load_interpolated_input
   12548 #define nir_build_load_intersection_opaque_amd _nir_build_load_intersection_opaque_amd
   12549 #define nir_load_intersection_opaque_amd nir_build_load_intersection_opaque_amd
   12550 #define nir_build_load_invocation_id _nir_build_load_invocation_id
   12551 #define nir_load_invocation_id nir_build_load_invocation_id
   12552 #define nir_build_load_is_indexed_draw _nir_build_load_is_indexed_draw
   12553 #define nir_load_is_indexed_draw nir_build_load_is_indexed_draw
   12554 #ifdef __cplusplus
   12555 #define nir_build_load_kernel_input(build, num_components, bit_size, src0, ...) \
   12556 _nir_build_load_kernel_input(build, num_components, bit_size, src0, _nir_load_kernel_input_indices{0, __VA_ARGS__})
   12557 #else
   12558 #define nir_build_load_kernel_input(build, num_components, bit_size, src0, ...) \
   12559 _nir_build_load_kernel_input(build, num_components, bit_size, src0, (struct _nir_load_kernel_input_indices){0, __VA_ARGS__})
   12560 #endif
   12561 #define nir_load_kernel_input nir_build_load_kernel_input
   12562 #define nir_build_load_layer_id _nir_build_load_layer_id
   12563 #define nir_load_layer_id nir_build_load_layer_id
   12564 #define nir_build_load_leaf_opaque_intel _nir_build_load_leaf_opaque_intel
   12565 #define nir_load_leaf_opaque_intel nir_build_load_leaf_opaque_intel
   12566 #define nir_build_load_leaf_procedural_intel _nir_build_load_leaf_procedural_intel
   12567 #define nir_load_leaf_procedural_intel nir_build_load_leaf_procedural_intel
   12568 #define nir_build_load_line_coord _nir_build_load_line_coord
   12569 #define nir_load_line_coord nir_build_load_line_coord
   12570 #define nir_build_load_line_width _nir_build_load_line_width
   12571 #define nir_load_line_width nir_build_load_line_width
   12572 #define nir_build_load_local_invocation_id _nir_build_load_local_invocation_id
   12573 #define nir_load_local_invocation_id nir_build_load_local_invocation_id
   12574 #define nir_build_load_local_invocation_index _nir_build_load_local_invocation_index
   12575 #define nir_load_local_invocation_index nir_build_load_local_invocation_index
   12576 #define nir_build_load_local_shared_r600 _nir_build_load_local_shared_r600
   12577 #define nir_load_local_shared_r600 nir_build_load_local_shared_r600
   12578 #define nir_build_load_num_subgroups _nir_build_load_num_subgroups
   12579 #define nir_load_num_subgroups nir_build_load_num_subgroups
   12580 #define nir_build_load_num_workgroups _nir_build_load_num_workgroups
   12581 #define nir_load_num_workgroups nir_build_load_num_workgroups
   12582 #ifdef __cplusplus
   12583 #define nir_build_load_output(build, num_components, bit_size, src0, ...) \
   12584 _nir_build_load_output(build, num_components, bit_size, src0, _nir_load_output_indices{0, __VA_ARGS__})
   12585 #else
   12586 #define nir_build_load_output(build, num_components, bit_size, src0, ...) \
   12587 _nir_build_load_output(build, num_components, bit_size, src0, (struct _nir_load_output_indices){0, __VA_ARGS__})
   12588 #endif
   12589 #define nir_load_output nir_build_load_output
   12590 #define nir_build_load_packed_passthrough_primitive_amd _nir_build_load_packed_passthrough_primitive_amd
   12591 #define nir_load_packed_passthrough_primitive_amd nir_build_load_packed_passthrough_primitive_amd
   12592 #ifdef __cplusplus
   12593 #define nir_build_load_param(build, num_components, bit_size, ...) \
   12594 _nir_build_load_param(build, num_components, bit_size, _nir_load_param_indices{0, __VA_ARGS__})
   12595 #else
   12596 #define nir_build_load_param(build, num_components, bit_size, ...) \
   12597 _nir_build_load_param(build, num_components, bit_size, (struct _nir_load_param_indices){0, __VA_ARGS__})
   12598 #endif
   12599 #define nir_load_param nir_build_load_param
   12600 #define nir_build_load_patch_vertices_in _nir_build_load_patch_vertices_in
   12601 #define nir_load_patch_vertices_in nir_build_load_patch_vertices_in
   12602 #ifdef __cplusplus
   12603 #define nir_build_load_per_primitive_output(build, num_components, bit_size, src0, src1, ...) \
   12604 _nir_build_load_per_primitive_output(build, num_components, bit_size, src0, src1, _nir_load_per_primitive_output_indices{0, __VA_ARGS__})
   12605 #else
   12606 #define nir_build_load_per_primitive_output(build, num_components, bit_size, src0, src1, ...) \
   12607 _nir_build_load_per_primitive_output(build, num_components, bit_size, src0, src1, (struct _nir_load_per_primitive_output_indices){0, __VA_ARGS__})
   12608 #endif
   12609 #define nir_load_per_primitive_output nir_build_load_per_primitive_output
   12610 #ifdef __cplusplus
   12611 #define nir_build_load_per_vertex_input(build, num_components, bit_size, src0, src1, ...) \
   12612 _nir_build_load_per_vertex_input(build, num_components, bit_size, src0, src1, _nir_load_per_vertex_input_indices{0, __VA_ARGS__})
   12613 #else
   12614 #define nir_build_load_per_vertex_input(build, num_components, bit_size, src0, src1, ...) \
   12615 _nir_build_load_per_vertex_input(build, num_components, bit_size, src0, src1, (struct _nir_load_per_vertex_input_indices){0, __VA_ARGS__})
   12616 #endif
   12617 #define nir_load_per_vertex_input nir_build_load_per_vertex_input
   12618 #ifdef __cplusplus
   12619 #define nir_build_load_per_vertex_output(build, num_components, bit_size, src0, src1, ...) \
   12620 _nir_build_load_per_vertex_output(build, num_components, bit_size, src0, src1, _nir_load_per_vertex_output_indices{0, __VA_ARGS__})
   12621 #else
   12622 #define nir_build_load_per_vertex_output(build, num_components, bit_size, src0, src1, ...) \
   12623 _nir_build_load_per_vertex_output(build, num_components, bit_size, src0, src1, (struct _nir_load_per_vertex_output_indices){0, __VA_ARGS__})
   12624 #endif
   12625 #define nir_load_per_vertex_output nir_build_load_per_vertex_output
   12626 #define nir_build_load_point_coord _nir_build_load_point_coord
   12627 #define nir_load_point_coord nir_build_load_point_coord
   12628 #define nir_build_load_primitive_id _nir_build_load_primitive_id
   12629 #define nir_load_primitive_id nir_build_load_primitive_id
   12630 #ifdef __cplusplus
   12631 #define nir_build_load_primitive_location_ir3(build, ...) \
   12632 _nir_build_load_primitive_location_ir3(build, _nir_load_primitive_location_ir3_indices{0, __VA_ARGS__})
   12633 #else
   12634 #define nir_build_load_primitive_location_ir3(build, ...) \
   12635 _nir_build_load_primitive_location_ir3(build, (struct _nir_load_primitive_location_ir3_indices){0, __VA_ARGS__})
   12636 #endif
   12637 #define nir_load_primitive_location_ir3 nir_build_load_primitive_location_ir3
   12638 #define nir_build_load_printf_buffer_address _nir_build_load_printf_buffer_address
   12639 #define nir_load_printf_buffer_address nir_build_load_printf_buffer_address
   12640 #define nir_build_load_ptr_dxil _nir_build_load_ptr_dxil
   12641 #define nir_load_ptr_dxil nir_build_load_ptr_dxil
   12642 #ifdef __cplusplus
   12643 #define nir_build_load_push_constant(build, num_components, bit_size, src0, ...) \
   12644 _nir_build_load_push_constant(build, num_components, bit_size, src0, _nir_load_push_constant_indices{0, __VA_ARGS__})
   12645 #else
   12646 #define nir_build_load_push_constant(build, num_components, bit_size, src0, ...) \
   12647 _nir_build_load_push_constant(build, num_components, bit_size, src0, (struct _nir_load_push_constant_indices){0, __VA_ARGS__})
   12648 #endif
   12649 #define nir_load_push_constant nir_build_load_push_constant
   12650 #ifdef __cplusplus
   12651 #define nir_build_load_raw_output_pan(build, num_components, bit_size, src0, ...) \
   12652 _nir_build_load_raw_output_pan(build, num_components, bit_size, src0, _nir_load_raw_output_pan_indices{0, __VA_ARGS__})
   12653 #else
   12654 #define nir_build_load_raw_output_pan(build, num_components, bit_size, src0, ...) \
   12655 _nir_build_load_raw_output_pan(build, num_components, bit_size, src0, (struct _nir_load_raw_output_pan_indices){0, __VA_ARGS__})
   12656 #endif
   12657 #define nir_load_raw_output_pan nir_build_load_raw_output_pan
   12658 #define nir_build_load_ray_base_mem_addr_intel _nir_build_load_ray_base_mem_addr_intel
   12659 #define nir_load_ray_base_mem_addr_intel nir_build_load_ray_base_mem_addr_intel
   12660 #define nir_build_load_ray_flags _nir_build_load_ray_flags
   12661 #define nir_load_ray_flags nir_build_load_ray_flags
   12662 #define nir_build_load_ray_geometry_index _nir_build_load_ray_geometry_index
   12663 #define nir_load_ray_geometry_index nir_build_load_ray_geometry_index
   12664 #define nir_build_load_ray_hit_kind _nir_build_load_ray_hit_kind
   12665 #define nir_load_ray_hit_kind nir_build_load_ray_hit_kind
   12666 #define nir_build_load_ray_hit_sbt_addr_intel _nir_build_load_ray_hit_sbt_addr_intel
   12667 #define nir_load_ray_hit_sbt_addr_intel nir_build_load_ray_hit_sbt_addr_intel
   12668 #define nir_build_load_ray_hit_sbt_stride_intel _nir_build_load_ray_hit_sbt_stride_intel
   12669 #define nir_load_ray_hit_sbt_stride_intel nir_build_load_ray_hit_sbt_stride_intel
   12670 #define nir_build_load_ray_hw_stack_size_intel _nir_build_load_ray_hw_stack_size_intel
   12671 #define nir_load_ray_hw_stack_size_intel nir_build_load_ray_hw_stack_size_intel
   12672 #define nir_build_load_ray_instance_custom_index _nir_build_load_ray_instance_custom_index
   12673 #define nir_load_ray_instance_custom_index nir_build_load_ray_instance_custom_index
   12674 #define nir_build_load_ray_launch_id _nir_build_load_ray_launch_id
   12675 #define nir_load_ray_launch_id nir_build_load_ray_launch_id
   12676 #define nir_build_load_ray_launch_size _nir_build_load_ray_launch_size
   12677 #define nir_load_ray_launch_size nir_build_load_ray_launch_size
   12678 #define nir_build_load_ray_miss_sbt_addr_intel _nir_build_load_ray_miss_sbt_addr_intel
   12679 #define nir_load_ray_miss_sbt_addr_intel nir_build_load_ray_miss_sbt_addr_intel
   12680 #define nir_build_load_ray_miss_sbt_stride_intel _nir_build_load_ray_miss_sbt_stride_intel
   12681 #define nir_load_ray_miss_sbt_stride_intel nir_build_load_ray_miss_sbt_stride_intel
   12682 #define nir_build_load_ray_num_dss_rt_stacks_intel _nir_build_load_ray_num_dss_rt_stacks_intel
   12683 #define nir_load_ray_num_dss_rt_stacks_intel nir_build_load_ray_num_dss_rt_stacks_intel
   12684 #define nir_build_load_ray_object_direction _nir_build_load_ray_object_direction
   12685 #define nir_load_ray_object_direction nir_build_load_ray_object_direction
   12686 #define nir_build_load_ray_object_origin _nir_build_load_ray_object_origin
   12687 #define nir_load_ray_object_origin nir_build_load_ray_object_origin
   12688 #ifdef __cplusplus
   12689 #define nir_build_load_ray_object_to_world(build, ...) \
   12690 _nir_build_load_ray_object_to_world(build, _nir_load_ray_object_to_world_indices{0, __VA_ARGS__})
   12691 #else
   12692 #define nir_build_load_ray_object_to_world(build, ...) \
   12693 _nir_build_load_ray_object_to_world(build, (struct _nir_load_ray_object_to_world_indices){0, __VA_ARGS__})
   12694 #endif
   12695 #define nir_load_ray_object_to_world nir_build_load_ray_object_to_world
   12696 #define nir_build_load_ray_sw_stack_size_intel _nir_build_load_ray_sw_stack_size_intel
   12697 #define nir_load_ray_sw_stack_size_intel nir_build_load_ray_sw_stack_size_intel
   12698 #define nir_build_load_ray_t_max _nir_build_load_ray_t_max
   12699 #define nir_load_ray_t_max nir_build_load_ray_t_max
   12700 #define nir_build_load_ray_t_min _nir_build_load_ray_t_min
   12701 #define nir_load_ray_t_min nir_build_load_ray_t_min
   12702 #define nir_build_load_ray_world_direction _nir_build_load_ray_world_direction
   12703 #define nir_load_ray_world_direction nir_build_load_ray_world_direction
   12704 #define nir_build_load_ray_world_origin _nir_build_load_ray_world_origin
   12705 #define nir_load_ray_world_origin nir_build_load_ray_world_origin
   12706 #ifdef __cplusplus
   12707 #define nir_build_load_ray_world_to_object(build, ...) \
   12708 _nir_build_load_ray_world_to_object(build, _nir_load_ray_world_to_object_indices{0, __VA_ARGS__})
   12709 #else
   12710 #define nir_build_load_ray_world_to_object(build, ...) \
   12711 _nir_build_load_ray_world_to_object(build, (struct _nir_load_ray_world_to_object_indices){0, __VA_ARGS__})
   12712 #endif
   12713 #define nir_load_ray_world_to_object nir_build_load_ray_world_to_object
   12714 #define nir_build_load_rel_patch_id_ir3 _nir_build_load_rel_patch_id_ir3
   12715 #define nir_load_rel_patch_id_ir3 nir_build_load_rel_patch_id_ir3
   12716 #ifdef __cplusplus
   12717 #define nir_build_load_reloc_const_intel(build, ...) \
   12718 _nir_build_load_reloc_const_intel(build, _nir_load_reloc_const_intel_indices{0, __VA_ARGS__})
   12719 #else
   12720 #define nir_build_load_reloc_const_intel(build, ...) \
   12721 _nir_build_load_reloc_const_intel(build, (struct _nir_load_reloc_const_intel_indices){0, __VA_ARGS__})
   12722 #endif
   12723 #define nir_load_reloc_const_intel nir_build_load_reloc_const_intel
   12724 #define nir_build_load_ring_es2gs_offset_amd _nir_build_load_ring_es2gs_offset_amd
   12725 #define nir_load_ring_es2gs_offset_amd nir_build_load_ring_es2gs_offset_amd
   12726 #define nir_build_load_ring_esgs_amd _nir_build_load_ring_esgs_amd
   12727 #define nir_load_ring_esgs_amd nir_build_load_ring_esgs_amd
   12728 #define nir_build_load_ring_tess_factors_amd _nir_build_load_ring_tess_factors_amd
   12729 #define nir_load_ring_tess_factors_amd nir_build_load_ring_tess_factors_amd
   12730 #define nir_build_load_ring_tess_factors_offset_amd _nir_build_load_ring_tess_factors_offset_amd
   12731 #define nir_load_ring_tess_factors_offset_amd nir_build_load_ring_tess_factors_offset_amd
   12732 #define nir_build_load_ring_tess_offchip_amd _nir_build_load_ring_tess_offchip_amd
   12733 #define nir_load_ring_tess_offchip_amd nir_build_load_ring_tess_offchip_amd
   12734 #define nir_build_load_ring_tess_offchip_offset_amd _nir_build_load_ring_tess_offchip_offset_amd
   12735 #define nir_load_ring_tess_offchip_offset_amd nir_build_load_ring_tess_offchip_offset_amd
   12736 #define nir_build_load_rt_arg_scratch_offset_amd _nir_build_load_rt_arg_scratch_offset_amd
   12737 #define nir_load_rt_arg_scratch_offset_amd nir_build_load_rt_arg_scratch_offset_amd
   12738 #define nir_build_load_sample_id _nir_build_load_sample_id
   12739 #define nir_load_sample_id nir_build_load_sample_id
   12740 #define nir_build_load_sample_id_no_per_sample _nir_build_load_sample_id_no_per_sample
   12741 #define nir_load_sample_id_no_per_sample nir_build_load_sample_id_no_per_sample
   12742 #define nir_build_load_sample_mask_in _nir_build_load_sample_mask_in
   12743 #define nir_load_sample_mask_in nir_build_load_sample_mask_in
   12744 #define nir_build_load_sample_pos _nir_build_load_sample_pos
   12745 #define nir_load_sample_pos nir_build_load_sample_pos
   12746 #define nir_build_load_sample_pos_from_id _nir_build_load_sample_pos_from_id
   12747 #define nir_load_sample_pos_from_id nir_build_load_sample_pos_from_id
   12748 #define nir_build_load_sample_positions_pan _nir_build_load_sample_positions_pan
   12749 #define nir_load_sample_positions_pan nir_build_load_sample_positions_pan
   12750 #define nir_build_load_sampler_lod_parameters_pan _nir_build_load_sampler_lod_parameters_pan
   12751 #define nir_load_sampler_lod_parameters_pan nir_build_load_sampler_lod_parameters_pan
   12752 #ifdef __cplusplus
   12753 #define nir_build_load_sbt_amd(build, ...) \
   12754 _nir_build_load_sbt_amd(build, _nir_load_sbt_amd_indices{0, __VA_ARGS__})
   12755 #else
   12756 #define nir_build_load_sbt_amd(build, ...) \
   12757 _nir_build_load_sbt_amd(build, (struct _nir_load_sbt_amd_indices){0, __VA_ARGS__})
   12758 #endif
   12759 #define nir_load_sbt_amd nir_build_load_sbt_amd
   12760 #ifdef __cplusplus
   12761 #define nir_build_load_scratch(build, num_components, bit_size, src0, ...) \
   12762 _nir_build_load_scratch(build, num_components, bit_size, src0, _nir_load_scratch_indices{0, __VA_ARGS__})
   12763 #else
   12764 #define nir_build_load_scratch(build, num_components, bit_size, src0, ...) \
   12765 _nir_build_load_scratch(build, num_components, bit_size, src0, (struct _nir_load_scratch_indices){0, __VA_ARGS__})
   12766 #endif
   12767 #define nir_load_scratch nir_build_load_scratch
   12768 #ifdef __cplusplus
   12769 #define nir_build_load_scratch_base_ptr(build, num_components, bit_size, ...) \
   12770 _nir_build_load_scratch_base_ptr(build, num_components, bit_size, _nir_load_scratch_base_ptr_indices{0, __VA_ARGS__})
   12771 #else
   12772 #define nir_build_load_scratch_base_ptr(build, num_components, bit_size, ...) \
   12773 _nir_build_load_scratch_base_ptr(build, num_components, bit_size, (struct _nir_load_scratch_base_ptr_indices){0, __VA_ARGS__})
   12774 #endif
   12775 #define nir_load_scratch_base_ptr nir_build_load_scratch_base_ptr
   12776 #define nir_build_load_scratch_dxil _nir_build_load_scratch_dxil
   12777 #define nir_load_scratch_dxil nir_build_load_scratch_dxil
   12778 #define nir_build_load_shader_query_enabled_amd _nir_build_load_shader_query_enabled_amd
   12779 #define nir_load_shader_query_enabled_amd nir_build_load_shader_query_enabled_amd
   12780 #define nir_build_load_shader_record_ptr _nir_build_load_shader_record_ptr
   12781 #define nir_load_shader_record_ptr nir_build_load_shader_record_ptr
   12782 #ifdef __cplusplus
   12783 #define nir_build_load_shared(build, num_components, bit_size, src0, ...) \
   12784 _nir_build_load_shared(build, num_components, bit_size, src0, _nir_load_shared_indices{0, __VA_ARGS__})
   12785 #else
   12786 #define nir_build_load_shared(build, num_components, bit_size, src0, ...) \
   12787 _nir_build_load_shared(build, num_components, bit_size, src0, (struct _nir_load_shared_indices){0, __VA_ARGS__})
   12788 #endif
   12789 #define nir_load_shared nir_build_load_shared
   12790 #define nir_build_load_shared_base_ptr _nir_build_load_shared_base_ptr
   12791 #define nir_load_shared_base_ptr nir_build_load_shared_base_ptr
   12792 #ifdef __cplusplus
   12793 #define nir_build_load_shared_block_intel(build, num_components, bit_size, src0, ...) \
   12794 _nir_build_load_shared_block_intel(build, num_components, bit_size, src0, _nir_load_shared_block_intel_indices{0, __VA_ARGS__})
   12795 #else
   12796 #define nir_build_load_shared_block_intel(build, num_components, bit_size, src0, ...) \
   12797 _nir_build_load_shared_block_intel(build, num_components, bit_size, src0, (struct _nir_load_shared_block_intel_indices){0, __VA_ARGS__})
   12798 #endif
   12799 #define nir_load_shared_block_intel nir_build_load_shared_block_intel
   12800 #define nir_build_load_shared_dxil _nir_build_load_shared_dxil
   12801 #define nir_load_shared_dxil nir_build_load_shared_dxil
   12802 #ifdef __cplusplus
   12803 #define nir_build_load_shared_ir3(build, num_components, bit_size, src0, ...) \
   12804 _nir_build_load_shared_ir3(build, num_components, bit_size, src0, _nir_load_shared_ir3_indices{0, __VA_ARGS__})
   12805 #else
   12806 #define nir_build_load_shared_ir3(build, num_components, bit_size, src0, ...) \
   12807 _nir_build_load_shared_ir3(build, num_components, bit_size, src0, (struct _nir_load_shared_ir3_indices){0, __VA_ARGS__})
   12808 #endif
   12809 #define nir_load_shared_ir3 nir_build_load_shared_ir3
   12810 #define nir_build_load_simd_width_intel _nir_build_load_simd_width_intel
   12811 #define nir_load_simd_width_intel nir_build_load_simd_width_intel
   12812 #define nir_build_load_size_ir3 _nir_build_load_size_ir3
   12813 #define nir_load_size_ir3 nir_build_load_size_ir3
   12814 #ifdef __cplusplus
   12815 #define nir_build_load_ssbo(build, num_components, bit_size, src0, src1, ...) \
   12816 _nir_build_load_ssbo(build, num_components, bit_size, src0, src1, _nir_load_ssbo_indices{0, __VA_ARGS__})
   12817 #else
   12818 #define nir_build_load_ssbo(build, num_components, bit_size, src0, src1, ...) \
   12819 _nir_build_load_ssbo(build, num_components, bit_size, src0, src1, (struct _nir_load_ssbo_indices){0, __VA_ARGS__})
   12820 #endif
   12821 #define nir_load_ssbo nir_build_load_ssbo
   12822 #define nir_build_load_ssbo_address _nir_build_load_ssbo_address
   12823 #define nir_load_ssbo_address nir_build_load_ssbo_address
   12824 #ifdef __cplusplus
   12825 #define nir_build_load_ssbo_block_intel(build, num_components, bit_size, src0, src1, ...) \
   12826 _nir_build_load_ssbo_block_intel(build, num_components, bit_size, src0, src1, _nir_load_ssbo_block_intel_indices{0, __VA_ARGS__})
   12827 #else
   12828 #define nir_build_load_ssbo_block_intel(build, num_components, bit_size, src0, src1, ...) \
   12829 _nir_build_load_ssbo_block_intel(build, num_components, bit_size, src0, src1, (struct _nir_load_ssbo_block_intel_indices){0, __VA_ARGS__})
   12830 #endif
   12831 #define nir_load_ssbo_block_intel nir_build_load_ssbo_block_intel
   12832 #ifdef __cplusplus
   12833 #define nir_build_load_ssbo_ir3(build, num_components, bit_size, src0, src1, src2, ...) \
   12834 _nir_build_load_ssbo_ir3(build, num_components, bit_size, src0, src1, src2, _nir_load_ssbo_ir3_indices{0, __VA_ARGS__})
   12835 #else
   12836 #define nir_build_load_ssbo_ir3(build, num_components, bit_size, src0, src1, src2, ...) \
   12837 _nir_build_load_ssbo_ir3(build, num_components, bit_size, src0, src1, src2, (struct _nir_load_ssbo_ir3_indices){0, __VA_ARGS__})
   12838 #endif
   12839 #define nir_load_ssbo_ir3 nir_build_load_ssbo_ir3
   12840 #define nir_build_load_subgroup_eq_mask _nir_build_load_subgroup_eq_mask
   12841 #define nir_load_subgroup_eq_mask nir_build_load_subgroup_eq_mask
   12842 #define nir_build_load_subgroup_ge_mask _nir_build_load_subgroup_ge_mask
   12843 #define nir_load_subgroup_ge_mask nir_build_load_subgroup_ge_mask
   12844 #define nir_build_load_subgroup_gt_mask _nir_build_load_subgroup_gt_mask
   12845 #define nir_load_subgroup_gt_mask nir_build_load_subgroup_gt_mask
   12846 #define nir_build_load_subgroup_id _nir_build_load_subgroup_id
   12847 #define nir_load_subgroup_id nir_build_load_subgroup_id
   12848 #define nir_build_load_subgroup_id_shift_ir3 _nir_build_load_subgroup_id_shift_ir3
   12849 #define nir_load_subgroup_id_shift_ir3 nir_build_load_subgroup_id_shift_ir3
   12850 #define nir_build_load_subgroup_invocation _nir_build_load_subgroup_invocation
   12851 #define nir_load_subgroup_invocation nir_build_load_subgroup_invocation
   12852 #define nir_build_load_subgroup_le_mask _nir_build_load_subgroup_le_mask
   12853 #define nir_load_subgroup_le_mask nir_build_load_subgroup_le_mask
   12854 #define nir_build_load_subgroup_lt_mask _nir_build_load_subgroup_lt_mask
   12855 #define nir_load_subgroup_lt_mask nir_build_load_subgroup_lt_mask
   12856 #define nir_build_load_subgroup_size _nir_build_load_subgroup_size
   12857 #define nir_load_subgroup_size nir_build_load_subgroup_size
   12858 #define nir_build_load_tcs_header_ir3 _nir_build_load_tcs_header_ir3
   12859 #define nir_load_tcs_header_ir3 nir_build_load_tcs_header_ir3
   12860 #define nir_build_load_tcs_in_param_base_r600 _nir_build_load_tcs_in_param_base_r600
   12861 #define nir_load_tcs_in_param_base_r600 nir_build_load_tcs_in_param_base_r600
   12862 #define nir_build_load_tcs_num_patches_amd _nir_build_load_tcs_num_patches_amd
   12863 #define nir_load_tcs_num_patches_amd nir_build_load_tcs_num_patches_amd
   12864 #define nir_build_load_tcs_out_param_base_r600 _nir_build_load_tcs_out_param_base_r600
   12865 #define nir_load_tcs_out_param_base_r600 nir_build_load_tcs_out_param_base_r600
   12866 #define nir_build_load_tcs_rel_patch_id_r600 _nir_build_load_tcs_rel_patch_id_r600
   12867 #define nir_load_tcs_rel_patch_id_r600 nir_build_load_tcs_rel_patch_id_r600
   12868 #define nir_build_load_tcs_tess_factor_base_r600 _nir_build_load_tcs_tess_factor_base_r600
   12869 #define nir_load_tcs_tess_factor_base_r600 nir_build_load_tcs_tess_factor_base_r600
   12870 #define nir_build_load_tess_coord _nir_build_load_tess_coord
   12871 #define nir_load_tess_coord nir_build_load_tess_coord
   12872 #define nir_build_load_tess_coord_r600 _nir_build_load_tess_coord_r600
   12873 #define nir_load_tess_coord_r600 nir_build_load_tess_coord_r600
   12874 #define nir_build_load_tess_factor_base_ir3 _nir_build_load_tess_factor_base_ir3
   12875 #define nir_load_tess_factor_base_ir3 nir_build_load_tess_factor_base_ir3
   12876 #define nir_build_load_tess_level_inner _nir_build_load_tess_level_inner
   12877 #define nir_load_tess_level_inner nir_build_load_tess_level_inner
   12878 #define nir_build_load_tess_level_inner_default _nir_build_load_tess_level_inner_default
   12879 #define nir_load_tess_level_inner_default nir_build_load_tess_level_inner_default
   12880 #define nir_build_load_tess_level_outer _nir_build_load_tess_level_outer
   12881 #define nir_load_tess_level_outer nir_build_load_tess_level_outer
   12882 #define nir_build_load_tess_level_outer_default _nir_build_load_tess_level_outer_default
   12883 #define nir_load_tess_level_outer_default nir_build_load_tess_level_outer_default
   12884 #define nir_build_load_tess_param_base_ir3 _nir_build_load_tess_param_base_ir3
   12885 #define nir_load_tess_param_base_ir3 nir_build_load_tess_param_base_ir3
   12886 #define nir_build_load_tess_rel_patch_id_amd _nir_build_load_tess_rel_patch_id_amd
   12887 #define nir_load_tess_rel_patch_id_amd nir_build_load_tess_rel_patch_id_amd
   12888 #define nir_build_load_texture_rect_scaling _nir_build_load_texture_rect_scaling
   12889 #define nir_load_texture_rect_scaling nir_build_load_texture_rect_scaling
   12890 #ifdef __cplusplus
   12891 #define nir_build_load_tlb_color_v3d(build, num_components, bit_size, src0, ...) \
   12892 _nir_build_load_tlb_color_v3d(build, num_components, bit_size, src0, _nir_load_tlb_color_v3d_indices{0, __VA_ARGS__})
   12893 #else
   12894 #define nir_build_load_tlb_color_v3d(build, num_components, bit_size, src0, ...) \
   12895 _nir_build_load_tlb_color_v3d(build, num_components, bit_size, src0, (struct _nir_load_tlb_color_v3d_indices){0, __VA_ARGS__})
   12896 #endif
   12897 #define nir_load_tlb_color_v3d nir_build_load_tlb_color_v3d
   12898 #ifdef __cplusplus
   12899 #define nir_build_load_ubo(build, num_components, bit_size, src0, src1, ...) \
   12900 _nir_build_load_ubo(build, num_components, bit_size, src0, src1, _nir_load_ubo_indices{0, __VA_ARGS__})
   12901 #else
   12902 #define nir_build_load_ubo(build, num_components, bit_size, src0, src1, ...) \
   12903 _nir_build_load_ubo(build, num_components, bit_size, src0, src1, (struct _nir_load_ubo_indices){0, __VA_ARGS__})
   12904 #endif
   12905 #define nir_load_ubo nir_build_load_ubo
   12906 #define nir_build_load_ubo_dxil _nir_build_load_ubo_dxil
   12907 #define nir_load_ubo_dxil nir_build_load_ubo_dxil
   12908 #ifdef __cplusplus
   12909 #define nir_build_load_ubo_vec4(build, num_components, bit_size, src0, src1, ...) \
   12910 _nir_build_load_ubo_vec4(build, num_components, bit_size, src0, src1, _nir_load_ubo_vec4_indices{0, __VA_ARGS__})
   12911 #else
   12912 #define nir_build_load_ubo_vec4(build, num_components, bit_size, src0, src1, ...) \
   12913 _nir_build_load_ubo_vec4(build, num_components, bit_size, src0, src1, (struct _nir_load_ubo_vec4_indices){0, __VA_ARGS__})
   12914 #endif
   12915 #define nir_load_ubo_vec4 nir_build_load_ubo_vec4
   12916 #ifdef __cplusplus
   12917 #define nir_build_load_uniform(build, num_components, bit_size, src0, ...) \
   12918 _nir_build_load_uniform(build, num_components, bit_size, src0, _nir_load_uniform_indices{0, __VA_ARGS__})
   12919 #else
   12920 #define nir_build_load_uniform(build, num_components, bit_size, src0, ...) \
   12921 _nir_build_load_uniform(build, num_components, bit_size, src0, (struct _nir_load_uniform_indices){0, __VA_ARGS__})
   12922 #endif
   12923 #define nir_load_uniform nir_build_load_uniform
   12924 #ifdef __cplusplus
   12925 #define nir_build_load_user_clip_plane(build, ...) \
   12926 _nir_build_load_user_clip_plane(build, _nir_load_user_clip_plane_indices{0, __VA_ARGS__})
   12927 #else
   12928 #define nir_build_load_user_clip_plane(build, ...) \
   12929 _nir_build_load_user_clip_plane(build, (struct _nir_load_user_clip_plane_indices){0, __VA_ARGS__})
   12930 #endif
   12931 #define nir_load_user_clip_plane nir_build_load_user_clip_plane
   12932 #define nir_build_load_user_data_amd _nir_build_load_user_data_amd
   12933 #define nir_load_user_data_amd nir_build_load_user_data_amd
   12934 #define nir_build_load_vertex_id _nir_build_load_vertex_id
   12935 #define nir_load_vertex_id nir_build_load_vertex_id
   12936 #define nir_build_load_vertex_id_zero_base _nir_build_load_vertex_id_zero_base
   12937 #define nir_load_vertex_id_zero_base nir_build_load_vertex_id_zero_base
   12938 #define nir_build_load_view_index _nir_build_load_view_index
   12939 #define nir_load_view_index nir_build_load_view_index
   12940 #define nir_build_load_viewport_offset _nir_build_load_viewport_offset
   12941 #define nir_load_viewport_offset nir_build_load_viewport_offset
   12942 #define nir_build_load_viewport_scale _nir_build_load_viewport_scale
   12943 #define nir_load_viewport_scale nir_build_load_viewport_scale
   12944 #define nir_build_load_viewport_x_offset _nir_build_load_viewport_x_offset
   12945 #define nir_load_viewport_x_offset nir_build_load_viewport_x_offset
   12946 #define nir_build_load_viewport_x_scale _nir_build_load_viewport_x_scale
   12947 #define nir_load_viewport_x_scale nir_build_load_viewport_x_scale
   12948 #define nir_build_load_viewport_y_offset _nir_build_load_viewport_y_offset
   12949 #define nir_load_viewport_y_offset nir_build_load_viewport_y_offset
   12950 #define nir_build_load_viewport_y_scale _nir_build_load_viewport_y_scale
   12951 #define nir_load_viewport_y_scale nir_build_load_viewport_y_scale
   12952 #define nir_build_load_viewport_z_offset _nir_build_load_viewport_z_offset
   12953 #define nir_load_viewport_z_offset nir_build_load_viewport_z_offset
   12954 #define nir_build_load_viewport_z_scale _nir_build_load_viewport_z_scale
   12955 #define nir_load_viewport_z_scale nir_build_load_viewport_z_scale
   12956 #define nir_build_load_vs_primitive_stride_ir3 _nir_build_load_vs_primitive_stride_ir3
   12957 #define nir_load_vs_primitive_stride_ir3 nir_build_load_vs_primitive_stride_ir3
   12958 #define nir_build_load_vs_vertex_stride_ir3 _nir_build_load_vs_vertex_stride_ir3
   12959 #define nir_load_vs_vertex_stride_ir3 nir_build_load_vs_vertex_stride_ir3
   12960 #ifdef __cplusplus
   12961 #define nir_build_load_vulkan_descriptor(build, num_components, bit_size, src0, ...) \
   12962 _nir_build_load_vulkan_descriptor(build, num_components, bit_size, src0, _nir_load_vulkan_descriptor_indices{0, __VA_ARGS__})
   12963 #else
   12964 #define nir_build_load_vulkan_descriptor(build, num_components, bit_size, src0, ...) \
   12965 _nir_build_load_vulkan_descriptor(build, num_components, bit_size, src0, (struct _nir_load_vulkan_descriptor_indices){0, __VA_ARGS__})
   12966 #endif
   12967 #define nir_load_vulkan_descriptor nir_build_load_vulkan_descriptor
   12968 #define nir_build_load_work_dim _nir_build_load_work_dim
   12969 #define nir_load_work_dim nir_build_load_work_dim
   12970 #define nir_build_load_workgroup_id _nir_build_load_workgroup_id
   12971 #define nir_load_workgroup_id nir_build_load_workgroup_id
   12972 #define nir_build_load_workgroup_id_zero_base _nir_build_load_workgroup_id_zero_base
   12973 #define nir_load_workgroup_id_zero_base nir_build_load_workgroup_id_zero_base
   12974 #define nir_build_load_workgroup_num_input_primitives_amd _nir_build_load_workgroup_num_input_primitives_amd
   12975 #define nir_load_workgroup_num_input_primitives_amd nir_build_load_workgroup_num_input_primitives_amd
   12976 #define nir_build_load_workgroup_num_input_vertices_amd _nir_build_load_workgroup_num_input_vertices_amd
   12977 #define nir_load_workgroup_num_input_vertices_amd nir_build_load_workgroup_num_input_vertices_amd
   12978 #define nir_build_load_workgroup_size _nir_build_load_workgroup_size
   12979 #define nir_load_workgroup_size nir_build_load_workgroup_size
   12980 #ifdef __cplusplus
   12981 #define nir_build_masked_swizzle_amd(build, src0, ...) \
   12982 _nir_build_masked_swizzle_amd(build, src0, _nir_masked_swizzle_amd_indices{0, __VA_ARGS__})
   12983 #else
   12984 #define nir_build_masked_swizzle_amd(build, src0, ...) \
   12985 _nir_build_masked_swizzle_amd(build, src0, (struct _nir_masked_swizzle_amd_indices){0, __VA_ARGS__})
   12986 #endif
   12987 #define nir_masked_swizzle_amd nir_build_masked_swizzle_amd
   12988 #define nir_build_mbcnt_amd _nir_build_mbcnt_amd
   12989 #define nir_mbcnt_amd nir_build_mbcnt_amd
   12990 #ifdef __cplusplus
   12991 #define nir_build_memcpy_deref(build, src0, src1, src2, ...) \
   12992 _nir_build_memcpy_deref(build, src0, src1, src2, _nir_memcpy_deref_indices{0, __VA_ARGS__})
   12993 #else
   12994 #define nir_build_memcpy_deref(build, src0, src1, src2, ...) \
   12995 _nir_build_memcpy_deref(build, src0, src1, src2, (struct _nir_memcpy_deref_indices){0, __VA_ARGS__})
   12996 #endif
   12997 #define nir_memcpy_deref nir_build_memcpy_deref
   12998 #define nir_build_memory_barrier _nir_build_memory_barrier
   12999 #define nir_memory_barrier nir_build_memory_barrier
   13000 #define nir_build_memory_barrier_atomic_counter _nir_build_memory_barrier_atomic_counter
   13001 #define nir_memory_barrier_atomic_counter nir_build_memory_barrier_atomic_counter
   13002 #define nir_build_memory_barrier_buffer _nir_build_memory_barrier_buffer
   13003 #define nir_memory_barrier_buffer nir_build_memory_barrier_buffer
   13004 #define nir_build_memory_barrier_image _nir_build_memory_barrier_image
   13005 #define nir_memory_barrier_image nir_build_memory_barrier_image
   13006 #define nir_build_memory_barrier_shared _nir_build_memory_barrier_shared
   13007 #define nir_memory_barrier_shared nir_build_memory_barrier_shared
   13008 #define nir_build_memory_barrier_tcs_patch _nir_build_memory_barrier_tcs_patch
   13009 #define nir_memory_barrier_tcs_patch nir_build_memory_barrier_tcs_patch
   13010 #define nir_build_nop _nir_build_nop
   13011 #define nir_nop nir_build_nop
   13012 #define nir_build_overwrite_tes_arguments_amd _nir_build_overwrite_tes_arguments_amd
   13013 #define nir_overwrite_tes_arguments_amd nir_build_overwrite_tes_arguments_amd
   13014 #define nir_build_overwrite_vs_arguments_amd _nir_build_overwrite_vs_arguments_amd
   13015 #define nir_overwrite_vs_arguments_amd nir_build_overwrite_vs_arguments_amd
   13016 #define nir_build_printf _nir_build_printf
   13017 #define nir_printf nir_build_printf
   13018 #define nir_build_quad_broadcast _nir_build_quad_broadcast
   13019 #define nir_quad_broadcast nir_build_quad_broadcast
   13020 #define nir_build_quad_swap_diagonal _nir_build_quad_swap_diagonal
   13021 #define nir_quad_swap_diagonal nir_build_quad_swap_diagonal
   13022 #define nir_build_quad_swap_horizontal _nir_build_quad_swap_horizontal
   13023 #define nir_quad_swap_horizontal nir_build_quad_swap_horizontal
   13024 #define nir_build_quad_swap_vertical _nir_build_quad_swap_vertical
   13025 #define nir_quad_swap_vertical nir_build_quad_swap_vertical
   13026 #ifdef __cplusplus
   13027 #define nir_build_quad_swizzle_amd(build, src0, ...) \
   13028 _nir_build_quad_swizzle_amd(build, src0, _nir_quad_swizzle_amd_indices{0, __VA_ARGS__})
   13029 #else
   13030 #define nir_build_quad_swizzle_amd(build, src0, ...) \
   13031 _nir_build_quad_swizzle_amd(build, src0, (struct _nir_quad_swizzle_amd_indices){0, __VA_ARGS__})
   13032 #endif
   13033 #define nir_quad_swizzle_amd nir_build_quad_swizzle_amd
   13034 #define nir_build_read_first_invocation _nir_build_read_first_invocation
   13035 #define nir_read_first_invocation nir_build_read_first_invocation
   13036 #define nir_build_read_invocation _nir_build_read_invocation
   13037 #define nir_read_invocation nir_build_read_invocation
   13038 #define nir_build_read_invocation_cond_ir3 _nir_build_read_invocation_cond_ir3
   13039 #define nir_read_invocation_cond_ir3 nir_build_read_invocation_cond_ir3
   13040 #ifdef __cplusplus
   13041 #define nir_build_reduce(build, src0, ...) \
   13042 _nir_build_reduce(build, src0, _nir_reduce_indices{0, __VA_ARGS__})
   13043 #else
   13044 #define nir_build_reduce(build, src0, ...) \
   13045 _nir_build_reduce(build, src0, (struct _nir_reduce_indices){0, __VA_ARGS__})
   13046 #endif
   13047 #define nir_reduce nir_build_reduce
   13048 #define nir_build_report_ray_intersection _nir_build_report_ray_intersection
   13049 #define nir_report_ray_intersection nir_build_report_ray_intersection
   13050 #ifdef __cplusplus
   13051 #define nir_build_rt_execute_callable(build, src0, src1, ...) \
   13052 _nir_build_rt_execute_callable(build, src0, src1, _nir_rt_execute_callable_indices{0, __VA_ARGS__})
   13053 #else
   13054 #define nir_build_rt_execute_callable(build, src0, src1, ...) \
   13055 _nir_build_rt_execute_callable(build, src0, src1, (struct _nir_rt_execute_callable_indices){0, __VA_ARGS__})
   13056 #endif
   13057 #define nir_rt_execute_callable nir_build_rt_execute_callable
   13058 #ifdef __cplusplus
   13059 #define nir_build_rt_resume(build, ...) \
   13060 _nir_build_rt_resume(build, _nir_rt_resume_indices{0, __VA_ARGS__})
   13061 #else
   13062 #define nir_build_rt_resume(build, ...) \
   13063 _nir_build_rt_resume(build, (struct _nir_rt_resume_indices){0, __VA_ARGS__})
   13064 #endif
   13065 #define nir_rt_resume nir_build_rt_resume
   13066 #define nir_build_rt_return_amd _nir_build_rt_return_amd
   13067 #define nir_rt_return_amd nir_build_rt_return_amd
   13068 #ifdef __cplusplus
   13069 #define nir_build_rt_trace_ray(build, src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, ...) \
   13070 _nir_build_rt_trace_ray(build, src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, _nir_rt_trace_ray_indices{0, __VA_ARGS__})
   13071 #else
   13072 #define nir_build_rt_trace_ray(build, src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, ...) \
   13073 _nir_build_rt_trace_ray(build, src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, (struct _nir_rt_trace_ray_indices){0, __VA_ARGS__})
   13074 #endif
   13075 #define nir_rt_trace_ray nir_build_rt_trace_ray
   13076 #ifdef __cplusplus
   13077 #define nir_build_scoped_barrier(build, ...) \
   13078 _nir_build_scoped_barrier(build, _nir_scoped_barrier_indices{0, __VA_ARGS__})
   13079 #else
   13080 #define nir_build_scoped_barrier(build, ...) \
   13081 _nir_build_scoped_barrier(build, (struct _nir_scoped_barrier_indices){0, __VA_ARGS__})
   13082 #endif
   13083 #define nir_scoped_barrier nir_build_scoped_barrier
   13084 #ifdef __cplusplus
   13085 #define nir_build_set_vertex_and_primitive_count(build, src0, src1, ...) \
   13086 _nir_build_set_vertex_and_primitive_count(build, src0, src1, _nir_set_vertex_and_primitive_count_indices{0, __VA_ARGS__})
   13087 #else
   13088 #define nir_build_set_vertex_and_primitive_count(build, src0, src1, ...) \
   13089 _nir_build_set_vertex_and_primitive_count(build, src0, src1, (struct _nir_set_vertex_and_primitive_count_indices){0, __VA_ARGS__})
   13090 #endif
   13091 #define nir_set_vertex_and_primitive_count nir_build_set_vertex_and_primitive_count
   13092 #ifdef __cplusplus
   13093 #define nir_build_shader_clock(build, ...) \
   13094 _nir_build_shader_clock(build, _nir_shader_clock_indices{0, __VA_ARGS__})
   13095 #else
   13096 #define nir_build_shader_clock(build, ...) \
   13097 _nir_build_shader_clock(build, (struct _nir_shader_clock_indices){0, __VA_ARGS__})
   13098 #endif
   13099 #define nir_shader_clock nir_build_shader_clock
   13100 #ifdef __cplusplus
   13101 #define nir_build_shared_atomic_add(build, bit_size, src0, src1, ...) \
   13102 _nir_build_shared_atomic_add(build, bit_size, src0, src1, _nir_shared_atomic_add_indices{0, __VA_ARGS__})
   13103 #else
   13104 #define nir_build_shared_atomic_add(build, bit_size, src0, src1, ...) \
   13105 _nir_build_shared_atomic_add(build, bit_size, src0, src1, (struct _nir_shared_atomic_add_indices){0, __VA_ARGS__})
   13106 #endif
   13107 #define nir_shared_atomic_add nir_build_shared_atomic_add
   13108 #define nir_build_shared_atomic_add_dxil _nir_build_shared_atomic_add_dxil
   13109 #define nir_shared_atomic_add_dxil nir_build_shared_atomic_add_dxil
   13110 #ifdef __cplusplus
   13111 #define nir_build_shared_atomic_and(build, bit_size, src0, src1, ...) \
   13112 _nir_build_shared_atomic_and(build, bit_size, src0, src1, _nir_shared_atomic_and_indices{0, __VA_ARGS__})
   13113 #else
   13114 #define nir_build_shared_atomic_and(build, bit_size, src0, src1, ...) \
   13115 _nir_build_shared_atomic_and(build, bit_size, src0, src1, (struct _nir_shared_atomic_and_indices){0, __VA_ARGS__})
   13116 #endif
   13117 #define nir_shared_atomic_and nir_build_shared_atomic_and
   13118 #define nir_build_shared_atomic_and_dxil _nir_build_shared_atomic_and_dxil
   13119 #define nir_shared_atomic_and_dxil nir_build_shared_atomic_and_dxil
   13120 #ifdef __cplusplus
   13121 #define nir_build_shared_atomic_comp_swap(build, bit_size, src0, src1, src2, ...) \
   13122 _nir_build_shared_atomic_comp_swap(build, bit_size, src0, src1, src2, _nir_shared_atomic_comp_swap_indices{0, __VA_ARGS__})
   13123 #else
   13124 #define nir_build_shared_atomic_comp_swap(build, bit_size, src0, src1, src2, ...) \
   13125 _nir_build_shared_atomic_comp_swap(build, bit_size, src0, src1, src2, (struct _nir_shared_atomic_comp_swap_indices){0, __VA_ARGS__})
   13126 #endif
   13127 #define nir_shared_atomic_comp_swap nir_build_shared_atomic_comp_swap
   13128 #define nir_build_shared_atomic_comp_swap_dxil _nir_build_shared_atomic_comp_swap_dxil
   13129 #define nir_shared_atomic_comp_swap_dxil nir_build_shared_atomic_comp_swap_dxil
   13130 #ifdef __cplusplus
   13131 #define nir_build_shared_atomic_exchange(build, bit_size, src0, src1, ...) \
   13132 _nir_build_shared_atomic_exchange(build, bit_size, src0, src1, _nir_shared_atomic_exchange_indices{0, __VA_ARGS__})
   13133 #else
   13134 #define nir_build_shared_atomic_exchange(build, bit_size, src0, src1, ...) \
   13135 _nir_build_shared_atomic_exchange(build, bit_size, src0, src1, (struct _nir_shared_atomic_exchange_indices){0, __VA_ARGS__})
   13136 #endif
   13137 #define nir_shared_atomic_exchange nir_build_shared_atomic_exchange
   13138 #define nir_build_shared_atomic_exchange_dxil _nir_build_shared_atomic_exchange_dxil
   13139 #define nir_shared_atomic_exchange_dxil nir_build_shared_atomic_exchange_dxil
   13140 #ifdef __cplusplus
   13141 #define nir_build_shared_atomic_fadd(build, bit_size, src0, src1, ...) \
   13142 _nir_build_shared_atomic_fadd(build, bit_size, src0, src1, _nir_shared_atomic_fadd_indices{0, __VA_ARGS__})
   13143 #else
   13144 #define nir_build_shared_atomic_fadd(build, bit_size, src0, src1, ...) \
   13145 _nir_build_shared_atomic_fadd(build, bit_size, src0, src1, (struct _nir_shared_atomic_fadd_indices){0, __VA_ARGS__})
   13146 #endif
   13147 #define nir_shared_atomic_fadd nir_build_shared_atomic_fadd
   13148 #ifdef __cplusplus
   13149 #define nir_build_shared_atomic_fcomp_swap(build, bit_size, src0, src1, src2, ...) \
   13150 _nir_build_shared_atomic_fcomp_swap(build, bit_size, src0, src1, src2, _nir_shared_atomic_fcomp_swap_indices{0, __VA_ARGS__})
   13151 #else
   13152 #define nir_build_shared_atomic_fcomp_swap(build, bit_size, src0, src1, src2, ...) \
   13153 _nir_build_shared_atomic_fcomp_swap(build, bit_size, src0, src1, src2, (struct _nir_shared_atomic_fcomp_swap_indices){0, __VA_ARGS__})
   13154 #endif
   13155 #define nir_shared_atomic_fcomp_swap nir_build_shared_atomic_fcomp_swap
   13156 #ifdef __cplusplus
   13157 #define nir_build_shared_atomic_fmax(build, bit_size, src0, src1, ...) \
   13158 _nir_build_shared_atomic_fmax(build, bit_size, src0, src1, _nir_shared_atomic_fmax_indices{0, __VA_ARGS__})
   13159 #else
   13160 #define nir_build_shared_atomic_fmax(build, bit_size, src0, src1, ...) \
   13161 _nir_build_shared_atomic_fmax(build, bit_size, src0, src1, (struct _nir_shared_atomic_fmax_indices){0, __VA_ARGS__})
   13162 #endif
   13163 #define nir_shared_atomic_fmax nir_build_shared_atomic_fmax
   13164 #ifdef __cplusplus
   13165 #define nir_build_shared_atomic_fmin(build, bit_size, src0, src1, ...) \
   13166 _nir_build_shared_atomic_fmin(build, bit_size, src0, src1, _nir_shared_atomic_fmin_indices{0, __VA_ARGS__})
   13167 #else
   13168 #define nir_build_shared_atomic_fmin(build, bit_size, src0, src1, ...) \
   13169 _nir_build_shared_atomic_fmin(build, bit_size, src0, src1, (struct _nir_shared_atomic_fmin_indices){0, __VA_ARGS__})
   13170 #endif
   13171 #define nir_shared_atomic_fmin nir_build_shared_atomic_fmin
   13172 #ifdef __cplusplus
   13173 #define nir_build_shared_atomic_imax(build, bit_size, src0, src1, ...) \
   13174 _nir_build_shared_atomic_imax(build, bit_size, src0, src1, _nir_shared_atomic_imax_indices{0, __VA_ARGS__})
   13175 #else
   13176 #define nir_build_shared_atomic_imax(build, bit_size, src0, src1, ...) \
   13177 _nir_build_shared_atomic_imax(build, bit_size, src0, src1, (struct _nir_shared_atomic_imax_indices){0, __VA_ARGS__})
   13178 #endif
   13179 #define nir_shared_atomic_imax nir_build_shared_atomic_imax
   13180 #define nir_build_shared_atomic_imax_dxil _nir_build_shared_atomic_imax_dxil
   13181 #define nir_shared_atomic_imax_dxil nir_build_shared_atomic_imax_dxil
   13182 #ifdef __cplusplus
   13183 #define nir_build_shared_atomic_imin(build, bit_size, src0, src1, ...) \
   13184 _nir_build_shared_atomic_imin(build, bit_size, src0, src1, _nir_shared_atomic_imin_indices{0, __VA_ARGS__})
   13185 #else
   13186 #define nir_build_shared_atomic_imin(build, bit_size, src0, src1, ...) \
   13187 _nir_build_shared_atomic_imin(build, bit_size, src0, src1, (struct _nir_shared_atomic_imin_indices){0, __VA_ARGS__})
   13188 #endif
   13189 #define nir_shared_atomic_imin nir_build_shared_atomic_imin
   13190 #define nir_build_shared_atomic_imin_dxil _nir_build_shared_atomic_imin_dxil
   13191 #define nir_shared_atomic_imin_dxil nir_build_shared_atomic_imin_dxil
   13192 #ifdef __cplusplus
   13193 #define nir_build_shared_atomic_or(build, bit_size, src0, src1, ...) \
   13194 _nir_build_shared_atomic_or(build, bit_size, src0, src1, _nir_shared_atomic_or_indices{0, __VA_ARGS__})
   13195 #else
   13196 #define nir_build_shared_atomic_or(build, bit_size, src0, src1, ...) \
   13197 _nir_build_shared_atomic_or(build, bit_size, src0, src1, (struct _nir_shared_atomic_or_indices){0, __VA_ARGS__})
   13198 #endif
   13199 #define nir_shared_atomic_or nir_build_shared_atomic_or
   13200 #define nir_build_shared_atomic_or_dxil _nir_build_shared_atomic_or_dxil
   13201 #define nir_shared_atomic_or_dxil nir_build_shared_atomic_or_dxil
   13202 #ifdef __cplusplus
   13203 #define nir_build_shared_atomic_umax(build, bit_size, src0, src1, ...) \
   13204 _nir_build_shared_atomic_umax(build, bit_size, src0, src1, _nir_shared_atomic_umax_indices{0, __VA_ARGS__})
   13205 #else
   13206 #define nir_build_shared_atomic_umax(build, bit_size, src0, src1, ...) \
   13207 _nir_build_shared_atomic_umax(build, bit_size, src0, src1, (struct _nir_shared_atomic_umax_indices){0, __VA_ARGS__})
   13208 #endif
   13209 #define nir_shared_atomic_umax nir_build_shared_atomic_umax
   13210 #define nir_build_shared_atomic_umax_dxil _nir_build_shared_atomic_umax_dxil
   13211 #define nir_shared_atomic_umax_dxil nir_build_shared_atomic_umax_dxil
   13212 #ifdef __cplusplus
   13213 #define nir_build_shared_atomic_umin(build, bit_size, src0, src1, ...) \
   13214 _nir_build_shared_atomic_umin(build, bit_size, src0, src1, _nir_shared_atomic_umin_indices{0, __VA_ARGS__})
   13215 #else
   13216 #define nir_build_shared_atomic_umin(build, bit_size, src0, src1, ...) \
   13217 _nir_build_shared_atomic_umin(build, bit_size, src0, src1, (struct _nir_shared_atomic_umin_indices){0, __VA_ARGS__})
   13218 #endif
   13219 #define nir_shared_atomic_umin nir_build_shared_atomic_umin
   13220 #define nir_build_shared_atomic_umin_dxil _nir_build_shared_atomic_umin_dxil
   13221 #define nir_shared_atomic_umin_dxil nir_build_shared_atomic_umin_dxil
   13222 #ifdef __cplusplus
   13223 #define nir_build_shared_atomic_xor(build, bit_size, src0, src1, ...) \
   13224 _nir_build_shared_atomic_xor(build, bit_size, src0, src1, _nir_shared_atomic_xor_indices{0, __VA_ARGS__})
   13225 #else
   13226 #define nir_build_shared_atomic_xor(build, bit_size, src0, src1, ...) \
   13227 _nir_build_shared_atomic_xor(build, bit_size, src0, src1, (struct _nir_shared_atomic_xor_indices){0, __VA_ARGS__})
   13228 #endif
   13229 #define nir_shared_atomic_xor nir_build_shared_atomic_xor
   13230 #define nir_build_shared_atomic_xor_dxil _nir_build_shared_atomic_xor_dxil
   13231 #define nir_shared_atomic_xor_dxil nir_build_shared_atomic_xor_dxil
   13232 #define nir_build_shuffle _nir_build_shuffle
   13233 #define nir_shuffle nir_build_shuffle
   13234 #define nir_build_shuffle_down _nir_build_shuffle_down
   13235 #define nir_shuffle_down nir_build_shuffle_down
   13236 #define nir_build_shuffle_up _nir_build_shuffle_up
   13237 #define nir_shuffle_up nir_build_shuffle_up
   13238 #define nir_build_shuffle_xor _nir_build_shuffle_xor
   13239 #define nir_shuffle_xor nir_build_shuffle_xor
   13240 #define nir_build_sparse_residency_code_and _nir_build_sparse_residency_code_and
   13241 #define nir_sparse_residency_code_and nir_build_sparse_residency_code_and
   13242 #ifdef __cplusplus
   13243 #define nir_build_ssbo_atomic_add(build, bit_size, src0, src1, src2, ...) \
   13244 _nir_build_ssbo_atomic_add(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_add_indices{0, __VA_ARGS__})
   13245 #else
   13246 #define nir_build_ssbo_atomic_add(build, bit_size, src0, src1, src2, ...) \
   13247 _nir_build_ssbo_atomic_add(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_add_indices){0, __VA_ARGS__})
   13248 #endif
   13249 #define nir_ssbo_atomic_add nir_build_ssbo_atomic_add
   13250 #ifdef __cplusplus
   13251 #define nir_build_ssbo_atomic_add_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13252 _nir_build_ssbo_atomic_add_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_add_ir3_indices{0, __VA_ARGS__})
   13253 #else
   13254 #define nir_build_ssbo_atomic_add_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13255 _nir_build_ssbo_atomic_add_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_add_ir3_indices){0, __VA_ARGS__})
   13256 #endif
   13257 #define nir_ssbo_atomic_add_ir3 nir_build_ssbo_atomic_add_ir3
   13258 #ifdef __cplusplus
   13259 #define nir_build_ssbo_atomic_and(build, bit_size, src0, src1, src2, ...) \
   13260 _nir_build_ssbo_atomic_and(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_and_indices{0, __VA_ARGS__})
   13261 #else
   13262 #define nir_build_ssbo_atomic_and(build, bit_size, src0, src1, src2, ...) \
   13263 _nir_build_ssbo_atomic_and(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_and_indices){0, __VA_ARGS__})
   13264 #endif
   13265 #define nir_ssbo_atomic_and nir_build_ssbo_atomic_and
   13266 #ifdef __cplusplus
   13267 #define nir_build_ssbo_atomic_and_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13268 _nir_build_ssbo_atomic_and_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_and_ir3_indices{0, __VA_ARGS__})
   13269 #else
   13270 #define nir_build_ssbo_atomic_and_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13271 _nir_build_ssbo_atomic_and_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_and_ir3_indices){0, __VA_ARGS__})
   13272 #endif
   13273 #define nir_ssbo_atomic_and_ir3 nir_build_ssbo_atomic_and_ir3
   13274 #ifdef __cplusplus
   13275 #define nir_build_ssbo_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, ...) \
   13276 _nir_build_ssbo_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_comp_swap_indices{0, __VA_ARGS__})
   13277 #else
   13278 #define nir_build_ssbo_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, ...) \
   13279 _nir_build_ssbo_atomic_comp_swap(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_comp_swap_indices){0, __VA_ARGS__})
   13280 #endif
   13281 #define nir_ssbo_atomic_comp_swap nir_build_ssbo_atomic_comp_swap
   13282 #ifdef __cplusplus
   13283 #define nir_build_ssbo_atomic_comp_swap_ir3(build, bit_size, src0, src1, src2, src3, src4, ...) \
   13284 _nir_build_ssbo_atomic_comp_swap_ir3(build, bit_size, src0, src1, src2, src3, src4, _nir_ssbo_atomic_comp_swap_ir3_indices{0, __VA_ARGS__})
   13285 #else
   13286 #define nir_build_ssbo_atomic_comp_swap_ir3(build, bit_size, src0, src1, src2, src3, src4, ...) \
   13287 _nir_build_ssbo_atomic_comp_swap_ir3(build, bit_size, src0, src1, src2, src3, src4, (struct _nir_ssbo_atomic_comp_swap_ir3_indices){0, __VA_ARGS__})
   13288 #endif
   13289 #define nir_ssbo_atomic_comp_swap_ir3 nir_build_ssbo_atomic_comp_swap_ir3
   13290 #ifdef __cplusplus
   13291 #define nir_build_ssbo_atomic_exchange(build, bit_size, src0, src1, src2, ...) \
   13292 _nir_build_ssbo_atomic_exchange(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_exchange_indices{0, __VA_ARGS__})
   13293 #else
   13294 #define nir_build_ssbo_atomic_exchange(build, bit_size, src0, src1, src2, ...) \
   13295 _nir_build_ssbo_atomic_exchange(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_exchange_indices){0, __VA_ARGS__})
   13296 #endif
   13297 #define nir_ssbo_atomic_exchange nir_build_ssbo_atomic_exchange
   13298 #ifdef __cplusplus
   13299 #define nir_build_ssbo_atomic_exchange_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13300 _nir_build_ssbo_atomic_exchange_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_exchange_ir3_indices{0, __VA_ARGS__})
   13301 #else
   13302 #define nir_build_ssbo_atomic_exchange_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13303 _nir_build_ssbo_atomic_exchange_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_exchange_ir3_indices){0, __VA_ARGS__})
   13304 #endif
   13305 #define nir_ssbo_atomic_exchange_ir3 nir_build_ssbo_atomic_exchange_ir3
   13306 #ifdef __cplusplus
   13307 #define nir_build_ssbo_atomic_fadd(build, bit_size, src0, src1, src2, ...) \
   13308 _nir_build_ssbo_atomic_fadd(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_fadd_indices{0, __VA_ARGS__})
   13309 #else
   13310 #define nir_build_ssbo_atomic_fadd(build, bit_size, src0, src1, src2, ...) \
   13311 _nir_build_ssbo_atomic_fadd(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_fadd_indices){0, __VA_ARGS__})
   13312 #endif
   13313 #define nir_ssbo_atomic_fadd nir_build_ssbo_atomic_fadd
   13314 #ifdef __cplusplus
   13315 #define nir_build_ssbo_atomic_fcomp_swap(build, bit_size, src0, src1, src2, src3, ...) \
   13316 _nir_build_ssbo_atomic_fcomp_swap(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_fcomp_swap_indices{0, __VA_ARGS__})
   13317 #else
   13318 #define nir_build_ssbo_atomic_fcomp_swap(build, bit_size, src0, src1, src2, src3, ...) \
   13319 _nir_build_ssbo_atomic_fcomp_swap(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_fcomp_swap_indices){0, __VA_ARGS__})
   13320 #endif
   13321 #define nir_ssbo_atomic_fcomp_swap nir_build_ssbo_atomic_fcomp_swap
   13322 #ifdef __cplusplus
   13323 #define nir_build_ssbo_atomic_fmax(build, bit_size, src0, src1, src2, ...) \
   13324 _nir_build_ssbo_atomic_fmax(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_fmax_indices{0, __VA_ARGS__})
   13325 #else
   13326 #define nir_build_ssbo_atomic_fmax(build, bit_size, src0, src1, src2, ...) \
   13327 _nir_build_ssbo_atomic_fmax(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_fmax_indices){0, __VA_ARGS__})
   13328 #endif
   13329 #define nir_ssbo_atomic_fmax nir_build_ssbo_atomic_fmax
   13330 #ifdef __cplusplus
   13331 #define nir_build_ssbo_atomic_fmin(build, bit_size, src0, src1, src2, ...) \
   13332 _nir_build_ssbo_atomic_fmin(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_fmin_indices{0, __VA_ARGS__})
   13333 #else
   13334 #define nir_build_ssbo_atomic_fmin(build, bit_size, src0, src1, src2, ...) \
   13335 _nir_build_ssbo_atomic_fmin(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_fmin_indices){0, __VA_ARGS__})
   13336 #endif
   13337 #define nir_ssbo_atomic_fmin nir_build_ssbo_atomic_fmin
   13338 #ifdef __cplusplus
   13339 #define nir_build_ssbo_atomic_imax(build, bit_size, src0, src1, src2, ...) \
   13340 _nir_build_ssbo_atomic_imax(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_imax_indices{0, __VA_ARGS__})
   13341 #else
   13342 #define nir_build_ssbo_atomic_imax(build, bit_size, src0, src1, src2, ...) \
   13343 _nir_build_ssbo_atomic_imax(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_imax_indices){0, __VA_ARGS__})
   13344 #endif
   13345 #define nir_ssbo_atomic_imax nir_build_ssbo_atomic_imax
   13346 #ifdef __cplusplus
   13347 #define nir_build_ssbo_atomic_imax_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13348 _nir_build_ssbo_atomic_imax_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_imax_ir3_indices{0, __VA_ARGS__})
   13349 #else
   13350 #define nir_build_ssbo_atomic_imax_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13351 _nir_build_ssbo_atomic_imax_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_imax_ir3_indices){0, __VA_ARGS__})
   13352 #endif
   13353 #define nir_ssbo_atomic_imax_ir3 nir_build_ssbo_atomic_imax_ir3
   13354 #ifdef __cplusplus
   13355 #define nir_build_ssbo_atomic_imin(build, bit_size, src0, src1, src2, ...) \
   13356 _nir_build_ssbo_atomic_imin(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_imin_indices{0, __VA_ARGS__})
   13357 #else
   13358 #define nir_build_ssbo_atomic_imin(build, bit_size, src0, src1, src2, ...) \
   13359 _nir_build_ssbo_atomic_imin(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_imin_indices){0, __VA_ARGS__})
   13360 #endif
   13361 #define nir_ssbo_atomic_imin nir_build_ssbo_atomic_imin
   13362 #ifdef __cplusplus
   13363 #define nir_build_ssbo_atomic_imin_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13364 _nir_build_ssbo_atomic_imin_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_imin_ir3_indices{0, __VA_ARGS__})
   13365 #else
   13366 #define nir_build_ssbo_atomic_imin_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13367 _nir_build_ssbo_atomic_imin_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_imin_ir3_indices){0, __VA_ARGS__})
   13368 #endif
   13369 #define nir_ssbo_atomic_imin_ir3 nir_build_ssbo_atomic_imin_ir3
   13370 #ifdef __cplusplus
   13371 #define nir_build_ssbo_atomic_or(build, bit_size, src0, src1, src2, ...) \
   13372 _nir_build_ssbo_atomic_or(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_or_indices{0, __VA_ARGS__})
   13373 #else
   13374 #define nir_build_ssbo_atomic_or(build, bit_size, src0, src1, src2, ...) \
   13375 _nir_build_ssbo_atomic_or(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_or_indices){0, __VA_ARGS__})
   13376 #endif
   13377 #define nir_ssbo_atomic_or nir_build_ssbo_atomic_or
   13378 #ifdef __cplusplus
   13379 #define nir_build_ssbo_atomic_or_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13380 _nir_build_ssbo_atomic_or_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_or_ir3_indices{0, __VA_ARGS__})
   13381 #else
   13382 #define nir_build_ssbo_atomic_or_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13383 _nir_build_ssbo_atomic_or_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_or_ir3_indices){0, __VA_ARGS__})
   13384 #endif
   13385 #define nir_ssbo_atomic_or_ir3 nir_build_ssbo_atomic_or_ir3
   13386 #ifdef __cplusplus
   13387 #define nir_build_ssbo_atomic_umax(build, bit_size, src0, src1, src2, ...) \
   13388 _nir_build_ssbo_atomic_umax(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_umax_indices{0, __VA_ARGS__})
   13389 #else
   13390 #define nir_build_ssbo_atomic_umax(build, bit_size, src0, src1, src2, ...) \
   13391 _nir_build_ssbo_atomic_umax(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_umax_indices){0, __VA_ARGS__})
   13392 #endif
   13393 #define nir_ssbo_atomic_umax nir_build_ssbo_atomic_umax
   13394 #ifdef __cplusplus
   13395 #define nir_build_ssbo_atomic_umax_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13396 _nir_build_ssbo_atomic_umax_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_umax_ir3_indices{0, __VA_ARGS__})
   13397 #else
   13398 #define nir_build_ssbo_atomic_umax_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13399 _nir_build_ssbo_atomic_umax_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_umax_ir3_indices){0, __VA_ARGS__})
   13400 #endif
   13401 #define nir_ssbo_atomic_umax_ir3 nir_build_ssbo_atomic_umax_ir3
   13402 #ifdef __cplusplus
   13403 #define nir_build_ssbo_atomic_umin(build, bit_size, src0, src1, src2, ...) \
   13404 _nir_build_ssbo_atomic_umin(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_umin_indices{0, __VA_ARGS__})
   13405 #else
   13406 #define nir_build_ssbo_atomic_umin(build, bit_size, src0, src1, src2, ...) \
   13407 _nir_build_ssbo_atomic_umin(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_umin_indices){0, __VA_ARGS__})
   13408 #endif
   13409 #define nir_ssbo_atomic_umin nir_build_ssbo_atomic_umin
   13410 #ifdef __cplusplus
   13411 #define nir_build_ssbo_atomic_umin_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13412 _nir_build_ssbo_atomic_umin_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_umin_ir3_indices{0, __VA_ARGS__})
   13413 #else
   13414 #define nir_build_ssbo_atomic_umin_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13415 _nir_build_ssbo_atomic_umin_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_umin_ir3_indices){0, __VA_ARGS__})
   13416 #endif
   13417 #define nir_ssbo_atomic_umin_ir3 nir_build_ssbo_atomic_umin_ir3
   13418 #ifdef __cplusplus
   13419 #define nir_build_ssbo_atomic_xor(build, bit_size, src0, src1, src2, ...) \
   13420 _nir_build_ssbo_atomic_xor(build, bit_size, src0, src1, src2, _nir_ssbo_atomic_xor_indices{0, __VA_ARGS__})
   13421 #else
   13422 #define nir_build_ssbo_atomic_xor(build, bit_size, src0, src1, src2, ...) \
   13423 _nir_build_ssbo_atomic_xor(build, bit_size, src0, src1, src2, (struct _nir_ssbo_atomic_xor_indices){0, __VA_ARGS__})
   13424 #endif
   13425 #define nir_ssbo_atomic_xor nir_build_ssbo_atomic_xor
   13426 #ifdef __cplusplus
   13427 #define nir_build_ssbo_atomic_xor_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13428 _nir_build_ssbo_atomic_xor_ir3(build, bit_size, src0, src1, src2, src3, _nir_ssbo_atomic_xor_ir3_indices{0, __VA_ARGS__})
   13429 #else
   13430 #define nir_build_ssbo_atomic_xor_ir3(build, bit_size, src0, src1, src2, src3, ...) \
   13431 _nir_build_ssbo_atomic_xor_ir3(build, bit_size, src0, src1, src2, src3, (struct _nir_ssbo_atomic_xor_ir3_indices){0, __VA_ARGS__})
   13432 #endif
   13433 #define nir_ssbo_atomic_xor_ir3 nir_build_ssbo_atomic_xor_ir3
   13434 #ifdef __cplusplus
   13435 #define nir_build_store_buffer_amd(build, src0, src1, src2, src3, ...) \
   13436 _nir_build_store_buffer_amd(build, src0, src1, src2, src3, _nir_store_buffer_amd_indices{0, __VA_ARGS__})
   13437 #else
   13438 #define nir_build_store_buffer_amd(build, src0, src1, src2, src3, ...) \
   13439 _nir_build_store_buffer_amd(build, src0, src1, src2, src3, (struct _nir_store_buffer_amd_indices){0, __VA_ARGS__})
   13440 #endif
   13441 #define nir_store_buffer_amd nir_build_store_buffer_amd
   13442 #ifdef __cplusplus
   13443 #define nir_build_store_combined_output_pan(build, src0, src1, src2, src3, ...) \
   13444 _nir_build_store_combined_output_pan(build, src0, src1, src2, src3, _nir_store_combined_output_pan_indices{0, __VA_ARGS__})
   13445 #else
   13446 #define nir_build_store_combined_output_pan(build, src0, src1, src2, src3, ...) \
   13447 _nir_build_store_combined_output_pan(build, src0, src1, src2, src3, (struct _nir_store_combined_output_pan_indices){0, __VA_ARGS__})
   13448 #endif
   13449 #define nir_store_combined_output_pan nir_build_store_combined_output_pan
   13450 #ifdef __cplusplus
   13451 #define nir_build_store_deref(build, src0, src1, ...) \
   13452 _nir_build_store_deref(build, src0, src1, _nir_store_deref_indices{0, __VA_ARGS__})
   13453 #else
   13454 #define nir_build_store_deref(build, src0, src1, ...) \
   13455 _nir_build_store_deref(build, src0, src1, (struct _nir_store_deref_indices){0, __VA_ARGS__})
   13456 #endif
   13457 #define nir_store_deref nir_build_store_deref
   13458 #ifdef __cplusplus
   13459 #define nir_build_store_deref_block_intel(build, src0, src1, ...) \
   13460 _nir_build_store_deref_block_intel(build, src0, src1, _nir_store_deref_block_intel_indices{0, __VA_ARGS__})
   13461 #else
   13462 #define nir_build_store_deref_block_intel(build, src0, src1, ...) \
   13463 _nir_build_store_deref_block_intel(build, src0, src1, (struct _nir_store_deref_block_intel_indices){0, __VA_ARGS__})
   13464 #endif
   13465 #define nir_store_deref_block_intel nir_build_store_deref_block_intel
   13466 #ifdef __cplusplus
   13467 #define nir_build_store_global(build, src0, src1, ...) \
   13468 _nir_build_store_global(build, src0, src1, _nir_store_global_indices{0, __VA_ARGS__})
   13469 #else
   13470 #define nir_build_store_global(build, src0, src1, ...) \
   13471 _nir_build_store_global(build, src0, src1, (struct _nir_store_global_indices){0, __VA_ARGS__})
   13472 #endif
   13473 #define nir_store_global nir_build_store_global
   13474 #ifdef __cplusplus
   13475 #define nir_build_store_global_block_intel(build, src0, src1, ...) \
   13476 _nir_build_store_global_block_intel(build, src0, src1, _nir_store_global_block_intel_indices{0, __VA_ARGS__})
   13477 #else
   13478 #define nir_build_store_global_block_intel(build, src0, src1, ...) \
   13479 _nir_build_store_global_block_intel(build, src0, src1, (struct _nir_store_global_block_intel_indices){0, __VA_ARGS__})
   13480 #endif
   13481 #define nir_store_global_block_intel nir_build_store_global_block_intel
   13482 #ifdef __cplusplus
   13483 #define nir_build_store_global_ir3(build, src0, src1, src2, ...) \
   13484 _nir_build_store_global_ir3(build, src0, src1, src2, _nir_store_global_ir3_indices{0, __VA_ARGS__})
   13485 #else
   13486 #define nir_build_store_global_ir3(build, src0, src1, src2, ...) \
   13487 _nir_build_store_global_ir3(build, src0, src1, src2, (struct _nir_store_global_ir3_indices){0, __VA_ARGS__})
   13488 #endif
   13489 #define nir_store_global_ir3 nir_build_store_global_ir3
   13490 #ifdef __cplusplus
   13491 #define nir_build_store_local_shared_r600(build, src0, src1, ...) \
   13492 _nir_build_store_local_shared_r600(build, src0, src1, _nir_store_local_shared_r600_indices{0, __VA_ARGS__})
   13493 #else
   13494 #define nir_build_store_local_shared_r600(build, src0, src1, ...) \
   13495 _nir_build_store_local_shared_r600(build, src0, src1, (struct _nir_store_local_shared_r600_indices){0, __VA_ARGS__})
   13496 #endif
   13497 #define nir_store_local_shared_r600 nir_build_store_local_shared_r600
   13498 #ifdef __cplusplus
   13499 #define nir_build_store_output(build, src0, src1, ...) \
   13500 _nir_build_store_output(build, src0, src1, _nir_store_output_indices{0, __VA_ARGS__})
   13501 #else
   13502 #define nir_build_store_output(build, src0, src1, ...) \
   13503 _nir_build_store_output(build, src0, src1, (struct _nir_store_output_indices){0, __VA_ARGS__})
   13504 #endif
   13505 #define nir_store_output nir_build_store_output
   13506 #ifdef __cplusplus
   13507 #define nir_build_store_per_primitive_output(build, src0, src1, src2, ...) \
   13508 _nir_build_store_per_primitive_output(build, src0, src1, src2, _nir_store_per_primitive_output_indices{0, __VA_ARGS__})
   13509 #else
   13510 #define nir_build_store_per_primitive_output(build, src0, src1, src2, ...) \
   13511 _nir_build_store_per_primitive_output(build, src0, src1, src2, (struct _nir_store_per_primitive_output_indices){0, __VA_ARGS__})
   13512 #endif
   13513 #define nir_store_per_primitive_output nir_build_store_per_primitive_output
   13514 #ifdef __cplusplus
   13515 #define nir_build_store_per_vertex_output(build, src0, src1, src2, ...) \
   13516 _nir_build_store_per_vertex_output(build, src0, src1, src2, _nir_store_per_vertex_output_indices{0, __VA_ARGS__})
   13517 #else
   13518 #define nir_build_store_per_vertex_output(build, src0, src1, src2, ...) \
   13519 _nir_build_store_per_vertex_output(build, src0, src1, src2, (struct _nir_store_per_vertex_output_indices){0, __VA_ARGS__})
   13520 #endif
   13521 #define nir_store_per_vertex_output nir_build_store_per_vertex_output
   13522 #define nir_build_store_raw_output_pan _nir_build_store_raw_output_pan
   13523 #define nir_store_raw_output_pan nir_build_store_raw_output_pan
   13524 #ifdef __cplusplus
   13525 #define nir_build_store_scratch(build, src0, src1, ...) \
   13526 _nir_build_store_scratch(build, src0, src1, _nir_store_scratch_indices{0, __VA_ARGS__})
   13527 #else
   13528 #define nir_build_store_scratch(build, src0, src1, ...) \
   13529 _nir_build_store_scratch(build, src0, src1, (struct _nir_store_scratch_indices){0, __VA_ARGS__})
   13530 #endif
   13531 #define nir_store_scratch nir_build_store_scratch
   13532 #define nir_build_store_scratch_dxil _nir_build_store_scratch_dxil
   13533 #define nir_store_scratch_dxil nir_build_store_scratch_dxil
   13534 #ifdef __cplusplus
   13535 #define nir_build_store_shared(build, src0, src1, ...) \
   13536 _nir_build_store_shared(build, src0, src1, _nir_store_shared_indices{0, __VA_ARGS__})
   13537 #else
   13538 #define nir_build_store_shared(build, src0, src1, ...) \
   13539 _nir_build_store_shared(build, src0, src1, (struct _nir_store_shared_indices){0, __VA_ARGS__})
   13540 #endif
   13541 #define nir_store_shared nir_build_store_shared
   13542 #ifdef __cplusplus
   13543 #define nir_build_store_shared_block_intel(build, src0, src1, ...) \
   13544 _nir_build_store_shared_block_intel(build, src0, src1, _nir_store_shared_block_intel_indices{0, __VA_ARGS__})
   13545 #else
   13546 #define nir_build_store_shared_block_intel(build, src0, src1, ...) \
   13547 _nir_build_store_shared_block_intel(build, src0, src1, (struct _nir_store_shared_block_intel_indices){0, __VA_ARGS__})
   13548 #endif
   13549 #define nir_store_shared_block_intel nir_build_store_shared_block_intel
   13550 #define nir_build_store_shared_dxil _nir_build_store_shared_dxil
   13551 #define nir_store_shared_dxil nir_build_store_shared_dxil
   13552 #ifdef __cplusplus
   13553 #define nir_build_store_shared_ir3(build, src0, src1, ...) \
   13554 _nir_build_store_shared_ir3(build, src0, src1, _nir_store_shared_ir3_indices{0, __VA_ARGS__})
   13555 #else
   13556 #define nir_build_store_shared_ir3(build, src0, src1, ...) \
   13557 _nir_build_store_shared_ir3(build, src0, src1, (struct _nir_store_shared_ir3_indices){0, __VA_ARGS__})
   13558 #endif
   13559 #define nir_store_shared_ir3 nir_build_store_shared_ir3
   13560 #define nir_build_store_shared_masked_dxil _nir_build_store_shared_masked_dxil
   13561 #define nir_store_shared_masked_dxil nir_build_store_shared_masked_dxil
   13562 #ifdef __cplusplus
   13563 #define nir_build_store_ssbo(build, src0, src1, src2, ...) \
   13564 _nir_build_store_ssbo(build, src0, src1, src2, _nir_store_ssbo_indices{0, __VA_ARGS__})
   13565 #else
   13566 #define nir_build_store_ssbo(build, src0, src1, src2, ...) \
   13567 _nir_build_store_ssbo(build, src0, src1, src2, (struct _nir_store_ssbo_indices){0, __VA_ARGS__})
   13568 #endif
   13569 #define nir_store_ssbo nir_build_store_ssbo
   13570 #ifdef __cplusplus
   13571 #define nir_build_store_ssbo_block_intel(build, src0, src1, src2, ...) \
   13572 _nir_build_store_ssbo_block_intel(build, src0, src1, src2, _nir_store_ssbo_block_intel_indices{0, __VA_ARGS__})
   13573 #else
   13574 #define nir_build_store_ssbo_block_intel(build, src0, src1, src2, ...) \
   13575 _nir_build_store_ssbo_block_intel(build, src0, src1, src2, (struct _nir_store_ssbo_block_intel_indices){0, __VA_ARGS__})
   13576 #endif
   13577 #define nir_store_ssbo_block_intel nir_build_store_ssbo_block_intel
   13578 #ifdef __cplusplus
   13579 #define nir_build_store_ssbo_ir3(build, src0, src1, src2, src3, ...) \
   13580 _nir_build_store_ssbo_ir3(build, src0, src1, src2, src3, _nir_store_ssbo_ir3_indices{0, __VA_ARGS__})
   13581 #else
   13582 #define nir_build_store_ssbo_ir3(build, src0, src1, src2, src3, ...) \
   13583 _nir_build_store_ssbo_ir3(build, src0, src1, src2, src3, (struct _nir_store_ssbo_ir3_indices){0, __VA_ARGS__})
   13584 #endif
   13585 #define nir_store_ssbo_ir3 nir_build_store_ssbo_ir3
   13586 #define nir_build_store_ssbo_masked_dxil _nir_build_store_ssbo_masked_dxil
   13587 #define nir_store_ssbo_masked_dxil nir_build_store_ssbo_masked_dxil
   13588 #define nir_build_store_tf_r600 _nir_build_store_tf_r600
   13589 #define nir_store_tf_r600 nir_build_store_tf_r600
   13590 #ifdef __cplusplus
   13591 #define nir_build_store_tlb_sample_color_v3d(build, src0, src1, ...) \
   13592 _nir_build_store_tlb_sample_color_v3d(build, src0, src1, _nir_store_tlb_sample_color_v3d_indices{0, __VA_ARGS__})
   13593 #else
   13594 #define nir_build_store_tlb_sample_color_v3d(build, src0, src1, ...) \
   13595 _nir_build_store_tlb_sample_color_v3d(build, src0, src1, (struct _nir_store_tlb_sample_color_v3d_indices){0, __VA_ARGS__})
   13596 #endif
   13597 #define nir_store_tlb_sample_color_v3d nir_build_store_tlb_sample_color_v3d
   13598 #define nir_build_terminate _nir_build_terminate
   13599 #define nir_terminate nir_build_terminate
   13600 #define nir_build_terminate_if _nir_build_terminate_if
   13601 #define nir_terminate_if nir_build_terminate_if
   13602 #define nir_build_terminate_ray _nir_build_terminate_ray
   13603 #define nir_terminate_ray nir_build_terminate_ray
   13604 #define nir_build_trace_ray _nir_build_trace_ray
   13605 #define nir_trace_ray nir_build_trace_ray
   13606 #define nir_build_trace_ray_commit_intel _nir_build_trace_ray_commit_intel
   13607 #define nir_trace_ray_commit_intel nir_build_trace_ray_commit_intel
   13608 #define nir_build_trace_ray_continue_intel _nir_build_trace_ray_continue_intel
   13609 #define nir_trace_ray_continue_intel nir_build_trace_ray_continue_intel
   13610 #define nir_build_trace_ray_initial_intel _nir_build_trace_ray_initial_intel
   13611 #define nir_trace_ray_initial_intel nir_build_trace_ray_initial_intel
   13612 #define nir_build_vote_all _nir_build_vote_all
   13613 #define nir_vote_all nir_build_vote_all
   13614 #define nir_build_vote_any _nir_build_vote_any
   13615 #define nir_vote_any nir_build_vote_any
   13616 #define nir_build_vote_feq _nir_build_vote_feq
   13617 #define nir_vote_feq nir_build_vote_feq
   13618 #define nir_build_vote_ieq _nir_build_vote_ieq
   13619 #define nir_vote_ieq nir_build_vote_ieq
   13620 #ifdef __cplusplus
   13621 #define nir_build_vulkan_resource_index(build, num_components, bit_size, src0, ...) \
   13622 _nir_build_vulkan_resource_index(build, num_components, bit_size, src0, _nir_vulkan_resource_index_indices{0, __VA_ARGS__})
   13623 #else
   13624 #define nir_build_vulkan_resource_index(build, num_components, bit_size, src0, ...) \
   13625 _nir_build_vulkan_resource_index(build, num_components, bit_size, src0, (struct _nir_vulkan_resource_index_indices){0, __VA_ARGS__})
   13626 #endif
   13627 #define nir_vulkan_resource_index nir_build_vulkan_resource_index
   13628 #ifdef __cplusplus
   13629 #define nir_build_vulkan_resource_reindex(build, bit_size, src0, src1, ...) \
   13630 _nir_build_vulkan_resource_reindex(build, bit_size, src0, src1, _nir_vulkan_resource_reindex_indices{0, __VA_ARGS__})
   13631 #else
   13632 #define nir_build_vulkan_resource_reindex(build, bit_size, src0, src1, ...) \
   13633 _nir_build_vulkan_resource_reindex(build, bit_size, src0, src1, (struct _nir_vulkan_resource_reindex_indices){0, __VA_ARGS__})
   13634 #endif
   13635 #define nir_vulkan_resource_reindex nir_build_vulkan_resource_reindex
   13636 #define nir_build_write_invocation_amd _nir_build_write_invocation_amd
   13637 #define nir_write_invocation_amd nir_build_write_invocation_amd
   13638 
   13639 #endif /* _NIR_BUILDER_OPCODES_ */
   13640