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  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_pipe_control.c 37 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
39 const struct intel_device_info *devinfo = &brw->screen->devinfo;
55 brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS));
59 brw->vtbl.emit_raw_pipe_control(brw, flags, NULL, 0, 0);
71 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
75 brw->vtbl.emit_raw_pipe_control(brw, flags, bo, offset, imm);
91 brw_emit_depth_stall_flushes(struct brw_context *brw)
93 const struct intel_device_info *devinfo = &brw->screen->devinfo
    [all...]
brw_ff_gs.h 40 brw_upload_ff_gs_prog(struct brw_context *brw);
gfx6_clip_state.c 38 brw_is_drawing_points(const struct brw_context *brw)
42 if (brw->ctx.Polygon.FrontMode == GL_POINT ||
43 brw->ctx.Polygon.BackMode == GL_POINT) {
47 if (brw->gs.base.prog_data) {
49 return brw_gs_prog_data(brw->gs.base.prog_data)->output_topology ==
51 } else if (brw->tes.base.prog_data) {
53 return brw_tes_prog_data(brw->tes.base.prog_data)->output_topology ==
57 return brw->primitive == _3DPRIM_POINTLIST;
62 brw_is_drawing_lines(const struct brw_context *brw)
66 if (brw->ctx.Polygon.FrontMode == GL_LINE |
    [all...]
brw_urb.c 100 static bool check_urb_layout(struct brw_context *brw)
102 brw->urb.vs_start = 0;
103 brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize;
104 brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize;
105 brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize
    [all...]
brw_compute.c 40 struct brw_context *brw = brw_context(ctx); local
49 brw_validate_textures(brw);
51 brw_predraw_resolve_inputs(brw, false, NULL);
56 brw_batch_require_space(brw, 600);
57 brw_require_statebuffer_space(brw, 2500);
58 brw_batch_save_state(brw);
59 fail_next = brw_batch_saved_state_is_empty(brw);
62 brw->batch.no_wrap = true;
63 brw_upload_compute_state(brw);
65 brw->vtbl.emit_compute_walker(brw)
100 struct brw_context *brw = brw_context(ctx); local
113 struct brw_context *brw = brw_context(ctx); local
135 struct brw_context *brw = brw_context(ctx); local
    [all...]
brw_gs_surface_state.c 39 brw_upload_gs_pull_constants(struct brw_context *brw)
41 struct brw_stage_state *stage_state = &brw->gs.base;
45 (struct brw_program *) brw->programs[MESA_SHADER_GEOMETRY];
51 const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
53 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_GEOMETRY);
55 brw_upload_pull_constants(brw, BRW_NEW_GS_CONSTBUF, &gp->program,
62 .brw = BRW_NEW_BATCH |
70 brw_upload_gs_ubo_surfaces(struct brw_context *brw)
72 struct gl_context *ctx = &brw->ctx;
79 struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data
    [all...]
brw_tcs_surface_state.c 39 brw_upload_tcs_pull_constants(struct brw_context *brw)
41 struct brw_stage_state *stage_state = &brw->tcs.base;
45 (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
51 const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
53 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
55 brw_upload_pull_constants(brw, BRW_NEW_TCS_CONSTBUF, &tcp->program,
62 .brw = BRW_NEW_BATCH |
70 brw_upload_tcs_ubo_surfaces(struct brw_context *brw)
72 struct gl_context *ctx = &brw->ctx;
79 struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data
    [all...]
brw_tes_surface_state.c 39 brw_upload_tes_pull_constants(struct brw_context *brw)
41 struct brw_stage_state *stage_state = &brw->tes.base;
45 (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
51 const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data;
53 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_EVAL);
55 brw_upload_pull_constants(brw, BRW_NEW_TES_CONSTBUF, &dp->program,
62 .brw = BRW_NEW_BATCH |
70 brw_upload_tes_ubo_surfaces(struct brw_context *brw)
72 struct gl_context *ctx = &brw->ctx;
79 struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data
    [all...]
brw_vs_surface_state.c 48 brw_upload_vs_pull_constants(struct brw_context *brw)
50 struct brw_stage_state *stage_state = &brw->vs.base;
54 (struct brw_program *) brw->programs[MESA_SHADER_VERTEX];
57 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
59 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_VERTEX);
61 brw_upload_pull_constants(brw, BRW_NEW_VS_CONSTBUF, &vp->program,
68 .brw = BRW_NEW_BATCH |
76 brw_upload_vs_ubo_surfaces(struct brw_context *brw)
78 struct gl_context *ctx = &brw->ctx;
83 brw_upload_ubo_surfaces(brw, prog, &brw->vs.base, brw->vs.base.prog_data)
    [all...]
brw_buffers.c 39 struct brw_context *const brw = brw_context(ctx); local
45 if (brw->driContext->driDrawablePriv)
46 dri2InvalidateDrawable(brw->driContext->driDrawablePriv);
47 brw_prepare_render(brw);
56 struct brw_context *const brw = brw_context(ctx); local
62 if (brw->driContext->driDrawablePriv)
63 dri2InvalidateDrawable(brw->driContext->driReadablePriv);
64 brw_prepare_render(brw);
brw_conditional_render.c 40 set_predicate_enable(struct brw_context *brw,
44 brw->predicate.state = BRW_PREDICATE_STATE_RENDER;
46 brw->predicate.state = BRW_PREDICATE_STATE_DONT_RENDER;
50 set_predicate_for_overflow_query(struct brw_context *brw,
54 if (!can_do_mi_math_and_lrr(brw->screen)) {
55 brw->predicate.state = BRW_PREDICATE_STATE_STALL_FOR_QUERY;
59 brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT;
65 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
67 hsw_overflow_result_to_gpr0(brw, query, count);
68 brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0))
133 struct brw_context *brw = brw_context(ctx); local
168 struct brw_context *brw = brw_context(ctx); local
    [all...]
brw_util.h 43 brw_get_line_width(struct brw_context *brw)
52 CLAMP(!_mesa_is_multisample_enabled(&brw->ctx) && !brw->ctx.Line.SmoothFlag
53 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
54 0.125f, brw->ctx.Const.MaxLineWidth);
56 if (!_mesa_is_multisample_enabled(&brw->ctx) && brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
brw_binding_tables.c 54 brw_upload_binding_table(struct brw_context *brw,
59 const struct intel_device_info *devinfo = &brw->screen->devinfo;
71 brw, &stage_state->surf_offset[
73 brw->shader_time.bo, 0, ISL_FORMAT_RAW,
74 brw->shader_time.bo->size, 1, RELOC_WRITE);
77 brw_state_batch(brw, prog_data->binding_table.size_bytes,
85 brw->ctx.NewDriverState |= BRW_NEW_BINDING_TABLE_POINTERS;
105 brw_vs_upload_binding_table(struct brw_context *brw)
108 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
109 brw_upload_binding_table(brw,
    [all...]
brw_reset.c 37 struct brw_context *brw = brw_context(ctx); local
38 struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx };
44 assert(brw->hw_ctx != 0);
50 if (brw->reset_count != 0)
53 if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0)
60 brw->reset_count = stats.reset_count;
69 brw->reset_count = stats.reset_count;
77 brw_check_for_reset(struct brw_context *brw)
79 struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx };
81 if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
gen6_clip_state.c 38 brw_is_drawing_points(const struct brw_context *brw)
42 if (brw->ctx.Polygon.FrontMode == GL_POINT ||
43 brw->ctx.Polygon.BackMode == GL_POINT) {
47 if (brw->gs.base.prog_data) {
49 return brw_gs_prog_data(brw->gs.base.prog_data)->output_topology ==
51 } else if (brw->tes.base.prog_data) {
53 return brw_tes_prog_data(brw->tes.base.prog_data)->output_topology ==
57 return brw->primitive == _3DPRIM_POINTLIST;
62 brw_is_drawing_lines(const struct brw_context *brw)
66 if (brw->ctx.Polygon.FrontMode == GL_LINE |
    [all...]
brw_pipe_control.c 37 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
39 const struct gen_device_info *devinfo = &brw->screen->devinfo;
55 brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS));
59 brw->vtbl.emit_raw_pipe_control(brw, flags, NULL, 0, 0);
71 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
75 brw->vtbl.emit_raw_pipe_control(brw, flags, bo, offset, imm);
91 brw_emit_depth_stall_flushes(struct brw_context *brw)
93 const struct gen_device_info *devinfo = &brw->screen->devinfo
    [all...]
brw_compute.c 40 struct brw_context *brw = brw_context(ctx); local
49 brw_validate_textures(brw);
51 brw_predraw_resolve_inputs(brw, false, NULL);
56 intel_batchbuffer_require_space(brw, 600);
57 brw_require_statebuffer_space(brw, 2500);
58 intel_batchbuffer_save_state(brw);
59 fail_next = intel_batchbuffer_saved_state_is_empty(brw);
62 brw->batch.no_wrap = true;
63 brw_upload_compute_state(brw);
65 brw->vtbl.emit_compute_walker(brw)
100 struct brw_context *brw = brw_context(ctx); local
112 struct brw_context *brw = brw_context(ctx); local
    [all...]
brw_urb.c 100 static bool check_urb_layout(struct brw_context *brw)
102 brw->urb.vs_start = 0;
103 brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize;
104 brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize;
105 brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize
    [all...]
brw_gs_surface_state.c 39 brw_upload_gs_pull_constants(struct brw_context *brw)
41 struct brw_stage_state *stage_state = &brw->gs.base;
45 (struct brw_program *) brw->programs[MESA_SHADER_GEOMETRY];
51 const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
53 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_GEOMETRY);
55 brw_upload_pull_constants(brw, BRW_NEW_GS_CONSTBUF, &gp->program,
62 .brw = BRW_NEW_BATCH |
70 brw_upload_gs_ubo_surfaces(struct brw_context *brw)
72 struct gl_context *ctx = &brw->ctx;
79 struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data
    [all...]
brw_tcs_surface_state.c 39 brw_upload_tcs_pull_constants(struct brw_context *brw)
41 struct brw_stage_state *stage_state = &brw->tcs.base;
45 (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
51 const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
53 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
55 brw_upload_pull_constants(brw, BRW_NEW_TCS_CONSTBUF, &tcp->program,
62 .brw = BRW_NEW_BATCH |
70 brw_upload_tcs_ubo_surfaces(struct brw_context *brw)
72 struct gl_context *ctx = &brw->ctx;
79 struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data
    [all...]
brw_tes_surface_state.c 39 brw_upload_tes_pull_constants(struct brw_context *brw)
41 struct brw_stage_state *stage_state = &brw->tes.base;
45 (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
51 const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data;
53 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_EVAL);
55 brw_upload_pull_constants(brw, BRW_NEW_TES_CONSTBUF, &dp->program,
62 .brw = BRW_NEW_BATCH |
70 brw_upload_tes_ubo_surfaces(struct brw_context *brw)
72 struct gl_context *ctx = &brw->ctx;
79 struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data
    [all...]
brw_vs_surface_state.c 48 brw_upload_vs_pull_constants(struct brw_context *brw)
50 struct brw_stage_state *stage_state = &brw->vs.base;
54 (struct brw_program *) brw->programs[MESA_SHADER_VERTEX];
57 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
59 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_VERTEX);
61 brw_upload_pull_constants(brw, BRW_NEW_VS_CONSTBUF, &vp->program,
68 .brw = BRW_NEW_BATCH |
76 brw_upload_vs_ubo_surfaces(struct brw_context *brw)
78 struct gl_context *ctx = &brw->ctx;
83 brw_upload_ubo_surfaces(brw, prog, &brw->vs.base, brw->vs.base.prog_data)
    [all...]
brw_conditional_render.c 41 set_predicate_enable(struct brw_context *brw,
45 brw->predicate.state = BRW_PREDICATE_STATE_RENDER;
47 brw->predicate.state = BRW_PREDICATE_STATE_DONT_RENDER;
51 set_predicate_for_overflow_query(struct brw_context *brw,
55 if (!can_do_mi_math_and_lrr(brw->screen)) {
56 brw->predicate.state = BRW_PREDICATE_STATE_STALL_FOR_QUERY;
60 brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT;
66 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
68 hsw_overflow_result_to_gpr0(brw, query, count);
69 brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0))
134 struct brw_context *brw = brw_context(ctx); local
169 struct brw_context *brw = brw_context(ctx); local
    [all...]
brw_util.h 43 brw_get_line_width(struct brw_context *brw)
52 CLAMP(!_mesa_is_multisample_enabled(&brw->ctx) && !brw->ctx.Line.SmoothFlag
53 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
54 0.125f, brw->ctx.Const.MaxLineWidth);
56 if (!_mesa_is_multisample_enabled(&brw->ctx) && brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
brw_binding_tables.c 54 brw_upload_binding_table(struct brw_context *brw,
59 const struct gen_device_info *devinfo = &brw->screen->devinfo;
71 brw, &stage_state->surf_offset[
73 brw->shader_time.bo, 0, ISL_FORMAT_RAW,
74 brw->shader_time.bo->size, 1, RELOC_WRITE);
77 brw_state_batch(brw, prog_data->binding_table.size_bytes,
85 brw->ctx.NewDriverState |= BRW_NEW_BINDING_TABLE_POINTERS;
105 brw_vs_upload_binding_table(struct brw_context *brw)
108 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
109 brw_upload_binding_table(brw,
    [all...]

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1 2 3 4 5 6 7 8 91011>>