Searched refs:brw_batch_emit (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c79 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) {
89 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
99 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_REG), lrr) {
118 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
157 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) {
193 brw_batch_emit(brw, GENX(3DSTATE_LINE_STIPPLE), line) {
218 brw_batch_emit(brw, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
499 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs) {
513 brw_batch_emit(brw, GENX(3DSTATE_VF_INSTANCING), vfi) {
518 brw_batch_emit(br
[all...]
H A DgenX_boilerplate.h134 #define brw_batch_emit(brw, cmd, name) \ macro
H A DgenX_pipe_control.c461 brw_batch_emit(brw, GENX(PIPE_CONTROL), pc) {
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c82 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) {
93 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
112 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
151 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) {
187 brw_batch_emit(brw, GENX(3DSTATE_LINE_STIPPLE), line) {
212 brw_batch_emit(brw, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
493 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs) {
507 brw_batch_emit(brw, GENX(3DSTATE_VF_INSTANCING), vfi) {
512 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs);
827 brw_batch_emit(br
[all...]
H A DgenX_boilerplate.h134 #define brw_batch_emit(brw, cmd, name) \ macro
H A DgenX_pipe_control.c465 brw_batch_emit(brw, GENX(PIPE_CONTROL), pc) {

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