Searched refs:brw_state_emit (Results 1 - 4 of 4) sorted by path

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_boilerplate.h152 #define brw_state_emit(brw, cmd, align, offset, name) \ macro
H A DgenX_state_upload.c1253 brw_state_emit(brw, GENX(DEPTH_STENCIL_STATE), 64, &ds_offset, ds) {
1295 brw_state_emit(brw, GENX(CLIP_STATE), 32, &brw->clip.state_offset, clip) {
1537 brw_state_emit(brw, GENX(SF_STATE), 64, &brw->sf.state_offset, sf) {
1833 brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) {
2182 brw_state_emit(brw, GENX(VS_STATE), 32, &stage_state->state_offset, vs) {
2705 brw_state_emit(brw, GENX(GS_STATE), 32, &brw->ff_gs.state_offset, gs) {
3463 brw_state_emit(brw, GENX(COLOR_CALC_STATE), 64, &brw->cc.state_offset, cc) {
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_boilerplate.h152 #define brw_state_emit(brw, cmd, align, offset, name) \ macro
H A DgenX_state_upload.c1243 brw_state_emit(brw, GENX(DEPTH_STENCIL_STATE), 64, &ds_offset, ds) {
1285 brw_state_emit(brw, GENX(CLIP_STATE), 32, &brw->clip.state_offset, clip) {
1527 brw_state_emit(brw, GENX(SF_STATE), 64, &brw->sf.state_offset, sf) {
1823 brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) {
2165 brw_state_emit(brw, GENX(VS_STATE), 32, &stage_state->state_offset, vs) {
2603 brw_state_emit(brw, GENX(GS_STATE), 32, &brw->ff_gs.state_offset, gs) {
3362 brw_state_emit(brw, GENX(COLOR_CALC_STATE), 64, &brw->cc.state_offset, cc) {

Completed in 22 milliseconds