| /xsrc/external/mit/fontconfig/dist/fc-lang/ |
| dsb.orth | 37 include cs.orth
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_cs.c | 30 tu_cs_init(struct tu_cs *cs,
37 memset(cs, 0, sizeof(*cs));
39 cs->device = device;
40 cs->mode = mode;
41 cs->next_bo_size = initial_size;
48 tu_cs_init_external(struct tu_cs *cs, struct tu_device *device,
51 memset(cs, 0, sizeof(*cs));
53 cs->device = device
[all...] |
| tu_cs.h | 33 tu_cs_init(struct tu_cs *cs,
39 tu_cs_init_external(struct tu_cs *cs, struct tu_device *device,
43 tu_cs_finish(struct tu_cs *cs);
46 tu_cs_begin(struct tu_cs *cs);
49 tu_cs_end(struct tu_cs *cs);
52 tu_cs_begin_sub_stream(struct tu_cs *cs, uint32_t size, struct tu_cs *sub_cs);
55 tu_cs_alloc(struct tu_cs *cs,
61 tu_cs_end_sub_stream(struct tu_cs *cs, struct tu_cs *sub_cs);
64 tu_cs_end_draw_state(struct tu_cs *cs, struct tu_cs *sub_cs)
66 struct tu_cs_entry entry = tu_cs_end_sub_stream(cs, sub_cs)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/ |
| tu_cs.c | 30 tu_cs_init(struct tu_cs *cs, enum tu_cs_mode mode, uint32_t initial_size)
34 memset(cs, 0, sizeof(*cs));
36 cs->mode = mode;
37 cs->next_bo_size = initial_size;
44 tu_cs_init_external(struct tu_cs *cs, uint32_t *start, uint32_t *end)
46 memset(cs, 0, sizeof(*cs));
48 cs->mode = TU_CS_MODE_EXTERNAL;
49 cs->start = cs->reserved_end = cs->cur = start
[all...] |
| tu_cs.h | 31 tu_cs_init(struct tu_cs *cs, enum tu_cs_mode mode, uint32_t initial_size);
34 tu_cs_init_external(struct tu_cs *cs, uint32_t *start, uint32_t *end);
37 tu_cs_finish(struct tu_device *dev, struct tu_cs *cs);
40 tu_cs_begin(struct tu_cs *cs);
43 tu_cs_end(struct tu_cs *cs);
47 struct tu_cs *cs,
52 tu_cs_end_sub_stream(struct tu_cs *cs, struct tu_cs *sub_cs);
56 struct tu_cs *cs,
60 tu_cs_reset(struct tu_device *dev, struct tu_cs *cs);
63 * Discard all entries. This allows \a cs to be reused while keeping th
[all...] |
| tu_meta_copy.c | 76 tu_cs_reserve_space(cmdbuf->device, &cmdbuf->cs, 10);
78 tu_cs_emit_pkt7(&cmdbuf->cs, CP_EVENT_WRITE, 1);
79 tu_cs_emit(&cmdbuf->cs, PC_CCU_INVALIDATE_COLOR);
81 tu_cs_emit_pkt7(&cmdbuf->cs, CP_EVENT_WRITE, 1);
82 tu_cs_emit(&cmdbuf->cs, LRZ_FLUSH);
84 tu_cs_emit_pkt7(&cmdbuf->cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
85 tu_cs_emit(&cmdbuf->cs, 0x0);
87 tu_cs_emit_wfi(&cmdbuf->cs);
89 tu_cs_emit_pkt4(&cmdbuf->cs, REG_A6XX_RB_CCU_CNTL, 1);
90 tu_cs_emit(&cmdbuf->cs, 0x10000000)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_cs.h | 34 struct radeon_cmdbuf *cs,
37 if (cs->max_dw - cs->cdw < needed)
38 ws->cs_grow(cs, needed);
39 return cs->cdw + needed;
42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
45 assert(cs->cdw + 2 + num <= cs->max_dw);
47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2)
[all...] |
| si_cmd_buffer.c | 40 struct radeon_cmdbuf *cs,
56 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
61 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
64 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
69 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
74 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
79 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
84 struct radeon_cmdbuf *cs)
86 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
87 radeon_emit(cs, 0)
384 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); local
1065 struct radeon_cmdbuf *cs = cmd_buffer->cs; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_cs.h | 35 radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed)
37 if (cs->max_dw - cs->cdw < needed)
38 ws->cs_grow(cs, needed);
39 return cs->cdw + needed;
43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
46 assert(cs->cdw + 2 + num <= cs->max_dw);
48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2)
[all...] |
| si_cmd_buffer.c | 37 struct radeon_cmdbuf *cs, unsigned raster_config,
50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs)
77 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
78 radeon_emit(cs, 0)
561 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); local
1442 struct radeon_cmdbuf *cs = cmd_buffer->cs; local
[all...] |
| /xsrc/external/mit/libdrm/dist/radeon/ |
| radeon_cs.h | 68 extern int radeon_cs_begin(struct radeon_cs *cs,
72 extern int radeon_cs_end(struct radeon_cs *cs,
76 extern int radeon_cs_emit(struct radeon_cs *cs);
77 extern int radeon_cs_destroy(struct radeon_cs *cs);
78 extern int radeon_cs_erase(struct radeon_cs *cs);
79 extern int radeon_cs_need_flush(struct radeon_cs *cs);
80 extern void radeon_cs_print(struct radeon_cs *cs, FILE *file);
81 extern void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit);
82 extern void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data);
83 extern int radeon_cs_write_reloc(struct radeon_cs *cs,
[all...] |
| radeon_cs.c | 14 radeon_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo,
18 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
28 radeon_cs_begin(struct radeon_cs *cs, uint32_t ndw,
31 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
36 radeon_cs_end(struct radeon_cs *cs,
39 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
43 drm_public int radeon_cs_emit(struct radeon_cs *cs)
45 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
49 drm_public int radeon_cs_destroy(struct radeon_cs *cs)
51 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_build_pm4.h | 35 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
38 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
39 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
40 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
43 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
45 radeon_set_config_reg_seq(cs, reg, 1);
46 radeon_emit(cs, value);
49 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
52 assert(cs->current.cdw + 2 + num <= cs->current.max_dw)
123 struct radeon_cmdbuf *cs = sctx->gfx_cs; local
144 struct radeon_cmdbuf *cs = sctx->gfx_cs; local
166 struct radeon_cmdbuf *cs = sctx->gfx_cs; local
192 struct radeon_cmdbuf *cs = sctx->gfx_cs; local
220 struct radeon_cmdbuf *cs = sctx->gfx_cs; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| cayman_msaa.c | 144 static void cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0])
[all...] |
| r600_cs.h | 45 struct radeon_cmdbuf *cs,
48 vram += (uint64_t)cs->used_vram_kb * 1024;
49 gtt += (uint64_t)cs->used_gart_kb * 1024;
60 * Add a buffer to the buffer list for the given command stream (CS).
62 * All buffers used by a CS must be added to the list. This tells the kernel
77 &ring->cs, rbo->buf,
108 !radeon_cs_memory_below_limit(rctx->screen, &ring->cs,
121 struct radeon_cmdbuf *cs = &ring->cs; local
126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0))
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| cayman_msaa.c | 144 static void cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0])
[all...] |
| r600_cs.h | 45 struct radeon_cmdbuf *cs,
48 vram += cs->used_vram;
49 gtt += cs->used_gart;
60 * Add a buffer to the buffer list for the given command stream (CS).
62 * All buffers used by a CS must be added to the list. This tells the kernel
77 ring->cs, rbo->buf,
108 !radeon_cs_memory_below_limit(rctx->screen, ring->cs,
121 struct radeon_cmdbuf *cs = ring->cs; local
126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0))
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/ |
| etnaviv_rasterizer.c | 38 struct etna_rasterizer_state *cs; local
44 cs = CALLOC_STRUCT(etna_rasterizer_state);
45 if (!cs)
48 cs->base = *so;
50 cs->PA_CONFIG = (so->flatshade ? VIVS_PA_CONFIG_SHADE_MODEL_FLAT : VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH) |
56 cs->PA_LINE_WIDTH = fui(so->line_width / 2.0f);
57 cs->PA_POINT_SIZE = fui(so->point_size / 2.0f);
58 cs->SE_DEPTH_SCALE = fui(so->offset_scale);
59 cs->SE_DEPTH_BIAS = fui((so->offset_units / 65535.0f) * 2.0f);
60 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/etnaviv/ |
| etnaviv_rasterizer.c | 38 struct etna_rasterizer_state *cs; local
44 cs = CALLOC_STRUCT(etna_rasterizer_state);
45 if (!cs)
48 cs->base = *so;
50 cs->PA_CONFIG = (so->flatshade ? VIVS_PA_CONFIG_SHADE_MODEL_FLAT : VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH) |
56 cs->PA_LINE_WIDTH = fui(so->line_width / 2.0f);
57 cs->PA_POINT_SIZE = fui(so->point_size / 2.0f);
58 cs->SE_DEPTH_SCALE = fui(so->offset_scale);
59 cs->SE_DEPTH_BIAS = fui(so->offset_units) / 65535.0f;
60 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE)
[all...] |
| etnaviv_state.c | 50 struct compiled_stencil_ref *cs = &ctx->stencil_ref; local
54 cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
56 cs->PE_STENCIL_CONFIG_EXT =
119 struct compiled_framebuffer_state *cs = &ctx->framebuffer; local
134 cs->PE_COLOR_FORMAT =
156 cs->PE_COLOR_ADDR = cbuf->reloc[0];
157 cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
162 cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
163 cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
166 cs->PE_COLOR_STRIDE = cbuf->surf.stride
343 struct compiled_scissor_state *cs = &ctx->scissor; local
364 struct compiled_viewport_state *cs = &ctx->viewport; local
415 struct compiled_set_vertex_buffer *cs = &so->cvb[idx]; local
489 struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state); local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/null/ |
| radv_null_cs.c | 71 struct radv_null_cs *cs = calloc(1, sizeof(struct radv_null_cs)); local
72 if (!cs)
75 cs->ws = radv_null_winsys(ws);
77 cs->base.buf = malloc(16384);
78 cs->base.max_dw = 4096;
79 if (!cs->base.buf) {
80 FREE(cs);
84 return &cs->base;
96 struct radv_null_cs *cs = radv_null_cs(rcs); local
97 FREE(cs->base.buf)
[all...] |
| /xsrc/external/mit/xorg-server/dist/composite/ |
| compinit.c | 58 CompScreenPtr cs = GetCompScreen(pScreen); local
61 free(cs->alternateVisuals);
63 pScreen->CloseScreen = cs->CloseScreen;
64 pScreen->InstallColormap = cs->InstallColormap;
65 pScreen->ChangeWindowAttributes = cs->ChangeWindowAttributes;
66 pScreen->ReparentWindow = cs->ReparentWindow;
67 pScreen->ConfigNotify = cs->ConfigNotify;
68 pScreen->MoveWindow = cs->MoveWindow;
69 pScreen->ResizeWindow = cs->ResizeWindow;
70 pScreen->ChangeBorderWidth = cs->ChangeBorderWidth
93 CompScreenPtr cs = GetCompScreen(pScreen); local
122 CompScreenPtr cs = GetCompScreen(pScreen); local
143 CompScreenPtr cs = GetCompScreen(pScreen); local
210 CompScreenPtr cs = GetCompScreen(pScreen); local
220 CompScreenPtr cs = GetCompScreen(pScreen); local
333 CompScreenPtr cs; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_cs.c | 257 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
260 if (cs->noop)
263 if (cs->next_fence) {
264 amdgpu_fence_reference(&fence, cs->next_fence);
268 fence = amdgpu_fence_create(cs->ctx,
269 cs->csc->ib[IB_MAIN].ip_type,
270 cs->csc->ib[IB_MAIN].ip_instance,
271 cs->csc->ib[IB_MAIN].ring);
275 amdgpu_fence_reference(&cs->next_fence, fence);
353 * recoveries), we can use the rejected cs count as a quick first check
516 struct amdgpu_cs_context *cs = acs->csc; local
541 struct amdgpu_cs_context *cs = acs->csc; local
591 struct amdgpu_cs_context *cs = acs->csc; local
654 struct amdgpu_cs_context *cs = acs->csc; local
953 struct amdgpu_cs *cs; local
1019 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
1076 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
1170 struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc; local
1205 struct amdgpu_cs_context *cs = acs->csc; local
1230 struct amdgpu_cs_context *cs = acs->csc; local
1250 struct amdgpu_cs_context *cs = acs->csc; local
1338 struct amdgpu_cs_context *cs = acs->csc; local
1349 struct amdgpu_cs_context *cs = acs->csc; local
1394 struct amdgpu_cs_context *cs = acs->cst; local
1651 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
1661 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
1799 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
1820 struct amdgpu_cs *cs = amdgpu_cs(rcs); local
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/ |
| radeon_drm_cs.c | 37 cs_add_buffer(cs, buf, read_domain, write_domain) adds a new relocation and
46 fails, the pipe driver flushes CS and tries do the validation again,
51 cs_write_reloc(cs, buf) just writes a reloc that has been added using
107 csc->cs.chunks = (uint64_t)(uintptr_t)csc->chunk_array;
157 struct radeon_drm_cs *cs; local
159 cs = CALLOC_STRUCT(radeon_drm_cs);
160 if (!cs) {
163 util_queue_fence_init(&cs->flush_completed);
165 cs->ws = ws;
166 cs->flush_cs = flush
339 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
383 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
390 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
436 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
486 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
549 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
706 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
723 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
750 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
785 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); local
[all...] |
| /xsrc/external/mit/xlsclients/dist/ |
| xlsclients.c | 292 child_wm_state *cs = closure; local
293 xcb_window_t orig = cs->orig_win;
294 xcb_connection_t *c = cs->c;
295 int verbose = cs->verbose;
296 int maxcmdlen = cs->maxcmdlen;
302 for (i = 0; i < cs->list_length; i++) {
304 gp_reply = xcb_get_property_reply(c, cs->prop_cookie[i], NULL);
308 print_client_properties(c, cs->win[i], cs->verbose, cs->maxcmdlen)
413 child_wm_state *cs = malloc(sizeof(*cs) + sizeof(*cs->prop_cookie) + sizeof(*cs->tree_cookie) + sizeof(*cs->win)); local
478 client_state *cs = closure; local
582 client_state *cs = malloc(sizeof(*cs)); local
[all...] |
