Searched refs:descriptors (Results 1 - 25 of 64) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.6.4.rst101 - radeonsi: rework how shader pointers to descriptors are set
102 - radeonsi: completely rework updating descriptors without CP DMA
H A D18.2.1.rst179 - radv: fix GPU hangs with 32-bit indirect descriptors
180 - radv: fix flushing indirect descriptors
181 - radv: fix setting global locations for indirect descriptors
H A D17.1.3.rst39 - radv: Dirty all descriptors sets when changing the pipeline.
H A D18.1.4.rst57 - anv/cmd_buffer: make descriptors dirty when emitting base state
H A D18.3.5.rst205 - radv: fix out-of-bounds access when copying descriptors BO list
206 - radv: don't copy buffer descriptors list for samplers
H A D13.0.3.rst135 - radeonsi: update all GSVS ring descriptors for new buffer allocations
H A D17.1.10.rst108 - anv: Fix descriptors copying
H A D17.2.2.rst114 - anv: Fix descriptors copying
H A D17.2.3.rst116 - anv/cmd_buffer: fix push descriptors with set > 0
H A D19.1.2.rst63 - radv: Only allocate supplied number of descriptors when variable.
H A D19.3.2.rst126 - radv/gfx10: fix the out-of-bounds check for vertex descriptors
H A D20.1.9.rst122 - radv: fix vertex buffer null descriptors
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c30 * descriptors in CPU memory and re-uploads a whole list if some slots have
37 * descriptors and the whole context would be unusable at that point.
40 * Also, uploading descriptors to newly allocated memory doesn't require
115 /* Initialize the array to NULL descriptors if the element size is 8. */
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
233 return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
872 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1105 /* Vertex buffer descriptors are the only ones which are uploaded
1167 * on performance (confirmed by testing). New descriptors ar
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H A Dsi_debug.c790 &sctx->descriptors[SI_DESCS_FIRST_SHADER +
1090 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1092 sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots,
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/lavapipe/
H A Dlvp_descriptor_set.c269 size_t size = sizeof(*set) + layout->size * sizeof(set->descriptors[0]);
287 struct lvp_descriptor *desc = set->descriptors;
371 &set->descriptors[bind_layout->descriptor_index];
466 &src->descriptors[src_layout->descriptor_index];
472 &dst->descriptors[dst_layout->descriptor_index];
615 &set->descriptors[bind_layout->descriptor_index];
H A Dlvp_private.h430 struct lvp_descriptor descriptors[0]; member in struct:lvp_descriptor_set
658 struct lvp_write_descriptor *descriptors; member in struct:lvp_cmd_push_descriptor_set
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_descriptor_set.c818 /* Combined image sampler descriptors can take up to 3 slots if they
871 "descriptors",
1114 (struct anv_buffer_view *) &set->descriptors[set->descriptor_count];
1116 /* By defining the descriptors to be zero now, we can later verify that
1119 memset(set->descriptors, 0,
1123 struct anv_descriptor *desc = set->descriptors;
1284 &set->descriptors[bind_layout->descriptor_index + element];
1412 &set->descriptors[bind_layout->descriptor_index + element];
1468 &set->descriptors[bind_layout->descriptor_index + element];
1508 /* If we're writing descriptors throug
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/xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
H A Dv3dv_descriptor_set.c96 return &set->descriptors[binding_layout->descriptor_index + array_index];
188 &set->descriptors[binding_layout->descriptor_index + array_index];
391 * texture sampler state. Note that not all the descriptors use it
978 struct v3dv_descriptor *descriptor = set->descriptors;
1060 struct v3dv_descriptor *src_descriptor = src_set->descriptors;
1061 struct v3dv_descriptor *dst_descriptor = dst_set->descriptors;
1210 set->descriptors +
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_descriptor_set.c663 /* Combined image sampler descriptors can take up to 3 slots if they
948 (struct anv_buffer_view *) &set->descriptors[layout->size];
951 /* By defining the descriptors to be zero now, we can later verify that
954 memset(set->descriptors, 0, sizeof(struct anv_descriptor) * layout->size);
957 struct anv_descriptor *desc = set->descriptors;
1106 &set->descriptors[bind_layout->descriptor_index + element];
1233 &set->descriptors[bind_layout->descriptor_index + element];
1283 &set->descriptors[bind_layout->descriptor_index + element];
1307 /* If we're writing descriptors through a push command, we need to
1441 &src->descriptors[src_layou
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c30 * descriptors in CPU memory and re-uploads a whole list if some slots have
37 * descriptors and the whole context would be unusable at that point.
40 * Also, uploading descriptors to newly allocated memory doesn't require
104 /* Initialize the array to NULL descriptors if the element size is 8. */
134 /* Skip the upload if no shader is using the descriptors. dirty_mask
135 * will stay dirty and the descriptors will be uploaded when there is
205 return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)];
914 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_INTERNAL];
1040 /* Initialize buffer descriptors, so that we don't have to do it at bind time. */
1153 return &sctx->descriptors[si_const_and_shader_buffer_descriptors_id
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H A Dsi_debug.c764 &sctx->descriptors[SI_DESCS_FIRST_SHADER + processor * SI_NUM_SHADER_DESCS];
1071 si_dump_descriptor_list(sctx->screen, &sctx->descriptors[SI_DESCS_INTERNAL], "", "RW buffers",
1072 4, sctx->descriptors[SI_DESCS_INTERNAL].num_active_slots, si_identity,
/xsrc/external/mit/MesaLib/dist/include/android_stub/hardware/
H A Dgralloc1.h367 * GRALLOC1_ERROR_NO_RESOURCES - no more descriptors can currently be created
689 * outNumFds - the number of file descriptors needed for transport
737 /* allocate(..., numDescriptors, descriptors, outBuffers)
743 * Each buffer will correspond to one of the descriptors passed into the
759 * GRALLOC1_ERROR_UNSUPPORTED if one or more of the descriptors can never be
763 * numDescriptors - the number of buffer descriptors, which must also be equal
765 * descriptors - the buffer descriptors to attempt to allocate
771 * GRALLOC1_ERROR_BAD_DESCRIPTOR - one of the descriptors does not refer to a
774 * than one backing store to satisfy all of the buffer descriptors
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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_descriptor_set.c129 /* Store block of offsets first, followed by the conversion descriptors (padded to the struct
575 memset(set->descriptors, 0, sizeof(struct radeon_winsys_bo *) * buffer_count);
897 /* allocate a set of buffers for each shader to contain descriptors */
1140 struct radeon_winsys_bo **buffer_list = set->descriptors;
1141 /* Immutable samplers are not copied into push descriptors when they are
1142 * allocated, so if we are writing push descriptors we have to copy the
1236 struct radeon_winsys_bo **src_buffer_list = src_set->descriptors;
1237 struct radeon_winsys_bo **dst_buffer_list = dst_set->descriptors;
1286 /* Sampler descriptors don't have a buffer list. */
1330 /* descriptorSetLayout should be ignored for push descriptors
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_private.h767 struct radeon_winsys_bo *descriptors[0]; member in struct:radv_descriptor_set
800 /* The number of descriptors to update */
806 /* In dwords. Not valid/used for dynamic descriptors */
819 /* For push descriptors */
1025 /* Vertex descriptors */
1122 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE]; member in struct:radv_cmd_buffer
1282 return &cmd_buffer->descriptors[bind_point];
H A Dradv_descriptor_set.c777 /* allocate a set of buffers for each shader to contain descriptors */
975 struct radeon_winsys_bo **buffer_list = set->descriptors;
976 /* Immutable samplers are not copied into push descriptors when they are
977 * allocated, so if we are writing push descriptors we have to copy the
1066 struct radeon_winsys_bo **src_buffer_list = src_set->descriptors;
1067 struct radeon_winsys_bo **dst_buffer_list = dst_set->descriptors;
1103 /* Sampler descriptors don't have a buffer list. */
1165 /* Immutable samplers are copied into push descriptors when they are pushed */
1225 struct radeon_winsys_bo **buffer_list = set->descriptors + templ->entry[i].buffer_offset;

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