Searched refs:dst_layout (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_meta_resolve_fs.c208 for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) { local in function:create_resolve_pipeline
209 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
239 }, &device->meta_state.alloc, rp + dst_layout);
460 unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout); local in function:radv_meta_resolve_fragment_image
466 if (!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout]) {
474 rp = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
H A Dradv_meta_blit2d.c292 unsigned dst_layout = radv_meta_dst_layout_from_layout(dst->current_layout); local in function:radv_meta_blit2d_normal_dst
305 .renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout],
788 for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) { local in function:blit2d_init_color_pipeline
789 if (!device->meta_state.blit2d_render_passes[fs_key][dst_layout]) {
790 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
821 }, &device->meta_state.alloc, &device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
H A Dradv_cmd_buffer.c57 VkImageLayout dst_layout,
4475 VkImageLayout dst_layout,
4486 if (radv_layout_is_htile_compressed(image, dst_layout,
4493 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4497 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4567 VkImageLayout dst_layout,
4590 if (radv_layout_dcc_compressed(image, dst_layout,
4614 VkImageLayout dst_layout,
4621 src_layout, dst_layout,
4630 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mas
4472 radv_handle_depth_image_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,VkImageLayout dst_layout,unsigned src_queue_mask,unsigned dst_queue_mask,const VkImageSubresourceRange * range) argument
4564 radv_init_color_image_metadata(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,VkImageLayout dst_layout,unsigned src_queue_mask,unsigned dst_queue_mask) argument
4611 radv_handle_color_image_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,VkImageLayout dst_layout,unsigned src_queue_mask,unsigned dst_queue_mask,const VkImageSubresourceRange * range) argument
4651 radv_handle_image_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,VkImageLayout dst_layout,uint32_t src_family,uint32_t dst_family,const VkImageSubresourceRange * range) argument
[all...]
H A Dradv_meta_blit.c350 unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout); local in function:meta_emit_blit
356 .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
/xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/
H A Dblorp_priv.h273 enum isl_msaa_layout dst_layout; member in struct:brw_blorp_blit_prog_key
H A Dblorp_blit.c1218 assert((key->dst_layout == ISL_MSAA_LAYOUT_NONE) ==
1246 key->rt_layout != key->dst_layout) {
1254 key->dst_layout);
1806 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1810 wm_prog_key->dst_layout = params->dst.surf.msaa_layout;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_blit2d.c265 unsigned dst_layout = radv_meta_dst_layout_from_layout(dst->current_layout); local in function:radv_meta_blit2d_normal_dst
281 .renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout],
723 for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) { local in function:blit2d_init_color_pipeline
724 if (!device->meta_state.blit2d_render_passes[fs_key][dst_layout]) {
725 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
784 &device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
H A Dradv_meta_resolve_fs.c169 for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) { local in function:create_resolve_pipeline
170 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
227 &device->meta_state.alloc, rp + dst_layout);
941 unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout); local in function:radv_meta_resolve_fragment_image
946 if (!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout]) {
955 rp = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
H A Dradv_cmd_buffer.c61 bool src_render_loop, VkImageLayout dst_layout,
7354 VkImageLayout dst_layout, bool dst_render_loop,
7368 radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop,
7373 !radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop,
7459 VkImageLayout dst_layout, bool dst_render_loop,
7478 radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, dst_layout,
7502 dst_layout, dst_render_loop, dst_queue_mask)) {
7521 VkImageLayout src_layout, VkImageLayout dst_layout, unsigned dst_queue_mask)
7524 (dst_layout == VK_IMAGE_LAYOUT_PRESENT_SRC_KHR ||
7542 VkImageLayout dst_layout, boo
7352 radv_handle_depth_image_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,bool src_render_loop,VkImageLayout dst_layout,bool dst_render_loop,unsigned src_queue_mask,unsigned dst_queue_mask,const VkImageSubresourceRange * range,struct radv_sample_locations_state * sample_locs) argument
7457 radv_init_color_image_metadata(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,bool src_render_loop,VkImageLayout dst_layout,bool dst_render_loop,unsigned src_queue_mask,unsigned dst_queue_mask,const VkImageSubresourceRange * range) argument
7520 radv_retile_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,VkImageLayout dst_layout,unsigned dst_queue_mask) argument
7540 radv_handle_color_image_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,bool src_render_loop,VkImageLayout dst_layout,bool dst_render_loop,unsigned src_queue_mask,unsigned dst_queue_mask,const VkImageSubresourceRange * range) argument
7619 radv_handle_image_transition(struct radv_cmd_buffer * cmd_buffer,struct radv_image * image,VkImageLayout src_layout,bool src_render_loop,VkImageLayout dst_layout,bool dst_render_loop,uint32_t src_family,uint32_t dst_family,const VkImageSubresourceRange * range,struct radv_sample_locations_state * sample_locs) argument
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H A Dradv_meta_blit.c285 unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout); local in function:meta_emit_blit
292 .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_priv.h319 enum isl_msaa_layout dst_layout; member in struct:brw_blorp_blit_prog_key
H A Dblorp_blit.c1201 assert((key->dst_layout == ISL_MSAA_LAYOUT_NONE) ==
1235 key->rt_layout != key->dst_layout) {
1243 key->dst_layout);
1932 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1936 key->dst_layout = params->dst.surf.msaa_layout;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_descriptor_set.c1691 const struct anv_descriptor_set_binding_layout *dst_layout = local in function:anv_UpdateDescriptorSets
1694 &dst->descriptors[dst_layout->descriptor_index];
1699 memcpy(dst->desc_mem.map + dst_layout->descriptor_offset +
1706 &dst->buffer_views[dst_layout->buffer_view_index +
1718 assert(dst_layout->data & ANV_DESCRIPTOR_BUFFER_VIEW);
1738 assert(desc_size == anv_descriptor_size(dst_layout));
1739 memcpy(dst->desc_mem.map + dst_layout->descriptor_offset +
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_descriptor_set.c1444 const struct anv_descriptor_set_binding_layout *dst_layout = local in function:anv_UpdateDescriptorSets
1447 &dst->descriptors[dst_layout->descriptor_index];
1455 memcpy(dst->desc_mem.map + dst_layout->descriptor_offset +
1463 assert(desc_size == anv_descriptor_size(dst_layout));
1464 memcpy(dst->desc_mem.map + dst_layout->descriptor_offset +
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/lavapipe/
H A Dlvp_descriptor_set.c469 const struct lvp_descriptor_set_binding_layout *dst_layout = local in function:lvp_UpdateDescriptorSets
472 &dst->descriptors[dst_layout->descriptor_index];

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