Searched refs:gfx9_eop_bug_va (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c841 uint64_t gfx9_eop_bug_va)
862 radeon_emit(cs, gfx9_eop_bug_va);
863 radeon_emit(cs, gfx9_eop_bug_va >> 32);
964 enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va)
1092 EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va);
1140 enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va)
1149 sqtt_flush_bits, gfx9_eop_bug_va);
1174 gfx9_eop_bug_va);
1257 EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va);
1355 &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va);
838 si_cs_emit_write_event_eop(struct radeon_cmdbuf * cs,enum chip_class chip_class,bool is_mec,unsigned event,unsigned event_flags,unsigned dst_sel,unsigned data_sel,uint64_t va,uint32_t new_fence,uint64_t gfx9_eop_bug_va) argument
962 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va) argument
1138 si_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va) argument
[all...]
H A Dradv_private.h1502 uint64_t gfx9_eop_bug_va; member in struct:radv_cmd_buffer
1534 uint64_t gfx9_eop_bug_va);
1541 enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va);
H A Dradv_query.c1538 cmd_buffer->gfx9_eop_bug_va);
1684 cmd_buffer->gfx9_eop_bug_va);
H A Dradv_cmd_buffer.c549 cmd_buffer->gfx9_eop_bug_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
550 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
552 radv_emit_clear_data(cmd_buffer, V_370_PFP, cmd_buffer->gfx9_eop_bug_va, 16 * num_db);
694 cmd_buffer->gfx9_eop_bug_va);
7860 cmd_buffer->gfx9_eop_bug_va);
8409 cmd_buffer->gfx9_eop_bug_va);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c672 uint64_t gfx9_eop_bug_va)
693 radeon_emit(cs, gfx9_eop_bug_va);
694 radeon_emit(cs, gfx9_eop_bug_va >> 32);
780 uint64_t gfx9_eop_bug_va)
812 gfx9_eop_bug_va);
883 gfx9_eop_bug_va);
989 cmd_buffer->gfx9_eop_bug_va);
665 si_cs_emit_write_event_eop(struct radeon_cmdbuf * cs,enum chip_class chip_class,bool is_mec,unsigned event,unsigned event_flags,unsigned data_sel,uint64_t va,uint32_t new_fence,uint64_t gfx9_eop_bug_va) argument
774 si_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,uint64_t gfx9_eop_bug_va) argument
H A Dradv_private.h1137 uint64_t gfx9_eop_bug_va; member in struct:radv_cmd_buffer
1172 uint64_t gfx9_eop_bug_va);
1181 uint64_t gfx9_eop_bug_va);
H A Dradv_query.c1614 cmd_buffer->gfx9_eop_bug_va);
1749 cmd_buffer->gfx9_eop_bug_va);
H A Dradv_cmd_buffer.c352 cmd_buffer->gfx9_eop_bug_va =
354 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
507 flags, cmd_buffer->gfx9_eop_bug_va);
4877 cmd_buffer->gfx9_eop_bug_va);

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