Searched refs:insns (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/pixman/dist/pixman/
H A Dpixman-arm-detect-win32.asm6 ;; I don't think the msvc arm asm knows how to do SIMD insns
15 ;; I don't think the msvc arm asm knows how to do NEON insns
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/
H A Dnv30_vertprog.c41 FREE(vp->insns);
42 vp->insns = NULL;
108 inst = vp->insns[reloc->location].data;
117 inst = vp->insns[reloc->location].data;
151 inst = vp->insns[reloc->location].data;
160 inst = vp->insns[reloc->location].data;
201 PUSH_DATAp(push, vp->insns[i].data, 4);
H A Dnvfx_vertprog.c301 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
302 vpc->vpi = &vp->insns[vp->nr_insns - 1];
776 vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
778 vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
962 struct util_dynarray insns; variable in typeref:struct:util_dynarray
993 util_dynarray_init(&insns, NULL);
1018 unsigned idx = insns.size >> 2;
1019 util_dynarray_append(&insns, unsigned, vp->nr_insns);
1030 util_dynarray_append(&insns, unsigne
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H A Dnv30_state.h90 struct nv30_vertprog_exec *insns; member in struct:nv30_vertprog
H A Dnvfx_fragprog.c1068 struct util_dynarray insns; variable in typeref:struct:util_dynarray
1095 util_dynarray_init(&insns, NULL);
1105 util_dynarray_append(&insns, unsigned, fp->insn_len);
1115 util_dynarray_append(&insns, unsigned, fp->insn_len);
1120 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1122 util_dynarray_fini(&insns);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv30/
H A Dnv30_vertprog.c41 FREE(vp->insns);
42 vp->insns = NULL;
108 inst = vp->insns[reloc->location].data;
117 inst = vp->insns[reloc->location].data;
151 inst = vp->insns[reloc->location].data;
160 inst = vp->insns[reloc->location].data;
201 PUSH_DATAp(push, vp->insns[i].data, 4);
H A Dnvfx_vertprog.c302 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
303 vpc->vpi = &vp->insns[vp->nr_insns - 1];
777 vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
779 vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
963 struct util_dynarray insns; variable in typeref:struct:util_dynarray
994 util_dynarray_init(&insns, NULL);
1019 unsigned idx = insns.size >> 2;
1020 util_dynarray_append(&insns, unsigned, vp->nr_insns);
1031 util_dynarray_append(&insns, unsigne
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H A Dnv30_state.h90 struct nv30_vertprog_exec *insns; member in struct:nv30_vertprog
H A Dnvfx_fragprog.c1068 struct util_dynarray insns; variable in typeref:struct:util_dynarray
1095 util_dynarray_init(&insns, NULL);
1105 util_dynarray_append(&insns, unsigned, fp->insn_len);
1115 util_dynarray_append(&insns, unsigned, fp->insn_len);
1120 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1122 util_dynarray_fini(&insns);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_ra.cpp291 ArrayList insns; member in class:nv50_ir::RegAlloc
716 bool allocateRegisters(ArrayList& insns);
973 GCRA::coalesce(ArrayList& insns) argument
975 bool ret = doCoalesce(insns, JOIN_MASK_PHI);
983 ret = doCoalesce(insns, JOIN_MASK_UNION | JOIN_MASK_TEX);
993 ret = doCoalesce(insns, JOIN_MASK_UNION);
1000 return doCoalesce(insns, JOIN_MASK_MOV);
1075 GCRA::doCoalesce(ArrayList& insns, unsigned int mask) argument
1079 for (n = 0; n < insns.getSize(); ++n) {
1081 Instruction *insn = reinterpret_cast<Instruction *>(insns
1212 buildRIG(ArrayList & insns) argument
1473 allocateRegisters(ArrayList & insns) argument
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H A Dnv50_ir_lowering_nvc0.cpp499 ArrayList insns; local in function:nv50_ir::NVC0LegalizePostRA::insertTextureBarriers
501 fn->orderInstructions(insns);
504 bbFirstTex.resize(fn->allBBlocks.getSize(), insns.getSize());
505 bbFirstUse.resize(fn->allBBlocks.getSize(), insns.getSize());
515 for (int i = 0; i < insns.getSize(); ++i) {
516 Instruction *tex = reinterpret_cast<Instruction *>(insns.get(i));
524 insns.clear();
H A Dnv50_ir_from_tgsi.cpp1053 struct tgsi_full_instruction *insns; member in class:tgsi::Source
1115 if (insns)
1116 FREE(insns);
1131 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
1132 sizeof(insns[0]));
1133 if (!insns)
1175 insns[insnCount++] = parse.FullToken.FullInstruction;
3137 tgsi::Instruction insn(&code->insns[ip]);
4351 if (!handleInstruction(&code->insns[ip]))
H A Dnv50_ir_emit_gm107.cpp4390 ArrayList insns; local in function:nv50_ir::SchedDataCalculatorGM107::visit
4392 func->orderInstructions(insns);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_ra.cpp292 ArrayList insns; member in class:nv50_ir::RegAlloc
759 bool allocateRegisters(ArrayList& insns);
1018 GCRA::coalesce(ArrayList& insns) argument
1020 bool ret = doCoalesce(insns, JOIN_MASK_PHI);
1028 ret = doCoalesce(insns, JOIN_MASK_UNION | JOIN_MASK_TEX);
1040 ret = doCoalesce(insns, JOIN_MASK_UNION);
1047 return doCoalesce(insns, JOIN_MASK_MOV);
1122 GCRA::doCoalesce(ArrayList& insns, unsigned int mask) argument
1126 for (n = 0; n < insns.getSize(); ++n) {
1128 Instruction *insn = reinterpret_cast<Instruction *>(insns
1262 buildRIG(ArrayList & insns) argument
1522 allocateRegisters(ArrayList & insns) argument
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H A Dnv50_ir_from_tgsi.cpp998 struct tgsi_full_instruction *insns; member in class:tgsi::Source
1063 : insns(NULL), info(info), info_out(info_out), clipVertexOutput(-1),
1079 if (insns)
1080 FREE(insns);
1091 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
1092 sizeof(insns[0]));
1093 if (!insns)
1128 insns[insnCount++] = parse.FullToken.FullInstruction;
3160 tgsi::Instruction insn(&code->insns[ip]);
4384 if (!handleInstruction(&code->insns[i
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H A Dnv50_ir_lowering_nvc0.cpp510 ArrayList insns; local in function:nv50_ir::NVC0LegalizePostRA::insertTextureBarriers
512 fn->orderInstructions(insns);
515 bbFirstTex.resize(fn->allBBlocks.getSize(), insns.getSize());
516 bbFirstUse.resize(fn->allBBlocks.getSize(), insns.getSize());
526 for (int i = 0; i < insns.getSize(); ++i) {
527 Instruction *tex = reinterpret_cast<Instruction *>(insns.get(i));
535 insns.clear();
H A Dnv50_ir_emit_gm107.cpp4313 ArrayList insns; local in function:nv50_ir::SchedDataCalculatorGM107::visit
4315 func->orderInstructions(insns);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/
H A Dnouveau_compiler.c60 *code = (unsigned *)vp.insns;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/
H A Dnouveau_compiler.c60 *code = (unsigned *)vp.insns;
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json4144 "description": "nir_to_tgsi: Track our TGSI insns in blocks before emitting tokens.",
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