| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/ |
| H A D | vc4_qpu_validate.c | 113 vc4_qpu_validate(uint64_t *insts, uint32_t num_inst) argument
127 uint64_t inst = insts[i];
166 if (writes_reg(insts[j], QPU_W_VPM) ||
167 reads_reg(insts[j], QPU_R_VARY) ||
168 reads_reg(insts[j], QPU_R_UNIF) ||
169 reads_reg(insts[j], QPU_R_VPM)) {
170 fail_instr(insts[j], "last 3 instructions "
178 if (writes_reg(insts[j], 14) ||
179 reads_reg(insts[j], 14)) {
180 fail_instr(insts[
[all...] |
| H A D | vc4_qir_live_variables.c | 33 struct qinst *insts[4]; member in struct:partial_update_state
160 if (state->insts[i] &&
161 state->insts[i]->cond ==
165 state->insts[i] = inst;
180 if (state->insts[i] && state->insts[i]->cond)
181 state->insts[i] = NULL;
|
| H A D | vc4_qpu.h | 240 vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/ |
| H A D | vc4_qpu_validate.c | 115 vc4_qpu_validate(uint64_t *insts, uint32_t num_inst) argument
129 uint64_t inst = insts[i];
168 if (writes_reg(insts[j], QPU_W_VPM) ||
169 reads_reg(insts[j], QPU_R_VARY) ||
170 reads_reg(insts[j], QPU_R_UNIF) ||
171 reads_reg(insts[j], QPU_R_VPM)) {
172 fail_instr(insts[j], "last 3 instructions "
180 if (writes_reg(insts[j], 14) ||
181 reads_reg(insts[j], 14)) {
182 fail_instr(insts[
[all...] |
| H A D | vc4_qir_live_variables.c | 33 struct qinst *insts[4]; member in struct:partial_update_state
148 if (state->insts[i] &&
149 state->insts[i]->cond ==
153 state->insts[i] = inst;
168 if (state->insts[i] && state->insts[i]->cond)
169 state->insts[i] = NULL;
|
| H A D | vc4_qpu.h | 240 vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
|
| /xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/ |
| H A D | lower_const_arrays_to_uniforms.cpp | 48 lower_const_array_visitor(exec_list *insts, unsigned s) argument
50 instructions = insts;
|
| /xsrc/external/mit/MesaLib/dist/src/compiler/glsl/ |
| H A D | lower_const_arrays_to_uniforms.cpp | 48 lower_const_array_visitor(exec_list *insts, unsigned s, argument
51 instructions = insts;
|
| /xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/ |
| H A D | vir_live_variables.c | 32 struct qinst *insts[4]; member in struct:partial_update_state
160 /* XXXif (state->insts[i] &&
161 state->insts[i]->cond ==
166 state->insts[i] = inst;
181 if (state->insts[i] &&
182 (state->insts[i]->qpu.flags.ac != V3D_QPU_COND_NONE ||
183 state->insts[i]->qpu.flags.mc != V3D_QPU_COND_NONE))
184 state->insts[i] = NULL;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_dataflow_deadcode.c | 155 struct instruction_state * insts = &s->Instructions[inst->IP]; local in function:update_instruction
167 insts->WriteMask |= usedmask;
178 insts->WriteALUResult = 1;
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_dataflow_deadcode.c | 155 struct instruction_state * insts = &s->Instructions[inst->IP]; local in function:update_instruction
167 insts->WriteMask |= usedmask;
178 insts->WriteALUResult = 1;
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/ |
| H A D | lower_x86.cpp | 440 std::vector<Instruction*> insts; local in function:SwrJit::LowerX86::runOnFunction
443 insts.push_back(&i);
446 for (auto* I : insts)
|