Searched refs:is_mec (Results 1 - 4 of 4) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | si_cmd_buffer.c | 667 bool is_mec,
677 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
690 if (chip_class == GFX9 && !is_mec) {
749 bool is_mec,
753 if (is_mec || is_gfx9) {
756 PKT3_SHADER_TYPE_S(is_mec));
778 bool is_mec,
807 is_mec,
908 !is_mec) {
915 si_emit_acquire_mem(cs, is_mec, chip_clas
665 si_cs_emit_write_event_eop(struct radeon_cmdbuf * cs,enum chip_class chip_class,bool is_mec,unsigned event,unsigned event_flags,unsigned data_sel,uint64_t va,uint32_t new_fence,uint64_t gfx9_eop_bug_va) argument
748 si_emit_acquire_mem(struct radeon_cmdbuf * cs,bool is_mec,bool is_gfx9,unsigned cp_coher_cntl) argument
774 si_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,uint64_t gfx9_eop_bug_va) argument
[all...] |
| H A D | radv_private.h | 1167 bool is_mec,
1179 bool is_mec,
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | si_cmd_buffer.c | 838 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec, argument
846 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
859 if (chip_class == GFX9 && !is_mec) {
885 if (is_mec) {
940 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) argument
942 if (is_mec || is_gfx9) {
944 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec));
963 uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits,
1120 !is_mec) {
1139 uint64_t flush_va, bool is_mec, enu
962 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va) argument
1138 si_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum chip_class chip_class,uint32_t * flush_cnt,uint64_t flush_va,bool is_mec,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va) argument
[all...] |
| H A D | radv_private.h | 1531 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec,
1539 uint32_t *fence_ptr, uint64_t va, bool is_mec,
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