| /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/ |
| H A D | midgard_emit.c | 507 unreachable("unexpected ldst opcode");
603 midgard_load_store_word ldst = ins->load_store; local in function:load_store_from_instr
604 ldst.op = ins->op;
606 if (OP_IS_STORE(ldst.op)) {
607 ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1;
609 ldst.reg = SSA_REG_FROM_FIXED(ins->dest);
616 ldst.swizzle = 0;
617 ldst.swizzle |= ins->swizzle[3][0] & 3;
618 ldst.swizzle |= (SSA_REG_FROM_FIXED(ins->src[3]) & 1 ? 1 : 0) << 2;
622 ldst
[all...] |
| H A D | midgard_ra.c | 182 unsigned *ldst = calloc(sz, 1); local in function:mir_lower_special_reads
203 mark_node_class(ldst, ins->src[0]);
204 mark_node_class(ldst, ins->src[1]);
205 mark_node_class(ldst, ins->src[2]);
206 mark_node_class(ldst, ins->src[3]);
235 bool is_ldst = BITSET_TEST(ldst, i);
241 * but not ldst or texr. Load/store ops (ldst) cannot read
312 free(ldst);
|
| H A D | midgard_schedule.c | 703 bool ldst = (instructions[i]->type == TAG_LOAD_STORE_4); local in function:mir_choose_instruction
738 if (ldst && mir_pipeline_count(instructions[i]) + predicate->pipeline_count > 2)
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_peephole.cpp | 2684 updateLdStOffset(Instruction *ldst, int32_t offset, Function *fn) argument
2686 if (offset != ldst->getSrc(0)->reg.data.offset) {
2687 if (ldst->getSrc(0)->refCount() > 1)
2688 ldst->setSrc(0, cloneShallow(fn, ldst->getSrc(0)));
2689 ldst->getSrc(0)->reg.data.offset = offset;
2710 bool overlaps(const Instruction *ldst) const;
2714 inline void set(const Instruction *ldst);
2741 void addRecord(Instruction *ldst);
2912 MemoryOpt::Record::set(const Instruction *ldst) argument
3170 Instruction *ldst, *next; local in function:nv50_ir::MemoryOpt::runOpt
[all...] |
| H A D | nv50_ir_emit_gk110.cpp | 2384 uses64bitAddress(const Instruction *ldst) argument
2386 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
2387 ldst->src(0).isIndirect(0) &&
2388 ldst->getIndirect(0, 0)->reg.size == 8;
|
| H A D | nv50_ir_ra.cpp | 1074 LValue *ldst = dst->asLValue(); local in function:nv50_ir::copyCompound
1077 if (ldst->compound && !lsrc->compound) {
1079 lsrc = ldst;
1080 ldst = swap;
1083 ldst->compound = lsrc->compound;
1084 ldst->compMask = lsrc->compMask;
|
| H A D | nv50_ir_emit_nvc0.cpp | 1864 uses64bitAddress(const Instruction *ldst) argument
1866 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1867 ldst->src(0).isIndirect(0) &&
1868 ldst->getIndirect(0, 0)->reg.size == 8;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_peephole.cpp | 2631 updateLdStOffset(Instruction *ldst, int32_t offset, Function *fn) argument
2633 if (offset != ldst->getSrc(0)->reg.data.offset) {
2634 if (ldst->getSrc(0)->refCount() > 1)
2635 ldst->setSrc(0, cloneShallow(fn, ldst->getSrc(0)));
2636 ldst->getSrc(0)->reg.data.offset = offset;
2657 bool overlaps(const Instruction *ldst) const;
2661 inline void set(const Instruction *ldst);
2688 void addRecord(Instruction *ldst);
2849 MemoryOpt::Record::set(const Instruction *ldst) argument
3107 Instruction *ldst, *next; local in function:nv50_ir::MemoryOpt::runOpt
[all...] |
| H A D | nv50_ir_emit_gk110.cpp | 2377 uses64bitAddress(const Instruction *ldst) argument
2379 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
2380 ldst->src(0).isIndirect(0) &&
2381 ldst->getIndirect(0, 0)->reg.size == 8;
|
| H A D | nv50_ir_ra.cpp | 1027 LValue *ldst = dst->asLValue(); local in function:nv50_ir::copyCompound
1030 if (ldst->compound && !lsrc->compound) {
1032 lsrc = ldst;
1033 ldst = swap;
1036 ldst->compound = lsrc->compound;
1037 ldst->compMask = lsrc->compMask;
|
| H A D | nv50_ir_emit_nvc0.cpp | 1857 uses64bitAddress(const Instruction *ldst) argument
1859 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1860 ldst->src(0).isIndirect(0) &&
1861 ldst->getIndirect(0, 0)->reg.size == 8;
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 19.3.0.rst | 347 - pan/midgard: Fix component count handling for ldst
355 - pan/midgard: Add mir_schedule_texture/ldst/alu helpers
|
| H A D | 21.2.0.rst | 2840 - pan/mdg: improve ldst opcode names and add missing ops
2842 - pan/mdg: properly encode/decode ldst instructions
|