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    Searched refs:midgard_reg_mode_32 (Results 1 - 9 of 9) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/
midgard_print_constant.c 84 case midgard_reg_mode_32:
disassemble.c 381 case midgard_reg_mode_32:
545 midgard_reg_mode_32 : midgard_reg_mode_16,
1415 midgard_reg_mode_32, 0xFF);
1472 midgard_reg_mode_32, 0xFF);
1791 print_vec_swizzle(fp, texture->swizzle, midgard_src_passthrough, midgard_reg_mode_32, 0xFF);
1798 print_vec_swizzle(fp, texture->in_reg_swizzle, exp, midgard_reg_mode_32, 0xFF);
1823 print_vec_swizzle(fp, swizzle, exp, midgard_reg_mode_32, 0xFF);
midgard.h 256 midgard_reg_mode_32 = 2, enumerator in enum:__anon2819
midgard_ops.c 203 #define M32 midgard_reg_mode_32
midgard_emit.c 319 } else if (reg_mode == midgard_reg_mode_32 && sz == 16) {
midgard_compile.c 2607 return midgard_reg_mode_32;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/panfrost/midgard/
disassemble.c 211 } else if (mode == midgard_reg_mode_32) {
285 case midgard_reg_mode_32:
313 bool modeable = (mode == midgard_reg_mode_32) || (mode == midgard_reg_mode_16);
315 bool uppable = !overriden_up || (mode == midgard_reg_mode_32);
327 case midgard_reg_mode_32:
midgard.h 169 midgard_reg_mode_32 = 2, enumerator in enum:__anon3900
midgard_compile.c 319 .reg_mode = midgard_reg_mode_32,
1124 .reg_mode = midgard_reg_mode_32,
1152 .reg_mode = midgard_reg_mode_32,
1423 .reg_mode = midgard_reg_mode_32,
1696 .reg_mode = midgard_reg_mode_32,
3547 .reg_mode = midgard_reg_mode_32,

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