Searched refs:nir_dest_is_divergent (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_instruction_selection_setup.cpp465 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
728 type = nir_dest_is_divergent(intrinsic->dest) ? RegType::vgpr : RegType::sgpr;
748 RegType type = nir_dest_is_divergent(tex->dest) ? RegType::vgpr : RegType::sgpr;
779 if (nir_dest_is_divergent(phi->dest)) {
H A Daco_instruction_selection.cpp1051 bool use_valu = s_op == aco_opcode::num_opcodes || nir_dest_is_divergent(instr->dest.dest) ||
5373 if (!nir_dest_is_divergent(instr->dest))
8404 assert(nir_dest_is_divergent(instr->dest) == expected_divergent);
8465 if (!nir_dest_is_divergent(instr->dest)) {
8562 if (!nir_dest_is_divergent(instr->dest)) {
9838 bool logical = !dst.is_linear() || nir_dest_is_divergent(instr->dest);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline.c3244 return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32
3247 return bit_size == 8 || !nir_dest_is_divergent(alu->dest.dest) ? 32 : 0;
3268 return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32
/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir.h1005 nir_dest_is_divergent(nir_dest dest) function in typeref:typename:bool

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