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    Searched refs:nir_store_ssbo (Results 1 - 6 of 6) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
si_shaderlib_nir.c 99 nir_store_ssbo(&b, value, zero, dst_offset, .write_mask=0x1, .align_mul=1);
145 nir_store_ssbo(&b, clear_value, zero, offset, .write_mask=0x1, .align_mul=2);
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_query.c 79 nir_store_ssbo(b, nir_vec2(b, value32, nir_imm_int(b, 0)), dst_buf, offset, .write_mask = 0x3,
84 nir_store_ssbo(b, value32, dst_buf, offset, .write_mask = 0x1, .align_mul = 4);
209 nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .write_mask = 0x1,
214 nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base,
326 nir_store_ssbo(&b, result, dst_buf, nir_load_var(&b, output_offset), .write_mask = 0x1,
331 nir_store_ssbo(&b, nir_u2u32(&b, result), dst_buf, nir_load_var(&b, output_offset),
359 nir_store_ssbo(&b, nir_imm_int64(&b, 0), dst_buf, output_elem, .write_mask = 0x1,
364 nir_store_ssbo(&b, nir_imm_int(&b, 0), dst_buf, output_elem, .write_mask = 0x1, .align_mul = 4);
487 nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .write_mask = 0x3,
492 nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf, output_base
    [all...]
radv_meta_buffer.c 25 nir_store_ssbo(&b, swizzled_load, dst_buf, offset, .write_mask = 0xf,
48 nir_store_ssbo(&b, load, dst_buf, offset, .write_mask = 0xf, .access = ACCESS_NON_READABLE,
radv_meta_copy_vrs_htile.c 137 nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .write_mask = 0x1,
radv_meta_clear.c 1075 nir_store_ssbo(&b, data, buf, offset, .write_mask = 0xf, .access = ACCESS_NON_READABLE,
  /xsrc/external/mit/MesaLib/src/compiler/nir/
nir_builder_opcodes.h 13569 #define nir_store_ssbo nir_build_store_ssbo macro

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