| /xsrc/external/mit/libFS/dist/src/ |
| H A D | FSQGlyphs.c | 70 FSOffset *offs; local in function:FSQueryXBitmaps8 96 offs = FSmallocarray(reply.num_chars, sizeof(FSOffset)); 97 *offsets = offs; 98 if (!offs) 103 FSfree(offs); 112 FSfree(offs); 118 offs->position = local_offs.position; 119 offs->length = local_offs.length; 120 offs++; 141 FSOffset *offs; local in function:FSQueryXBitmaps16 [all...] |
| /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/ |
| H A D | bi_opt_push_ubo.c | 113 for (unsigned offs = 0; offs < range; ++offs) { local in function:bi_pick_ubo 116 .offset = (r + offs) * 4
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| H A D | disassemble.c | 262 int64_t offs = 0; local in function:dump_pc_imm 266 offs = sx64; 269 offs = sx32[1]; 272 offs = sx32[high32]; 278 assert((offs & 15) == 0); 279 fprintf(fp, "clause_%" PRId64, branch_offset + (offs / 16)); 286 if (offs == 0)
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| /xsrc/external/mit/MesaLib/dist/src/panfrost/util/ |
| H A D | pan_ir.c | 136 pan_lookup_pushed_ubo(struct panfrost_ubo_push *push, unsigned ubo, unsigned offs) argument 140 .offset = offs
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| H A D | pan_ir.h | 138 pan_lookup_pushed_ubo(struct panfrost_ubo_push *push, unsigned ubo, unsigned offs);
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| /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/ |
| H A D | mir_promote_uniforms.c | 112 for (unsigned offs = 0; offs < 4; ++offs) { local in function:mir_pick_ubo 115 .offset = (vec4 * 16) + (offs * 4)
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| /xsrc/external/mit/xf86-video-openchrome/dist/src/ |
| H A D | via_exa_h2.c | 369 unsigned long offs; local in function:viaIsAGP 372 offs = ((unsigned long)pPix->devPrivate.ptr 375 if ((offs - pVia->scratchOffset) < pVia->agpSize) { 376 *offset = offs + pVia->agpAddr;
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| H A D | via_exa_h6.c | 382 unsigned long offs; local in function:viaIsAGP 385 offs = ((unsigned long)pPix->devPrivate.ptr 388 if ((offs - pVia->scratchOffset) < pVia->agpSize) { 389 *offset = offs + pVia->agpAddr;
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| /xsrc/external/mit/pixman/dist/pixman/ |
| H A D | pixman-fast-path.c | 1978 #define A1_FILL_MASK(n, offs) (((1U << (n)) - 1) << (32 - (offs) - (n))) 1980 #define A1_FILL_MASK(n, offs) (((1U << (n)) - 1) << (offs)) 1984 pixman_fill1_line (uint32_t *dst, int offs, int width, int v) argument 1986 if (offs) 1988 int leading_pixels = 32 - offs; 1992 *dst |= A1_FILL_MASK (width, offs); 1994 *dst &= ~A1_FILL_MASK (width, offs); 2000 *dst++ |= A1_FILL_MASK (leading_pixels, offs); 2033 int offs = x & 31; local in function:pixman_fill1 [all...] |
| H A D | pixman-rvv.c | 2796 #define A1_FILL_MASK(n, offs) (((1U << (n)) - 1) << (offs)) 2803 pixman_fill1_line (uint32_t *dst, int offs, int width, int v) argument 2805 if (offs) 2807 int leading_pixels = 32 - offs; 2811 *dst |= A1_FILL_MASK (width, offs); 2813 *dst &= ~A1_FILL_MASK (width, offs); 2819 *dst++ |= A1_FILL_MASK (leading_pixels, offs); 2821 *dst++ &= ~A1_FILL_MASK (leading_pixels, offs); 2852 int offs local in function:rvv_fill1 [all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/ |
| H A D | radeon_vce_40_2_2.c | 54 uint32_t offs = enc->cs->current.cdw - enc->task_info_idx + 3; local in function:task_info 56 enc->cs->current.buf[enc->task_info_idx] = offs;
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| H A D | radeon_vce_52.c | 582 uint32_t offs = enc->cs->current.cdw - enc->task_info_idx + 3; local in function:task_info 584 enc->cs->current.buf[enc->task_info_idx] = offs;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/ |
| H A D | radeon_vce_40_2_2.c | 51 uint32_t offs = enc->cs.current.cdw - enc->task_info_idx + 3; local in function:task_info 53 enc->cs.current.buf[enc->task_info_idx] = offs;
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| H A D | radeon_vce_52.c | 590 uint32_t offs = enc->cs.current.cdw - enc->task_info_idx + 3; local in function:task_info 592 enc->cs.current.buf[enc->task_info_idx] = offs;
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| /xsrc/external/mit/xf86-video-sis/dist/src/ |
| H A D | sis_cursor.c | 91 int i, offs = 0; local in function:UpdateHWCursorStatus 93 if(pSiS->SecondHead) offs = 8; 96 pSiS->HWCursorBackup[offs + i] = SIS_MMIO_IN32(pSiS->IOBase, 0x8500 + ((offs + i) << 2));
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_from_nir.cpp | 2073 Value *offs[2]; local in function:__anon42ea91d60110::Converter::visit 2075 offs[c] = getScratch(); 2076 mkOp2(OP_MIN, TYPE_F32, offs[c], getSrc(&insn->src[0], c), loadImm(NULL, 0.4375f)); 2077 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f)); 2078 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f)); 2079 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]); 2081 mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[ [all...] |
| H A D | nv50_ir_from_tgsi.cpp | 3095 Value *offs[2]; local in function:__anon9636d7c40110::Converter::handleINTERP 3097 offs[c] = getScratch(); 3098 mkOp2(OP_MIN, TYPE_F32, offs[c], fetchSrc(1, c), loadImm(NULL, 0.4375f)); 3099 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f)); 3100 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f)); 3101 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]); 3104 offs[ [all...] |
| H A D | nv50_ir_lowering_nvc0.cpp | 1119 Value *offs[2] = {NULL, NULL}; local in function:nv50_ir::NVC0LoweringPass::handleTEX 1123 bld.mkMov(offs[n / 2] = bld.getScratch(), i->offset[n][c].get()); 1126 offs[n / 2], 1129 offs[n / 2]); 1132 i->setSrc(s, offs[0]); 1133 if (offs[1]) 1134 i->setSrc(s + 1, offs[1]);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_from_nir.cpp | 1803 Value *offs[2]; local in function:__anonbe08c7a90110::Converter::visit 1805 offs[c] = getScratch(); 1806 mkOp2(OP_MIN, TYPE_F32, offs[c], getSrc(&insn->src[0], c), loadImm(NULL, 0.4375f)); 1807 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f)); 1808 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f)); 1809 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]); 1811 mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[ [all...] |
| H A D | nv50_ir_from_tgsi.cpp | 3118 Value *offs[2]; local in function:__anon751bc7f70210::Converter::handleINTERP 3120 offs[c] = getScratch(); 3121 mkOp2(OP_MIN, TYPE_F32, offs[c], fetchSrc(1, c), loadImm(NULL, 0.4375f)); 3122 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f)); 3123 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f)); 3124 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]); 3127 offs[ [all...] |
| H A D | nv50_ir_lowering_nvc0.cpp | 1133 Value *offs[2] = {NULL, NULL}; local in function:nv50_ir::NVC0LoweringPass::handleTEX 1137 bld.mkMov(offs[n / 2] = bld.getScratch(), i->offset[n][c].get()); 1140 offs[n / 2], 1143 offs[n / 2]); 1146 i->setSrc(s, offs[0]); 1147 if (offs[1]) 1148 i->setSrc(s + 1, offs[1]);
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/main/ |
| H A D | texcompress_fxt1.c | 1324 GLuint offs = 0 + (y + 0) * srcRowStride; local in function:fxt1_encode 1327 lines[0] = &data[offs]; 1331 offs += 8 * comps;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/asahi/ |
| H A D | agx_state.c | 936 unsigned offs = ALIGN_POT(binary.size, 256); local in function:agx_update_shader 938 memcpy(((uint8_t *) compiled->bo->ptr.cpu) + offs, packed_varyings, packed_varying_sz); 939 offs += packed_varying_sz;
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| /xsrc/external/mit/MesaLib/dist/src/util/format/ |
| H A D | u_format_fxt1.c | 1202 uint32_t offs = 0 + (y + 0) * srcRowStride; local in function:fxt1_encode 1205 lines[0] = &data[offs]; 1209 offs += 8 * comps;
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| /xsrc/external/mit/MesaLib/dist/docs/isl/ |
| H A D | formats.rst | 16 a binary form, and each makes different trade-offs. By default, most color
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