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  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_crtc.c 146 RADEONComputePLL_old(RADEONPLLPtr pll,
155 uint32_t min_ref_div = pll->min_ref_div;
156 uint32_t max_ref_div = pll->max_ref_div;
157 uint32_t min_post_div = pll->min_post_div;
158 uint32_t max_post_div = pll->max_post_div;
161 uint32_t best_vco = pll->best_vco;
176 min_ref_div = max_ref_div = pll->reference_div;
180 uint32_t pll_in = pll->reference_freq / mid;
181 if (pll_in < pll->pll_in_min)
183 else if (pll_in > pll->pll_in_max
    [all...]
radeon_tv.c 230 /* XXX: these should probably be OUTPLL to avoid various PLL errata */
480 ErrorF("Restore TV PLL\n");
618 RADEONPLLPtr pll = &info->pll; local
635 if (pll->reference_freq == 2700)
640 if (pll->reference_freq == 2700)
741 RADEONPLLPtr pll = &info->pll; local
764 if (pll->reference_freq == 2700)
769 if (pll->reference_freq == 2700
1083 RADEONPLLPtr pll = &info->pll; local
1124 RADEONPLLPtr pll = &info->pll; local
1187 RADEONPLLPtr pll = &info->pll; local
1228 RADEONPLLPtr pll = &info->pll; local
    [all...]
radeon_driver.c 579 /* This workaround is necessary on rv200 and RS200 or PLL
614 /* Read PLL register */
629 /* Write PLL information */
1010 RADEONPLLPtr pll = &info->pll; local
1202 pll->reference_div = ref_div;
1203 pll->xclk = xclk;
1204 pll->reference_freq = xtal;
1206 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, "
1215 RADEONPLLPtr pll = &info->pll local
    [all...]
radeon_mm_i2c.c 367 RADEONPLLPtr pll = &(info->pll); local
439 nm=(pll->reference_freq * 40000.0)/(1.0*I2C_CLOCK_FREQ);
444 nm=(pll->reference_freq * 40000.0)/(4.0*I2C_CLOCK_FREQ);
448 nm=(pll->reference_freq * 10000.0)/(4.0*I2C_CLOCK_FREQ);
451 nm=(pll->xclk * 40000.0)/(1.0*I2C_CLOCK_FREQ);
460 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref=%d M=0x%02x N=0x%02x timing=0x%02x\n", pll->reference_freq, pPriv->radeon_M, pPriv->radeon_N, pPriv->radeon_i2c_timing);
radeon_bios.c 981 /* Read PLL parameters from BIOS block. Default to typical values if there
986 RADEONPLLPtr pll = &info->pll; local
1001 pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e);
1002 pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10);
1003 pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12);
1004 pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16);
1007 pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36);
1008 pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a);
1010 pll->pll_in_min = 40
    [all...]
radeon_atombios.c 136 "TMDS PLL ChargePump", MSG_FORMAT_DEC},
138 "TMDS PLL DutyCycle", MSG_FORMAT_DEC},
140 "TMDS PLL VCO Gain", MSG_FORMAT_DEC},
142 "TMDS PLL VoltageSwing", MSG_FORMAT_DEC},
1490 prescale = (info->pll.reference_freq * 10) / i2c_clock;
2267 RADEONPLLPtr pll = &info->pll; local
2282 pll->xclk = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMaxPixelClock);
2283 pll->pll_in_min = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMinPixelClockPLL_Input);
2284 pll->pll_in_max = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMaxPixelClockPLL_Input)
    [all...]
radeon_pm.c 51 RADEONPLLPtr pll = &info->pll; local
66 req_clock += pll->reference_freq;
67 req_clock /= (2 * pll->reference_freq);
72 req_clock *= pll->reference_freq;
legacy_crtc.c 278 * 3 parts, each part having a fixed PLL gain value.
297 /* Write PLL registers */
307 /* apparently restoring the pll causes a hang??? */
313 pllGain = RADEONComputePLLGain(info->pll.reference_freq,
319 This appears to related to the PLL divider registers (fail to lock?).
321 In this case we really don't need to fiddle with PLL registers.
430 pllGain = RADEONComputePLLGain(info->pll.reference_freq,
598 /* Read PLL registers */
619 /* Read PLL registers */
1186 /* Define PLL registers for requested video mode *
    [all...]
radeon_probe.h 456 uint32_t pll[2][15]; member in struct:dce4_state
484 struct avivo_pll_state pll[2]; member in struct:avivo_state
640 /* Computed values for PLL */
647 /* PLL registers */
atombios_crtc.c 339 /* ErrorF("Picked PLL %d\n", radeon_crtc->pll_id); */
475 info->pll.reference_div = args.v3.sOutput.ucRefDiv;
479 info->pll.post_div = args.v3.sOutput.ucPostDiv;
645 RADEONComputePLL(crtc, &info->pll, sclock, &temp,
650 "crtc(%d) Clock: mode %d, PLL %lu\n",
653 "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), fracfbdiv %u, pdiv %u\n",
713 /* ErrorF("Set CRTC %d PLL success\n", radeon_crtc->crtc_id); */
717 ErrorF("Set CRTC %d PLL failed\n", radeon_crtc->crtc_id);
radeon.h 856 RADEONPLLRec pll; member in struct:__anon6814
1171 RADEONPLLPtr pll, unsigned long freq,
radeon_video.c 1379 RADEONPLLPtr pll = &(info->pll); local
1410 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "video decoder type is 0x%04x (BIOS value) versus 0x%04x (current PLL setting)\n",
1411 t->video_decoder_type, pll->xclk);
1452 switch((info->RageTheatreCrystal>=0)?info->RageTheatreCrystal:pll->reference_freq){
2591 /* I suspect we may need a usleep after writing to the PLL. if you play a video too soon
  /xsrc/external/mit/xf86-video-r128/dist/src/
r128_crtc.c 348 /* Define PLL registers for requested video mode. */
350 R128PLLPtr pll, double dot_clock)
377 if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
378 if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
382 if (save->pll_output_freq >= pll->min_pll_freq
383 && save->pll_output_freq <= pll->max_pll_freq) break;
387 save->feedback_div = R128Div(pll->reference_div * save->pll_output_freq,
388 pll->reference_freq)
    [all...]
r128_driver.c 364 /* Read PLL information */
598 /* Read PLL parameters from BIOS block. Default to typical values if there
603 R128PLLPtr pll = &info->pll; local
607 does set up the PLL registers properly and we can use
617 pll->reference_freq = 2950;
618 pll->min_pll_freq = 12500;
619 pll->max_pll_freq = 25000;
623 pll->reference_div =
629 pll->xclk = R128Div((2 * Nx * pll->reference_freq)
    [all...]
r128.h 217 /* Computed values for PLL */
223 /* PLL registers */
330 R128PLLRec pll; member in struct:__anon170
  /xsrc/external/mit/xf86-video-nv/dist/src/
nv_hw.c 126 unsigned int pll, N, M, MB, NB, P; local
129 pll = pNv->PMC[0x4020/4];
130 P = (pll >> 16) & 0x07;
131 pll = pNv->PMC[0x4024/4];
132 M = pll & 0xFF;
133 N = (pll >> 8) & 0xFF;
140 MB = (pll >> 16) & 0xFF;
141 NB = (pll >> 24) & 0xFF;
145 pll = pNv->PMC[0x4000/4];
146 P = (pll >> 16) & 0x07
684 unsigned int M, N, P, pll, MClk, NVClk, memctrl; local
    [all...]
nv_dac.c 224 nvReg->vpll = nvReg->pll;
225 nvReg->vpll2 = nvReg->pll;
nv_type.h 50 U032 pll; member in struct:_riva_hw_state
riva_hw.c 528 unsigned int M, N, P, pll, MClk; local
530 pll = chip->PRAMDAC[0x00000504/4];
531 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
568 * Calculate the Video Clock parameters for the PLL.
  /xsrc/external/mit/xf86-video-siliconmotion/dist/src/
smi_501.c 57 int32_t pll, int32_t value);
239 int32_t pll; local
251 pll = clock.value;
254 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
259 pll = clock.value;
262 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
286 int32_t pll; local
298 pll = clock.value;
303 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
325 int32_t pll; local
    [all...]
smi_501.h 220 * 30:30 PLL SELECT
368 * 13:14 PLL Recovery.
373 * 19:22 PLL Recovery Clock Divider.
378 * Internally, the PLL recovery time counters are based on a 32 us
439 * 4:5 PLL Input frequency
448 int32_t pll : bits( 4, 5); member in struct:_MSOCRegRec::__anon9330::__anon9331
454 /* Programmable PLL Control
457 * 0:7 PLL M Value
458 * 8:14 PLL N Value
459 * 15:15 PLL Output Divided by 2
    [all...]
  /xsrc/external/mit/xf86-video-openchrome/dist/src/
via_outputs.c 794 union pllparams pll; local
796 pll.packed = clock;
797 dtz = pll.params.dtz;
798 dr = pll.params.dr;
799 dn = pll.params.dn;
800 dm = pll.params.dm;
  /xsrc/external/mit/xf86-video-openchrome/dist/tools/
registers.c 376 { 0x03, "ECK Pll Power Control", },
377 { 0x0c, "LCK PLL Power Control", },
378 { 0x30, "VCK PLL Power Control", },
394 { 0x04, "LCDCK PLL Locked Detect", },
395 { 0x08, "VCK PLL Locked Detect", },
396 { 0x10, "ECL PLL Locked Detect", },
397 { 0x60, "PLL Frequency Division Select for Testing", },
410 { 0x01, "Reset ECK PLL", },
411 { 0x02, "Reset VCK PLL", },
412 { 0x04, "Reset LCDCK PLL", },
858 enum pll { enum
    [all...]
  /xsrc/external/mit/xf86-video-geode/dist/src/gfx/
vid_1200.c 82 * SC1200 PLL TABLE
262 unsigned long value, pll; local
284 pll = READ_VID32(SC1200_VID_MISC);
285 WRITE_VID32(SC1200_VID_MISC, pll | SC1200_PLL_POWER_NORMAL);
  /xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
vid_1200.c 132 * SC1200 PLL TABLE
421 unsigned long value, pll; local
443 pll = READ_VID32(SC1200_VID_MISC);
444 WRITE_VID32(SC1200_VID_MISC, pll | SC1200_PLL_POWER_NORMAL);

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