Searched refs:pll_flags (Results 1 - 5 of 5) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Datombios_crtc.c365 int pll_flags = 0; local in function:atombios_adjust_pll
384 pll_flags |= /*RADEON_PLL_USE_FRAC_FB_DIV |*/
387 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
389 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
391 pll_flags |= RADEON_PLL_LEGACY;
394 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
396 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
412 pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
418 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
420 pll_flags |
594 int pll_flags = 0; local in function:atombios_crtc_set_pll
[all...]
H A Dlegacy_crtc.c1773 int pll_flags = RADEON_PLL_LEGACY; local in function:legacy_crtc_mode_set
1778 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
1780 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
1794 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
1796 pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV);
1816 RADEONInitPLLRegisters(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
1830 RADEONInitPLL2Registers(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vg.c1679 vg_set_clock_frequency(unsigned long frequency, unsigned long pll_flags) argument
1694 if (!(pll_flags & VG_PLL_MANUAL)) {
1717 if (pll_flags & VG_PLL_DIVIDE_BY_2)
1719 if (pll_flags & VG_PLL_DIVIDE_BY_4)
1721 if (pll_flags & VG_PLL_BYPASS)
1723 if (pll_flags & VG_PLL_VIP_CLOCK)
2687 vg_state->pll_flags = 0;
2700 vg_state->pll_flags |= VG_PLL_MANUAL;
2703 vg_state->pll_flags |= VG_PLL_DIVIDE_BY_2;
2705 vg_state->pll_flags |
[all...]
H A Dcim_rtns.h186 unsigned long pll_flags);
H A Dcim_parm.h535 unsigned long pll_flags; member in struct:tagVGSaveRestore

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