Searched refs:post_div (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_crtc.c169 uint32_t post_div; local in function:RADEONComputePLL_old
190 min_post_div = max_post_div = pll->post_div;
197 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
200 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
205 if ((post_div == 5) ||
206 (post_div == 7) ||
207 (post_div == 9) ||
208 (post_div
323 calc_fb_div(RADEONPLLPtr pll,unsigned long freq,int flags,int post_div,int ref_div,int * fb_div,int * fb_div_frac) argument
352 calc_fb_ref_div(RADEONPLLPtr pll,unsigned long freq,int flags,int post_div,int * fb_div,int * fb_div_frac,int * ref_div) argument
393 int fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; local in function:RADEONComputePLL_new
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H A Dlegacy_crtc.c1204 } *post_div, post_divs[] = { local in function:RADEONInitPLLRegisters
1237 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1238 if (post_div->divider == post_divider)
1242 if (!post_div->divider) {
1244 post_div = &post_divs[0];
1250 save->post_div = post_divider;
1258 save->post_div);
1269 save->ppll_div_3 = (save->feedback_div | (post_div
1295 } *post_div, post_divs[] = { local in function:RADEONInitPLL2Registers
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H A Dradeon_pm.c48 int *post_div)
54 *post_div = 8;
57 *post_div = 4;
60 *post_div = 2;
63 *post_div = 1;
74 req_clock /= *post_div;
84 int ref_div, fb_div, post_div; local in function:RADEONSetEngineClock
91 eng_clock = calc_eng_mem_clock(pScrn, eng_clock, ref_div, &fb_div, &post_div);
123 if ((eng_clock * post_div) >= 90000)
143 switch (post_div) {
44 calc_eng_mem_clock(ScrnInfoPtr pScrn,uint32_t req_clock,int ref_div,int * fb_div,int * post_div) argument
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H A Datombios_crtc.c479 info->pll.post_div = args.v3.sOutput.ucPostDiv;
588 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:atombios_crtc_set_pll
646 &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags);
655 (unsigned int)fb_div, (unsigned int)frac_fb_div, (unsigned int)post_div);
670 args.v2.ucPostDiv = post_div;
680 args.v3.ucPostDiv = post_div;
692 args.v5.ucPostDiv = post_div;
H A Dradeon_probe.h385 uint32_t post_div; member in struct:avivo_pll_state
645 int post_div; member in struct:__anon297917400b08
H A Dradeon_driver.c4931 state->pll[0].post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
4940 state->pll[1].post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
4949 state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV);
4956 state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV);
4963 state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV);
5344 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll[0].post_div);
5353 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll[1].post_div);
5366 OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div);
5373 OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div);
5380 OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div);
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H A Dradeon.h293 uint32_t post_div; member in struct:__anonb194aea90308
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_crtc.c357 } *post_div, local in function:R128InitPLLRegisters
378 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
379 save->pll_output_freq = post_div->divider * freq;
387 save->post_div = post_div->divider;
394 save->post_div));
397 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
413 } *post_div, local in function:R128InitPLL2Registers
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H A Dr128.h224 int post_div; member in struct:__anona5d7874c0208

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