| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | brw_reg_type.c | 88 enum hw_reg_type reg_type; member in struct:hw_type
161 enum hw_3src_reg_type reg_type; member in struct:hw_3src_type
216 assert(table[type].reg_type != (enum hw_reg_type)INVALID);
217 return table[type].reg_type;
246 if (table[i].reg_type == (enum hw_reg_type)hw_type) {
264 assert(gen7_hw_3src_type[type].reg_type != (enum hw_3src_reg_type)INVALID);
265 return gen7_hw_3src_type[type].reg_type;
277 assert(gen10_hw_3src_align1_type[type].reg_type != (enum hw_3src_reg_type)INVALID);
278 return gen10_hw_3src_align1_type[type].reg_type;
291 if (gen7_hw_3src_type[i].reg_type
[all...] |
| H A D | brw_fs_nir.cpp | 347 const brw_reg_type reg_type = reg->bit_size == 8 ? BRW_REGISTER_TYPE_B : local in function:fs_visitor::nir_emit_impl
349 nir_locals[reg->index] = bld.vgrf(reg_type, size);
1838 const brw_reg_type reg_type = local in function:fs_visitor::nir_emit_load_const
1840 fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
1885 const brw_reg_type reg_type = local in function:fs_visitor::get_nir_src
1887 reg = bld.vgrf(reg_type, src.ssa->num_components);
1934 const brw_reg_type reg_type = local in function:fs_visitor::get_nir_dest
1940 bld.vgrf(reg_type, dest.ssa.num_components);
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| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | brw_reg_type.c | 92 enum hw_reg_type reg_type; member in struct:hw_type
239 enum hw_3src_reg_type reg_type; member in struct:hw_3src_type
356 assert(table[type].reg_type != (enum hw_reg_type)INVALID);
357 return table[type].reg_type;
396 if (table[i].reg_type == (enum hw_reg_type)hw_type) {
425 assert(table[type].reg_type != (enum hw_3src_reg_type)INVALID);
426 return table[type].reg_type;
439 return gfx125_hw_3src_type[type].reg_type;
442 return gfx12_hw_3src_type[type].reg_type;
445 return gfx11_hw_3src_type[type].reg_type;
[all...] |
| H A D | brw_fs_nir.cpp | 314 const brw_reg_type reg_type = reg->bit_size == 8 ? BRW_REGISTER_TYPE_B : local in function:fs_visitor::nir_emit_impl
316 nir_locals[reg->index] = bld.vgrf(reg_type, size);
2018 const brw_reg_type reg_type = local in function:fs_visitor::nir_emit_load_const
2020 fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
2065 const brw_reg_type reg_type = local in function:fs_visitor::get_nir_src
2067 reg = bld.vgrf(reg_type, src.ssa->num_components);
2114 const brw_reg_type reg_type = local in function:fs_visitor::get_nir_dest
2120 bld.vgrf(reg_type, dest.ssa.num_components);
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/perf/ |
| H A D | gen_perf.py | 656 for reg_type, reg_length in register_lengths.items():
659 reg_type, reg_length))
695 for reg_type, reg_length in register_lengths.items():
696 c(".{0} = {1}_{2}_{3},".format(reg_type, gen.chipset, set.underscore_name, reg_type))
697 c(".n_{0} = 0, /* Determined at runtime */".format(reg_type))
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_flow.c | 146 LLVMBuildBitCast(builder, value, mask->reg_type, ""),
147 LLVMConstNull(mask->reg_type),
170 mask->reg_type = LLVMIntTypeInContext(gallivm->context, type.width * type.length);
|
| H A D | lp_bld_flow.h | 75 LLVMTypeRef reg_type; member in struct:lp_build_mask_context
|
| H A D | lp_bld_tgsi_soa.c | 429 LLVMTypeRef reg_type = LLVMIntTypeInContext(gallivm->context, local in function:lp_exec_endloop
470 LLVMBuildBitCast(builder, mask->exec_mask, reg_type, ""),
471 LLVMConstNull(reg_type), "i1cond");
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_flow.h | 75 LLVMTypeRef reg_type; member in struct:lp_build_mask_context
|
| H A D | lp_bld_flow.c | 146 LLVMBuildBitCast(builder, value, mask->reg_type, ""),
147 LLVMConstNull(mask->reg_type),
170 mask->reg_type = LLVMIntTypeInContext(gallivm->context, type.width * type.length);
|
| H A D | lp_bld_ir_common.c | 279 LLVMTypeRef reg_type = LLVMIntTypeInContext(gallivm->context, local in function:lp_exec_endloop
320 LLVMBuildBitCast(builder, mask->exec_mask, reg_type, ""),
321 LLVMConstNull(reg_type), "i1cond");
|
| /xsrc/external/mit/MesaLib/dist/src/intel/tools/ |
| H A D | i965_gram.y | 351 enum brw_reg_type reg_type;
524 %type <reg_type> reg_type imm_type
1515 dstreg dstregion writemask reg_type
1529 dstoperandex_typed dstregion writemask reg_type
1541 | nullreg dstregion writemask reg_type
1648 directgenreg region reg_type
1677 | accreg region reg_type
1687 srcarcoperandex_typed region reg_type
1701 | nullreg region reg_type
2099 reg_type: label
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler_nir.h | 257 enum reg_type { enum
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/ |
| H A D | ir3_shader.c | 611 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r"; local in function:dump_reg
612 fprintf(out, "; %s: %s%d.%c\n", name, reg_type, (r & ~HALF_REG_ID) >> 2,
708 const char *reg_type = so->outputs[i].half ? "hr" : "r"; local in function:ir3_shader_disasm
709 fprintf(out, " %s%d.%c (%s)", reg_type, (regid >> 2), "xyzw"[regid & 0x3],
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_instruction_selection.cpp | 3829 RegType reg_type = RegType::sgpr; local in function:aco::__anon562fcc110110::emit_load
3832 reg_type = RegType::vgpr;
3841 tmp[0] = bld.tmp(RegClass::get(reg_type, tmp_size));
3850 RegClass::get(reg_type, tmp[0].bytes() / component_size * component_size);
3855 RegClass elem_rc = RegClass::get(reg_type, component_size);
4494 create_vec_from_array(isel_context* ctx, Temp arr[], unsigned cnt, RegType reg_type, argument
4501 dst = bld.tmp(RegClass(reg_type, cnt * dword_size));
4514 Temp zero = bld.copy(bld.def(RegClass(reg_type, dword_size)),
|