| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| radeon_pm.c | 772 atombios_set_engine_clock(pScrn, info->pm.mode[i].sclk);
774 RADEONSetEngineClock(pScrn, info->pm.mode[i].sclk);
796 info->pm.mode[0].sclk = (uint32_t)info->sclk * 100; /* 10 khz */
805 info->pm.mode[1].sclk = info->pm.mode[0].sclk / 4;
810 info->pm.mode[2].sclk = info->pm.mode[0].sclk;
827 info->pm.mode[2].sclk = info->pm.mode[0].sclk / 2
[all...] |
| atombios_crtc.c | 1166 * CORE_CLOCK_BANDWIDTH (Mbyte/s) = SCLK (MHz) * 16 / Dynamic Engine clock Divider
1176 float core_clock_bandwidth = ((float)info->pm.mode[info->pm.current_mode].sclk / 100) * 16 / 1;
1195 float pclk, sclk, sclkfreq = 0; local
1309 sclk = system clock(ns)
1312 sclk = 1000 / (available_bandwidth / 16);
1313 /* Sclkfreq = sclk in MHz = 1000/sclk (because sclk is in ns). */
1314 sclkfreq = 1000 / sclk;
1315 chunk_time = sclk * 256 * 1.3
[all...] |
| legacy_crtc.c | 1523 /* DDR64 SCLK_EFF = SCLK for analysis */
1524 sclk_eff = info->sclk;
1528 sclk_eff = info->sclk - (info->dri->agpMode * 50.0 / 3.0);
1531 sclk_eff = info->sclk;
1584 disp_latency_overhead = 8.0 / info->sclk;
1708 read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128));
|
| radeon_bios.c | 1016 info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0;
1020 if (info->sclk == 0) info->sclk = 200;
1026 "sclk: %f, mclk: %f\n",
1029 (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk);
|
| radeon.h | 429 uint32_t sclk; member in struct:__anon6810
861 float sclk; /* in MHz */ member in struct:__anon6814
|
| radeon_driver.c | 1186 * Calculate SCLK
1190 case 1: info->sclk = spll; break;
1191 case 2: info->sclk = spll / 2.0; break;
1192 case 3: info->sclk = spll / 4.0; break;
1193 case 4: info->sclk = spll / 8.0; break;
1194 case 7: info->sclk = mpll; break;
1196 info->sclk = 200.00;
1197 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source"
1198 " setting %d, can't probe SCLK value !\n", tmp);
1207 "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk)
[all...] |
| radeon_atombios.c | 1468 int engine_clk = (int)info->sclk * 100;
2280 info->sclk = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->ulDefaultEngineClock) / 100.0;
2293 info->sclk = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->ulDefaultEngineClock) / 100.0;
|
| /xsrc/external/mit/MesaLib/dist/include/drm-uapi/ |
| amdgpu_drm.h | 1086 __u32 sclk; member in struct:drm_amdgpu_info_vce_clock_table_entry
|
| /xsrc/external/mit/libdrm/dist/include/drm/ |
| amdgpu_drm.h | 1521 __u32 sclk; member in struct:drm_amdgpu_info_vce_clock_table_entry
|
