| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_shader_args.c | 34 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs) argument
36 ud_info->sgpr_idx = *sgpr_idx;
38 *sgpr_idx += num_sgprs;
42 set_loc_shader(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx, uint8_t num_sgprs) argument
47 set_loc(ud_info, sgpr_idx, num_sgprs);
51 set_loc_shader_ptr(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx) argument
55 set_loc_shader(args, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
59 set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx) argument
65 set_loc(ud_info, sgpr_idx,
[all...] |
| H A D | radv_cmd_buffer.c | 793 if (loc->sgpr_idx == -1)
798 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,
821 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
1015 if (loc->sgpr_idx == -1)
1020 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs);
2964 assert(loc->sgpr_idx != -1);
2966 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
3186 return loc->sgpr_idx != -1;
3476 if (loc->sgpr_idx == -1)
3481 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx *
[all...] |
| H A D | radv_shader.h | 179 int8_t sgpr_idx; member in struct:radv_userdata_info
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| H A D | radv_pipeline.c | 5447 return loc->sgpr_idx != -1;
5467 if (loc->sgpr_idx != -1) {
5469 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
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| H A D | radv_nir_to_llvm.c | 117 if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) {
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_shader.h | 229 int8_t sgpr_idx; member in struct:radv_userdata_info
|
| H A D | radv_cmd_buffer.c | 593 if (loc->sgpr_idx == -1)
599 base_reg + loc->sgpr_idx * 4, va, false);
623 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
643 if (loc->sgpr_idx == -1)
648 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
2060 if (loc->sgpr_idx == -1)
2066 base_reg + loc->sgpr_idx * 4, va, false);
2071 if (loc->sgpr_idx != -1) {
2075 base_reg + loc->sgpr_idx * 4, va, false);
3561 if (loc->sgpr_idx
[all...] |
| H A D | radv_nir_to_llvm.c | 549 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, argument
552 ud_info->sgpr_idx = *sgpr_idx;
554 *sgpr_idx += num_sgprs;
558 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx, argument
565 set_loc(ud_info, sgpr_idx, num_sgprs);
569 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx) argument
573 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
577 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx) argument
584 set_loc(ud_info, sgpr_idx,
[all...] |
| H A D | radv_pipeline.c | 3783 if (loc->sgpr_idx != -1) {
3785 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_optimizer.cpp | 2730 uint32_t sgpr_idx = 0; local in function:aco::apply_sgprs
2738 sgpr_idx = i;
2742 operand_mask &= ~(1u << sgpr_idx);
2758 if (sgpr_idx == 0)
2761 if (sgpr_idx == 0 || instr->isVOP3() || instr->isSDWA() || instr->isVOP3P() ||
2764 if (info.is_extract() && can_apply_extract(ctx, instr, sgpr_idx, info))
2765 apply_extract(ctx, instr, sgpr_idx, info);
2768 instr->operands[sgpr_idx] = Operand(sgpr);
2770 instr->operands[sgpr_idx] = instr->operands[0];
2777 instr->operands[sgpr_idx]
[all...] |
| H A D | aco_instruction_selection.cpp | 5358 if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) {
5532 unsigned num_inline_push_consts = loc->sgpr_idx != -1 ? loc->num_sgprs : 0;
|