| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.5.rst | 48 - pan/mdg: Mask spills from texture write
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| H A D | 20.0.0.rst | 320 - pan/midgard: Dynamically allocate r26/27 for spills
372 - pan/decode: Append 0:0 spills:fills to blobber-db
715 - aco: fix immediate offset for spills if scratch is used
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| H A D | 20.3.0.rst | 699 - pan/bi: Add spills/fills parameters
825 - broadcom/compiler: Allow spills of temporaries from TMU reads
2425 - v3d/compiler: allow to batch spills
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| H A D | 19.3.0.rst | 823 - aco: fix immediate offset for spills if scratch is used
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| /xsrc/external/mit/MesaLib/dist/src/asahi/compiler/ |
| H A D | agx_compiler.h | 397 unsigned spills; member in struct:__anon010094cb0408
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| H A D | agx_compile.c | 1094 "%u:%u spills:fills\n",
1097 ctx->spills, ctx->fills);
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| /xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/ |
| H A D | bi_ra.c | 471 ctx->spills++;
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| H A D | compiler.h | 642 unsigned spills; member in struct:__anon9a2e09911508
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| H A D | bifrost_compile.c | 3165 "%u:%u spills:fills\n",
3174 ctx->spills, ctx->fills);
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| /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/ |
| H A D | compiler.h | 255 /* Count of spills and fills for shaderdb */
256 unsigned spills; member in struct:compiler_context
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| H A D | midgard_ra.c | 953 ctx->spills++;
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| H A D | midgard_compile.c | 3280 "%u:%u spills:fills\n",
3287 ctx->spills, ctx->fills);
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| /xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/ |
| H A D | vir.c | 1585 "%d uniforms, %d max-temps, %d:%d spills:fills, "
1593 c->spills,
1735 c->spills > 0) {
1738 "Compiled %s with %d spills and %d fills",
1740 c->spills, c->fills);
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| H A D | vir_register_allocate.c | 156 * penalize spills during that time.
242 c->spills++;
336 /* spills */
553 /* Allow up to 10 spills in batches of 1 in any case to avoid any chance of
554 * over-spilling if the program requires few spills to compile.
560 * be great and we shift focus to batching spills to cut down compile
566 /* Don't emit spills using the TMU until we've dropped thread count first. We,
816 /* TMU spills inject thrsw signals that invalidate
829 /* See comment above about batching TMU spills.
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| H A D | v3d_compiler.h | 672 * TMU spills.
687 * spills.
703 /* Whether TMU spills are allowed. If this is disabled it may cause
706 * eliminate TMU spills in the shader.
763 uint32_t spills, fills, loops; member in struct:v3d_compile
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| H A D | nir_to_vir.c | 3920 * if we need to do any spills that inject additional thread switches later on,
4140 if (!c->spills && c->last_thrsw != restore_last_thrsw)
4143 if (c->spills &&
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| /xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/ |
| H A D | vir_register_allocate.c | 272 c->spills++;
651 /* Don't emit spills using the TMU until we've dropped thread
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| H A D | v3d_compiler.h | 552 uint32_t spills, fills, loops; member in struct:v3d_compile
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| H A D | vir.c | 940 "%d uniforms, %d max-temps, %d:%d spills:fills",
947 c->spills,
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| H A D | nir_to_vir.c | 2553 if (c->spills &&
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| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | brw_compiler.h | 1473 uint32_t spills; member in struct:brw_compile_stats
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| H A D | brw_fs_generator.cpp | 1907 /* `send_count` explicitly does not include spills or fills, as we'd
2772 "%d:%d spills:fills, %u sends, "
2804 "%d:%d spills:fills, %u sends, "
2821 stats->spills = spill_count;
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| H A D | brw_vec4_generator.cpp | 1533 /* `send_count` explicitly does not include spills or fills, as we'd
2250 "spills:fills, %u sends. Compacted %d to %d bytes (%.0f%%)\n",
2268 "%d:%d spills:fills, %u sends, "
2279 stats->spills = spill_count;
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| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| H A D | anv_pipeline.c | 3251 stat->value.u64 = exe->stats.spills;
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| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | 508 "description": "broadcom/compiler: fix register class patching for postponed spills",
1777 "description": "broadcom/compiler: document that spill_base is used for spills and scratch",
1822 "description": "broadcom/compiler: define max number of tmu spills for compile strategies",
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