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    Searched refs:src_offset (Results 1 - 25 of 330) sorted by relevancy

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  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
i915_blit.h 36 unsigned src_offset, unsigned short dst_pitch,
i915_blit.c 81 unsigned src_offset, unsigned short dst_pitch,
93 __FUNCTION__, src_buffer, src_pitch, src_offset, src_x, src_y,
138 OUT_RELOC_FENCED(src_buffer, I915_USAGE_2D_SOURCE, src_offset);
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
r200_blit.h 37 intptr_t src_offset,
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
radeon_blit.h 37 intptr_t src_offset,
radeon_tex_copy.c 84 intptr_t src_offset = rrb->draw_offset; local
92 x, y, rrb->base.Base.Width, rrb->base.Base.Height, (uint32_t) src_offset, rrb->pitch/rrb->cpp);
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp,
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
i915_blit.h 37 unsigned src_offset,
i915_blit.c 93 unsigned src_offset,
110 src_buffer, src_pitch, src_offset, src_x, src_y,
157 OUT_RELOC_FENCED(src_buffer, I915_USAGE_2D_SOURCE, src_offset);
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
r200_blit.h 37 intptr_t src_offset,
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
radeon_blit.h 37 intptr_t src_offset,
radeon_tex_copy.c 84 intptr_t src_offset = rrb->draw_offset; local
92 x, y, rrb->base.Base.Width, rrb->base.Base.Height, (uint32_t) src_offset, rrb->pitch/rrb->cpp);
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp,
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
evergreen_hw_context.c 35 uint64_t src_offset,
50 src_offset += rsrc->gpu_address;
53 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
71 radeon_emit(cs, src_offset & 0xffffffff);
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
75 src_offset += csize << shift;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
evergreen_hw_context.c 35 uint64_t src_offset,
50 src_offset += rsrc->gpu_address;
53 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
71 radeon_emit(cs, src_offset & 0xffffffff);
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
75 src_offset += csize << shift;
  /xsrc/external/mit/MesaLib/dist/src/panfrost/vulkan/
panvk_vX_descriptor_set.c 222 unsigned src_offset = 0; local
224 while (src_offset < pDescriptorWrite->descriptorCount &&
236 unsigned ndescs = MIN2(pDescriptorWrite->descriptorCount - src_offset,
246 const VkDescriptorImageInfo *info = &pDescriptorWrite->pImageInfo[src_offset + i];
268 panvk_set_image_desc(&descs[i], &pDescriptorWrite->pImageInfo[src_offset + i]);
274 panvk_set_texel_buffer_view_desc(&descs[i], &pDescriptorWrite->pTexelBufferView[src_offset + i]);
282 &pDescriptorWrite->pBufferInfo[src_offset + i]);
289 panvk_set_buffer_info_desc(&descs[i], &pDescriptorWrite->pBufferInfo[src_offset + i]);
295 src_offset += ndescs;
310 unsigned src_offset = pDescriptorCopy->srcArrayElement local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_pixel_draw.c 59 GLuint src_offset; local
107 src_offset = (GLintptr)pixels;
108 src_offset += _mesa_image_offset(2, unpack, width, height,
111 src_buffer = brw_bufferobj_buffer(brw, src, src_offset,
118 src_offset,
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
intel_pixel_draw.c 59 GLuint src_offset; local
107 src_offset = (GLintptr)pixels;
108 src_offset += _mesa_image_offset(2, unpack, width, height,
111 src_buffer = intel_bufferobj_buffer(brw, src, src_offset,
118 src_offset,
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
intel_blit.h 64 unsigned int src_offset,
intel_blit.c 82 GLuint src_offset,
106 if (src_offset & 4095)
131 src_buffer, src_pitch, src_offset, src_x, src_y,
137 if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
193 src_offset);
578 unsigned int src_offset,
592 pitch, src_bo, src_offset, I915_TILING_NONE,
601 src_offset += pitch * height;
608 pitch, src_bo, src_offset, I915_TILING_NONE,
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
intel_blit.h 64 unsigned int src_offset,
intel_blit.c 82 GLuint src_offset,
106 if (src_offset & 4095)
131 src_buffer, src_pitch, src_offset, src_x, src_y,
137 if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
193 src_offset);
578 unsigned int src_offset,
592 pitch, src_bo, src_offset, I915_TILING_NONE,
601 src_offset += pitch * height;
608 pitch, src_bo, src_offset, I915_TILING_NONE,
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
si_dma.c 35 uint64_t src_offset,
50 src_offset += ssrc->gpu_address;
53 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
71 radeon_emit(cs, src_offset);
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
75 src_offset += count;
259 uint64_t dst_offset, src_offset; local
265 src_offset= ssrc->surface.u.legacy.level[src_level].offset;
266 src_offset += (uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
267 src_offset += src_y * src_pitch + src_x * bpp
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/kernel/
vc4_validate.c 479 uint32_t src_offset = 0; local
481 while (src_offset < len) {
483 void *src_pkt = unvalidated + src_offset;
489 src_offset, cmd);
496 src_offset, cmd);
500 if (src_offset + info->len > len) {
503 src_offset, cmd, info->name, info->len,
504 src_offset + len);
515 src_offset, cmd, info->name);
519 src_offset += info->len
814 uint32_t src_offset = *(uint32_t *)(pkt_u + o); local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/kernel/
vc4_validate.c 479 uint32_t src_offset = 0; local
481 while (src_offset < len) {
483 void *src_pkt = unvalidated + src_offset;
489 src_offset, cmd);
496 src_offset, cmd);
500 if (src_offset + info->len > len) {
503 src_offset, cmd, info->name, info->len,
504 src_offset + len);
515 src_offset, cmd, info->name);
519 src_offset += info->len
814 uint32_t src_offset = *(uint32_t *)(pkt_u + o); local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
radv_meta_resolve_cs.c 105 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); local
106 nir_intrinsic_set_base(src_offset, 0);
107 nir_intrinsic_set_range(src_offset, 16);
108 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
109 src_offset->num_components = 2;
110 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
111 nir_builder_instr_insert(&b, &src_offset->instr);
121 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3)
    [all...]
radv_meta_resolve_fs.c 82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); local
83 nir_intrinsic_set_base(src_offset, 0);
84 nir_intrinsic_set_range(src_offset, 8);
85 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
86 src_offset->num_components = 2;
87 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
88 nir_builder_instr_insert(&b, &src_offset->instr);
92 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
svga_state_vdecl.c 73 unsigned int offset = vb->buffer_offset + ve[i].src_offset;
112 + ve[i].src_offset

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