Searched refs:start_idx (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
H A Dnir_lower_vec_to_movs.c56 insert_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader) argument
58 assert(start_idx < nir_op_infos[vec->op].num_inputs);
61 nir_alu_src_copy(&mov->src[0], &vec->src[start_idx], mov);
64 mov->dest.write_mask = (1u << start_idx);
65 mov->src[0].swizzle[start_idx] = vec->src[start_idx].swizzle[0];
66 mov->src[0].negate = vec->src[start_idx].negate;
67 mov->src[0].abs = vec->src[start_idx].abs;
69 for (unsigned i = start_idx + 1; i < 4; i++) {
73 if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx]
121 try_coalesce(nir_alu_instr * vec,unsigned start_idx) argument
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/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_lower_vec_to_movs.c62 insert_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader) argument
64 assert(start_idx < nir_op_infos[vec->op].num_inputs);
67 if (nir_src_is_undef(vec->src[start_idx].src))
68 return 1 << start_idx;
71 nir_alu_src_copy(&mov->src[0], &vec->src[start_idx]);
74 mov->dest.write_mask = (1u << start_idx);
75 mov->src[0].swizzle[start_idx] = vec->src[start_idx].swizzle[0];
76 mov->src[0].negate = vec->src[start_idx].negate;
77 mov->src[0].abs = vec->src[start_idx]
131 try_coalesce(nir_alu_instr * vec,unsigned start_idx,void * _data) argument
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H A Dnir_lower_bool_to_bitsize.c58 make_sources_canonical(nir_builder *b, nir_alu_instr *alu, uint32_t start_idx) argument
64 uint32_t bit_size = nir_src_bit_size(alu->src[start_idx].src);
65 for (uint32_t i = start_idx + 1; i < op_info->num_inputs; i++) {
/xsrc/external/mit/freetype/dist/src/psaux/
H A Dpsstack.c249 CF2_Int start_idx, idx, i; local in function:cf2_stack_roll
297 start_idx = -1;
304 if ( start_idx == idx )
306 start_idx++;
307 idx = start_idx;
/xsrc/external/mit/MesaLib/dist/src/util/perf/
H A Du_trace.c536 uint32_t start_idx = begin_it.event_idx; local in function:u_trace_disable_event_range
539 memset(&current_chunk->traces[start_idx], 0,
540 (current_chunk->num_traces - start_idx) * sizeof(struct u_trace_event));
541 start_idx = 0;
545 memset(&current_chunk->traces[start_idx], 0,
546 (end_it.event_idx - start_idx) * sizeof(struct u_trace_event));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir.c684 insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader) argument
686 assert(start_idx < nir_op_infos[vec->op].num_inputs);
687 unsigned write_mask = (1u << start_idx);
690 nir_alu_src_copy(&mov->src[0], &vec->src[start_idx]);
692 mov->src[0].swizzle[0] = vec->src[start_idx].swizzle[0];
693 mov->src[0].negate = vec->src[start_idx].negate;
694 mov->src[0].abs = vec->src[start_idx].abs;
698 for (unsigned i = start_idx + 1; i < 4; i++) {
702 if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx].src) &&
703 vec->src[i].negate == vec->src[start_idx]
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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_assembler.cpp755 int start_idx = out.size();
762 for (int i = start_idx; i < out.size(); i++)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/panfrost/midgard/
H A Dmidgard_compile.c3724 int start_idx = ctx->block_count; local in function:emit_loop
3731 br_back.branch.target_block = start_idx;
/xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/
H A Dmidgard_compile.c2888 int start_idx = ctx->block_count; local in function:emit_loop
2895 br_back.branch.target_block = start_idx;

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